* [PATCH] drm/amdgpu: fix bug with IH ring setup
@ 2018-11-12 19:20 Yang, Philip
[not found] ` <1542050408-19731-1-git-send-email-Philip.Yang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Yang, Philip @ 2018-11-12 19:20 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Yang, Philip
The bug limits the IH ring wptr address to 40bit. When the system memory
is bigger than 1TB, the bus address is more than 40bit, this causes the
interrupt cannot be handled and cleared correctly.
Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index a99f717..a0fda6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
else
wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread[parent not found: <1542050408-19731-1-git-send-email-Philip.Yang-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: fix bug with IH ring setup [not found] ` <1542050408-19731-1-git-send-email-Philip.Yang-5C7GfCeVMHo@public.gmane.org> @ 2018-11-12 19:33 ` Deucher, Alexander [not found] ` <BN6PR12MB18094950A3FC8AA193D0A821F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 3+ messages in thread From: Deucher, Alexander @ 2018-11-12 19:33 UTC (permalink / raw) To: Yang, Philip, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org [-- Attachment #1.1: Type: text/plain, Size: 1815 bytes --] Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org> ________________________________ From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Yang, Philip <Philip.Yang-5C7GfCeVMHo@public.gmane.org> Sent: Monday, November 12, 2018 2:20 PM To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Yang, Philip Subject: [PATCH] drm/amdgpu: fix bug with IH ring setup The bug limits the IH ring wptr address to 40bit. When the system memory is bigger than 1TB, the bus address is more than 40bit, this causes the interrupt cannot be handled and cleared correctly. Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28 Signed-off-by: Philip Yang <Philip.Yang-5C7GfCeVMHo@public.gmane.org> --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index a99f717..a0fda6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) else wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF); /* set rptr, wptr to 0 */ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 3413 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <BN6PR12MB18094950A3FC8AA193D0A821F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: fix bug with IH ring setup [not found] ` <BN6PR12MB18094950A3FC8AA193D0A821F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2018-11-13 8:06 ` Christian König 0 siblings, 0 replies; 3+ messages in thread From: Christian König @ 2018-11-13 8:06 UTC (permalink / raw) To: Deucher, Alexander, Yang, Philip, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org [-- Attachment #1.1: Type: text/plain, Size: 2242 bytes --] Reviewed-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org> Am 12.11.18 um 20:33 schrieb Deucher, Alexander: > > Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org> > > > > ------------------------------------------------------------------------ > *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of > Yang, Philip <Philip.Yang-5C7GfCeVMHo@public.gmane.org> > *Sent:* Monday, November 12, 2018 2:20 PM > *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > *Cc:* Yang, Philip > *Subject:* [PATCH] drm/amdgpu: fix bug with IH ring setup > The bug limits the IH ring wptr address to 40bit. When the system memory > is bigger than 1TB, the bus address is more than 40bit, this causes the > interrupt cannot be handled and cleared correctly. > > Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28 > Signed-off-by: Philip Yang <Philip.Yang-5C7GfCeVMHo@public.gmane.org> > --- > drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > index a99f717..a0fda6f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > @@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device > *adev) > else > wptr_off = adev->wb.gpu_addr + > (adev->irq.ih.wptr_offs * 4); > WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, > lower_32_bits(wptr_off)); > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, > upper_32_bits(wptr_off) & 0xFF); > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, > upper_32_bits(wptr_off) & 0xFFFF); > > /* set rptr, wptr to 0 */ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 5862 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-11-12 19:20 [PATCH] drm/amdgpu: fix bug with IH ring setup Yang, Philip
[not found] ` <1542050408-19731-1-git-send-email-Philip.Yang-5C7GfCeVMHo@public.gmane.org>
2018-11-12 19:33 ` Deucher, Alexander
[not found] ` <BN6PR12MB18094950A3FC8AA193D0A821F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-11-13 8:06 ` Christian König
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