* [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM
@ 2025-12-01 14:28 Philip Yang
2025-12-01 14:28 ` [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW Philip Yang
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: Philip Yang @ 2025-12-01 14:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Felix.Kuehling, christian.koenig, david.yatsin, Philip Yang
To reduce multiple queues switch latency, move user queues MQD to HBM,
and map on GART with mtype RW.
v2: patch 4 GART mapping use MC address, vram_base_offset + physical address
Philip Yang (4):
drm/amdkfd: Bind gfx9 MQD in GART with mtype RW
drm/amdkfd: Add domain parameter to alloc kernel BO
drm/amdkfd: Move gfx9 MQD to VRAM domain
drm/amdkfd: Map VRAM MQD on GART
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 9 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 115 +++++++++++++++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 9 ++
.../amd/amdkfd/kfd_process_queue_manager.c | 2 +
12 files changed, 124 insertions(+), 24 deletions(-)
--
2.50.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW
2025-12-01 14:28 [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
@ 2025-12-01 14:28 ` Philip Yang
2025-12-03 17:40 ` Kuehling, Felix
2025-12-01 14:28 ` [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
` (3 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Philip Yang @ 2025-12-01 14:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Felix.Kuehling, christian.koenig, david.yatsin, Philip Yang
For gfx9, bind MQD in GART with mtype RW to enable caching, to
reduce queue switch latency.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e553cf411191..5f58cff2c28b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -841,6 +841,8 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
int i;
uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
+ flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_RW);
+
pages_per_xcc = total_pages;
do_div(pages_per_xcc, num_xcc);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 139642eacdd0..4dd15767a722 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -101,6 +101,7 @@ struct amdgpu_bo_vm;
AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))
#define AMDGPU_MTYPE_NC 0
+#define AMDGPU_MTYPE_RW 1
#define AMDGPU_MTYPE_CC 2
#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
--
2.50.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
2025-12-01 14:28 [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
2025-12-01 14:28 ` [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW Philip Yang
@ 2025-12-01 14:28 ` Philip Yang
2025-12-01 17:38 ` Russell, Kent
2025-12-01 14:28 ` [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain Philip Yang
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Philip Yang @ 2025-12-01 14:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Felix.Kuehling, christian.koenig, david.yatsin, Philip Yang
To allocate kernel BO from VRAM domain for MQD in the following patch.
No functional change because kernel BO allocate are all from GTT domain so far.
amdgpu_amdkfd_alloc_gtt_mem has many duplicate code as
function amdgpu_bo_create_kernel, with one extra flag MQD_GFX9
to bind MQD and control stack in GART with different mtype,
the duplicate code could be removed in future.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 ++
7 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index a2879d2b7c8e..9cd1660b8f60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -317,7 +317,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
}
int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
- void **mem_obj, uint64_t *gpu_addr,
+ u32 domain, void **mem_obj, uint64_t *gpu_addr,
void **cpu_ptr, bool cp_mqd_gfx9)
{
struct amdgpu_bo *bo = NULL;
@@ -328,7 +328,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
memset(&bp, 0, sizeof(bp));
bp.size = size;
bp.byte_align = PAGE_SIZE;
- bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+ bp.domain = domain;
bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
@@ -351,7 +351,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
goto allocate_mem_reserve_bo_failed;
}
- r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
+ r = amdgpu_bo_pin(bo, domain);
if (r) {
dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
goto allocate_mem_pin_bo_failed;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 335d733751cb..14b5ab6fa051 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -237,7 +237,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
#endif
/* Shared API */
int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
- void **mem_obj, uint64_t *gpu_addr,
+ u32 domain, void **mem_obj, uint64_t *gpu_addr,
void **cpu_ptr, bool mqd_gfx9);
void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj);
int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index ba9a09b6589a..494a563e072e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -359,6 +359,7 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)
if (!pdd->proc_ctx_cpu_ptr) {
r = amdgpu_amdkfd_alloc_gtt_mem(adev,
AMDGPU_MES_PROC_CTX_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
&pdd->proc_ctx_bo,
&pdd->proc_ctx_gpu_addr,
&pdd->proc_ctx_cpu_ptr,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 9f183d27a0ef..b0cfad750919 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -787,7 +787,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
size += 512 * 1024;
if (amdgpu_amdkfd_alloc_gtt_mem(
- kfd->adev, size, &kfd->gtt_mem,
+ kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT,
+ &kfd->gtt_mem,
&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
false)) {
dev_err(kfd_device, "Could not allocate %d bytes\n", size);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 36ac35d64126..028fca1d2755 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -2906,6 +2906,7 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
NUM_XCC(dqm->dev->xcc_mask));
retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
+ AMDGPU_GEM_DOMAIN_GTT,
&(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
(void *)&(mem_obj->cpu_ptr), false);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index 2e9b6bcf2704..a489d43d5f64 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -139,6 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
(ALIGN(q->ctl_stack_size, PAGE_SIZE) +
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
NUM_XCC(node->xcc_mask),
+ AMDGPU_GEM_DOMAIN_GTT,
&(mqd_mem_obj->gtt_mem),
&(mqd_mem_obj->gpu_addr),
(void *)&(mqd_mem_obj->cpu_ptr), true);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 5f8cda4733f9..e0c5ec7e2fe9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -266,6 +266,7 @@ static int init_user_queue(struct process_queue_manager *pqm,
if (dev->kfd->shared_resources.enable_mes) {
retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
AMDGPU_MES_GANG_CTX_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
&(*q)->gang_ctx_bo,
&(*q)->gang_ctx_gpu_addr,
&(*q)->gang_ctx_cpu_ptr,
@@ -369,6 +370,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) {
retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
AMDGPU_MES_PROC_CTX_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
&pdd->proc_ctx_bo,
&pdd->proc_ctx_gpu_addr,
&pdd->proc_ctx_cpu_ptr,
--
2.50.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain
2025-12-01 14:28 [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
2025-12-01 14:28 ` [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW Philip Yang
2025-12-01 14:28 ` [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
@ 2025-12-01 14:28 ` Philip Yang
2025-12-03 17:55 ` Kuehling, Felix
2025-12-01 14:28 ` [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART Philip Yang
2025-12-03 15:52 ` [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
4 siblings, 1 reply; 20+ messages in thread
From: Philip Yang @ 2025-12-01 14:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Felix.Kuehling, christian.koenig, david.yatsin, Philip Yang
To reduce queue switch latency further, move MQD to VRAM domain, add
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag to allocate contiguous pages
using one buddy block.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 9cd1660b8f60..c11e37915365 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
bp.size = size;
bp.byte_align = PAGE_SIZE;
bp.domain = domain;
- bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+ AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index a489d43d5f64..c6945c842267 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -139,7 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
(ALIGN(q->ctl_stack_size, PAGE_SIZE) +
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
NUM_XCC(node->xcc_mask),
- AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_GEM_DOMAIN_VRAM,
&(mqd_mem_obj->gtt_mem),
&(mqd_mem_obj->gpu_addr),
(void *)&(mqd_mem_obj->cpu_ptr), true);
--
2.50.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART
2025-12-01 14:28 [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
` (2 preceding siblings ...)
2025-12-01 14:28 ` [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain Philip Yang
@ 2025-12-01 14:28 ` Philip Yang
2025-12-03 16:06 ` Christian König
2025-12-03 15:52 ` [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
4 siblings, 1 reply; 20+ messages in thread
From: Philip Yang @ 2025-12-01 14:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Felix.Kuehling, christian.koenig, david.yatsin, Philip Yang
MQD BO on VRAM access via FB aperture is mtype UC uncaching, map to GART
as mtype RW caching, to reduce queue switch latency.
TTM bo only has one resource, add GART resource to amdgpu_bo in order to
support dynamic GART resource and VRAM BO resource.
Update amdgpu_ttm_gart_bind_gfx9_mqd to map MQD in system or VRAM.
Add helper amdgpu_ttm_alloc_gart_for_vram_bo to alloc GART entries resource
for MQD bo->gart_res and bind to GART mapping.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 113 +++++++++++++++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 8 ++
5 files changed, 108 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 926a3f09a776..d267456cd181 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1297,6 +1297,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
abo = ttm_to_amdgpu_bo(bo);
+ if (abo->gart_res)
+ ttm_resource_free(bo, &abo->gart_res);
+
WARN_ON(abo->vm_bo);
if (abo->kfd_bo)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 52c2d1731aab..a412f5ec2a09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -106,6 +106,7 @@ struct amdgpu_bo {
struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
struct ttm_placement placement;
struct ttm_buffer_object tbo;
+ struct ttm_resource *gart_res;
struct ttm_bo_kmap_obj kmap;
u64 flags;
/* per VM structure for page tables and with virtual addresses */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 5f58cff2c28b..1d8f5fc66acc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -832,14 +832,27 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
* Ctrl stack and modify their memory type to NC.
*/
static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
- struct ttm_tt *ttm, uint64_t flags)
+ struct ttm_buffer_object *tbo,
+ uint64_t flags)
{
+ struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
+ struct ttm_tt *ttm = tbo->ttm;
struct amdgpu_ttm_tt *gtt = (void *)ttm;
- uint64_t total_pages = ttm->num_pages;
+ uint64_t total_pages;
int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
uint64_t page_idx, pages_per_xcc;
- int i;
uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
+ int i;
+
+ if (!ttm && !abo->gart_res)
+ return;
+
+ if (ttm) {
+ total_pages = ttm->num_pages;
+ } else {
+ WARN_ON_ONCE(abo->gart_res->size != tbo->resource->size);
+ total_pages = (abo->gart_res->size) >> PAGE_SHIFT;
+ }
flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_RW);
@@ -847,19 +860,33 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
do_div(pages_per_xcc, num_xcc);
for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
- /* MQD page: use default flags */
- amdgpu_gart_bind(adev,
- gtt->offset + (page_idx << PAGE_SHIFT),
- 1, >t->ttm.dma_address[page_idx], flags);
- /*
- * Ctrl pages - modify the memory type to NC (ctrl_flags) from
- * the second page of the BO onward.
- */
- amdgpu_gart_bind(adev,
- gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
- pages_per_xcc - 1,
- >t->ttm.dma_address[page_idx + 1],
- ctrl_flags);
+ if (ttm) {
+ /* MQD page: use default flags */
+ amdgpu_gart_bind(adev,
+ gtt->offset + (page_idx << PAGE_SHIFT),
+ 1, >t->ttm.dma_address[page_idx], flags);
+ /*
+ * Ctrl pages - modify the memory type to NC (ctrl_flags) from
+ * the second page of the BO onward.
+ */
+ amdgpu_gart_bind(adev,
+ gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
+ pages_per_xcc - 1,
+ >t->ttm.dma_address[page_idx + 1],
+ ctrl_flags);
+ } else {
+ u64 pa = (tbo->resource->start + page_idx) << PAGE_SHIFT;
+ u64 start_page = abo->gart_res->start + page_idx;
+
+ pa += adev->vm_manager.vram_base_offset;
+ amdgpu_gart_map_vram_range(adev, pa, start_page, 1,
+ flags, NULL);
+
+ amdgpu_gart_map_vram_range(adev, pa + PAGE_SIZE,
+ start_page + 1,
+ pages_per_xcc - 1,
+ ctrl_flags, NULL);
+ }
}
}
@@ -875,12 +902,14 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
flags |= AMDGPU_PTE_TMZ;
if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
- amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
+ amdgpu_ttm_gart_bind_gfx9_mqd(adev, tbo, flags);
} else {
amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
gtt->ttm.dma_address, flags);
}
- gtt->bound = true;
+
+ if (ttm)
+ gtt->bound = true;
}
/*
@@ -1000,6 +1029,54 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
return 0;
}
+int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo,
+ u64 *gpu_addr)
+{
+ struct ttm_buffer_object *bo = &abo->tbo;
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
+ struct ttm_operation_ctx ctx = { false, false };
+ struct ttm_placement placement;
+ struct ttm_place placements;
+ struct ttm_resource *res;
+ uint64_t flags;
+ int r;
+
+ /* Only for valid VRAM bo resource */
+ if (bo->resource->start == AMDGPU_BO_INVALID_OFFSET)
+ return 0;
+
+ r = amdgpu_bo_reserve(abo, false);
+ if (unlikely(r))
+ return r;
+
+ /* allocate GART space */
+ placement.num_placement = 1;
+ placement.placement = &placements;
+ placements.fpfn = 0;
+ placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
+ placements.mem_type = TTM_PL_TT;
+ placements.flags = bo->resource->placement;
+
+ r = ttm_bo_mem_space(bo, &placement, &res, &ctx);
+ if (unlikely(r))
+ goto out_unreserve;
+
+ /* compute PTE flags for this buffer object */
+ flags = amdgpu_ttm_tt_pte_flags(adev, NULL, bo->resource);
+
+ /* Bind VRAM pages */
+ abo->gart_res = res;
+
+ amdgpu_ttm_gart_bind(adev, bo, flags);
+ amdgpu_gart_invalidate_tlb(adev);
+
+ *gpu_addr = res->start << PAGE_SHIFT;
+
+out_unreserve:
+ amdgpu_bo_unreserve(abo);
+ return r;
+}
+
/*
* amdgpu_ttm_recover_gart - Rebind GTT pages
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 15e659575087..707654732759 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -179,6 +179,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
u64 k_job_id);
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
+int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo, u64 *gpu_addr);
void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index c6945c842267..d96de02c6bb9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -148,6 +148,14 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
kfree(mqd_mem_obj);
return NULL;
}
+
+ retval = amdgpu_ttm_alloc_gart_vram_bo(mqd_mem_obj->gtt_mem,
+ &(mqd_mem_obj->gpu_addr));
+ if (retval) {
+ amdgpu_amdkfd_free_gtt_mem(node->adev, &(mqd_mem_obj->gtt_mem));
+ kfree(mqd_mem_obj);
+ return NULL;
+ }
} else {
retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd),
&mqd_mem_obj);
--
2.50.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* RE: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
2025-12-01 14:28 ` [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
@ 2025-12-01 17:38 ` Russell, Kent
2025-12-01 20:31 ` Philip Yang
0 siblings, 1 reply; 20+ messages in thread
From: Russell, Kent @ 2025-12-01 17:38 UTC (permalink / raw)
To: Yang, Philip, amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix, Koenig, Christian, Yat Sin, David, Yang, Philip
[Public]
I know that it makes the change more complicated, but should we be renaming the function since we're no longer guaranteeing a GTT memory allocation in the alloc_gtt_mem function?
Kent
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Philip Yang
> Sent: Monday, December 1, 2025 9:29 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian
> <Christian.Koenig@amd.com>; Yat Sin, David <David.YatSin@amd.com>; Yang,
> Philip <Philip.Yang@amd.com>
> Subject: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
>
> To allocate kernel BO from VRAM domain for MQD in the following patch.
> No functional change because kernel BO allocate are all from GTT domain so far.
>
> amdgpu_amdkfd_alloc_gtt_mem has many duplicate code as
> function amdgpu_bo_create_kernel, with one extra flag MQD_GFX9
> to bind MQD and control stack in GART with different mtype,
> the duplicate code could be removed in future.
>
> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 ++
> 7 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index a2879d2b7c8e..9cd1660b8f60 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -317,7 +317,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device
> *adev)
> }
>
> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
> - void **mem_obj, uint64_t *gpu_addr,
> + u32 domain, void **mem_obj, uint64_t *gpu_addr,
> void **cpu_ptr, bool cp_mqd_gfx9)
> {
> struct amdgpu_bo *bo = NULL;
> @@ -328,7 +328,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device
> *adev, size_t size,
> memset(&bp, 0, sizeof(bp));
> bp.size = size;
> bp.byte_align = PAGE_SIZE;
> - bp.domain = AMDGPU_GEM_DOMAIN_GTT;
> + bp.domain = domain;
> bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> bp.type = ttm_bo_type_kernel;
> bp.resv = NULL;
> @@ -351,7 +351,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device
> *adev, size_t size,
> goto allocate_mem_reserve_bo_failed;
> }
>
> - r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
> + r = amdgpu_bo_pin(bo, domain);
> if (r) {
> dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
> goto allocate_mem_pin_bo_failed;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 335d733751cb..14b5ab6fa051 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -237,7 +237,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct
> amdgpu_bo *bo,
> #endif
> /* Shared API */
> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
> - void **mem_obj, uint64_t *gpu_addr,
> + u32 domain, void **mem_obj, uint64_t *gpu_addr,
> void **cpu_ptr, bool mqd_gfx9);
> void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj);
> int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> index ba9a09b6589a..494a563e072e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> @@ -359,6 +359,7 @@ int kfd_dbg_set_mes_debug_mode(struct
> kfd_process_device *pdd, bool sq_trap_en)
> if (!pdd->proc_ctx_cpu_ptr) {
> r = amdgpu_amdkfd_alloc_gtt_mem(adev,
> AMDGPU_MES_PROC_CTX_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> &pdd->proc_ctx_bo,
> &pdd->proc_ctx_gpu_addr,
> &pdd->proc_ctx_cpu_ptr,
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 9f183d27a0ef..b0cfad750919 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -787,7 +787,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
> size += 512 * 1024;
>
> if (amdgpu_amdkfd_alloc_gtt_mem(
> - kfd->adev, size, &kfd->gtt_mem,
> + kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT,
> + &kfd->gtt_mem,
> &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
> false)) {
> dev_err(kfd_device, "Could not allocate %d bytes\n", size);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 36ac35d64126..028fca1d2755 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -2906,6 +2906,7 @@ static int allocate_hiq_sdma_mqd(struct
> device_queue_manager *dqm)
> NUM_XCC(dqm->dev->xcc_mask));
>
> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
> + AMDGPU_GEM_DOMAIN_GTT,
> &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
> (void *)&(mem_obj->cpu_ptr), false);
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> index 2e9b6bcf2704..a489d43d5f64 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> @@ -139,6 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node
> *node,
> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
> NUM_XCC(node->xcc_mask),
> + AMDGPU_GEM_DOMAIN_GTT,
> &(mqd_mem_obj->gtt_mem),
> &(mqd_mem_obj->gpu_addr),
> (void *)&(mqd_mem_obj->cpu_ptr), true);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> index 5f8cda4733f9..e0c5ec7e2fe9 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> @@ -266,6 +266,7 @@ static int init_user_queue(struct process_queue_manager
> *pqm,
> if (dev->kfd->shared_resources.enable_mes) {
> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
> AMDGPU_MES_GANG_CTX_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> &(*q)->gang_ctx_bo,
> &(*q)->gang_ctx_gpu_addr,
> &(*q)->gang_ctx_cpu_ptr,
> @@ -369,6 +370,7 @@ int pqm_create_queue(struct process_queue_manager
> *pqm,
> if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) {
> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
> AMDGPU_MES_PROC_CTX_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> &pdd->proc_ctx_bo,
> &pdd->proc_ctx_gpu_addr,
> &pdd->proc_ctx_cpu_ptr,
> --
> 2.50.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
2025-12-01 17:38 ` Russell, Kent
@ 2025-12-01 20:31 ` Philip Yang
2025-12-01 22:48 ` Russell, Kent
2025-12-03 17:45 ` Kuehling, Felix
0 siblings, 2 replies; 20+ messages in thread
From: Philip Yang @ 2025-12-01 20:31 UTC (permalink / raw)
To: Russell, Kent, Yang, Philip, amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix, Koenig, Christian, Yat Sin, David
On 2025-12-01 12:38, Russell, Kent wrote:
> [Public]
>
> I know that it makes the change more complicated, but should we be renaming the function since we're no longer guaranteeing a GTT memory allocation in the alloc_gtt_mem function?
yes, you are right, I have the patch to
s/alloc_gtt_mem/alloc_kernel_mem/g, s/free_gtt_mem/free_kernel_mem/g,
and found it is too much changes, not related to the purpose of this
patch series, so I dropped that patch. We can cleanup this in the
followup patch, probably remove the alloc/free_gtt_mem functions and use
amdgpu_bo_create_kernel instead.
Regards,
Philip
>
> Kent
>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Philip Yang
>> Sent: Monday, December 1, 2025 9:29 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian
>> <Christian.Koenig@amd.com>; Yat Sin, David <David.YatSin@amd.com>; Yang,
>> Philip <Philip.Yang@amd.com>
>> Subject: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
>>
>> To allocate kernel BO from VRAM domain for MQD in the following patch.
>> No functional change because kernel BO allocate are all from GTT domain so far.
>>
>> amdgpu_amdkfd_alloc_gtt_mem has many duplicate code as
>> function amdgpu_bo_create_kernel, with one extra flag MQD_GFX9
>> to bind MQD and control stack in GART with different mtype,
>> the duplicate code could be removed in future.
>>
>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
>> drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 +
>> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
>> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
>> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 +
>> drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 ++
>> 7 files changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> index a2879d2b7c8e..9cd1660b8f60 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> @@ -317,7 +317,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device
>> *adev)
>> }
>>
>> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
>> - void **mem_obj, uint64_t *gpu_addr,
>> + u32 domain, void **mem_obj, uint64_t *gpu_addr,
>> void **cpu_ptr, bool cp_mqd_gfx9)
>> {
>> struct amdgpu_bo *bo = NULL;
>> @@ -328,7 +328,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device
>> *adev, size_t size,
>> memset(&bp, 0, sizeof(bp));
>> bp.size = size;
>> bp.byte_align = PAGE_SIZE;
>> - bp.domain = AMDGPU_GEM_DOMAIN_GTT;
>> + bp.domain = domain;
>> bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>> bp.type = ttm_bo_type_kernel;
>> bp.resv = NULL;
>> @@ -351,7 +351,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device
>> *adev, size_t size,
>> goto allocate_mem_reserve_bo_failed;
>> }
>>
>> - r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
>> + r = amdgpu_bo_pin(bo, domain);
>> if (r) {
>> dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
>> goto allocate_mem_pin_bo_failed;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> index 335d733751cb..14b5ab6fa051 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> @@ -237,7 +237,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct
>> amdgpu_bo *bo,
>> #endif
>> /* Shared API */
>> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
>> - void **mem_obj, uint64_t *gpu_addr,
>> + u32 domain, void **mem_obj, uint64_t *gpu_addr,
>> void **cpu_ptr, bool mqd_gfx9);
>> void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj);
>> int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>> index ba9a09b6589a..494a563e072e 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>> @@ -359,6 +359,7 @@ int kfd_dbg_set_mes_debug_mode(struct
>> kfd_process_device *pdd, bool sq_trap_en)
>> if (!pdd->proc_ctx_cpu_ptr) {
>> r = amdgpu_amdkfd_alloc_gtt_mem(adev,
>> AMDGPU_MES_PROC_CTX_SIZE,
>> + AMDGPU_GEM_DOMAIN_GTT,
>> &pdd->proc_ctx_bo,
>> &pdd->proc_ctx_gpu_addr,
>> &pdd->proc_ctx_cpu_ptr,
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>> index 9f183d27a0ef..b0cfad750919 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>> @@ -787,7 +787,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
>> size += 512 * 1024;
>>
>> if (amdgpu_amdkfd_alloc_gtt_mem(
>> - kfd->adev, size, &kfd->gtt_mem,
>> + kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT,
>> + &kfd->gtt_mem,
>> &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
>> false)) {
>> dev_err(kfd_device, "Could not allocate %d bytes\n", size);
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>> index 36ac35d64126..028fca1d2755 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>> @@ -2906,6 +2906,7 @@ static int allocate_hiq_sdma_mqd(struct
>> device_queue_manager *dqm)
>> NUM_XCC(dqm->dev->xcc_mask));
>>
>> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
>> + AMDGPU_GEM_DOMAIN_GTT,
>> &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
>> (void *)&(mem_obj->cpu_ptr), false);
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> index 2e9b6bcf2704..a489d43d5f64 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> @@ -139,6 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node
>> *node,
>> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
>> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
>> NUM_XCC(node->xcc_mask),
>> + AMDGPU_GEM_DOMAIN_GTT,
>> &(mqd_mem_obj->gtt_mem),
>> &(mqd_mem_obj->gpu_addr),
>> (void *)&(mqd_mem_obj->cpu_ptr), true);
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>> index 5f8cda4733f9..e0c5ec7e2fe9 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>> @@ -266,6 +266,7 @@ static int init_user_queue(struct process_queue_manager
>> *pqm,
>> if (dev->kfd->shared_resources.enable_mes) {
>> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
>> AMDGPU_MES_GANG_CTX_SIZE,
>> + AMDGPU_GEM_DOMAIN_GTT,
>> &(*q)->gang_ctx_bo,
>> &(*q)->gang_ctx_gpu_addr,
>> &(*q)->gang_ctx_cpu_ptr,
>> @@ -369,6 +370,7 @@ int pqm_create_queue(struct process_queue_manager
>> *pqm,
>> if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) {
>> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
>> AMDGPU_MES_PROC_CTX_SIZE,
>> + AMDGPU_GEM_DOMAIN_GTT,
>> &pdd->proc_ctx_bo,
>> &pdd->proc_ctx_gpu_addr,
>> &pdd->proc_ctx_cpu_ptr,
>> --
>> 2.50.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
2025-12-01 20:31 ` Philip Yang
@ 2025-12-01 22:48 ` Russell, Kent
2025-12-03 17:45 ` Kuehling, Felix
1 sibling, 0 replies; 20+ messages in thread
From: Russell, Kent @ 2025-12-01 22:48 UTC (permalink / raw)
To: Yang, Philip, amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix, Koenig, Christian, Yat Sin, David
[AMD Official Use Only - AMD Internal Distribution Only]
Makes sense. This one can be
Reviewed-by: Kent Russell <kent.russell@amd.com>
> -----Original Message-----
> From: Yang, Philip <Philip.Yang@amd.com>
> Sent: Monday, December 1, 2025 3:31 PM
> To: Russell, Kent <Kent.Russell@amd.com>; Yang, Philip <Philip.Yang@amd.com>;
> amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian
> <Christian.Koenig@amd.com>; Yat Sin, David <David.YatSin@amd.com>
> Subject: Re: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
>
>
>
> On 2025-12-01 12:38, Russell, Kent wrote:
> > [Public]
> >
> > I know that it makes the change more complicated, but should we be renaming the
> function since we're no longer guaranteeing a GTT memory allocation in the
> alloc_gtt_mem function?
> yes, you are right, I have the patch to
> s/alloc_gtt_mem/alloc_kernel_mem/g, s/free_gtt_mem/free_kernel_mem/g,
> and found it is too much changes, not related to the purpose of this
> patch series, so I dropped that patch. We can cleanup this in the
> followup patch, probably remove the alloc/free_gtt_mem functions and use
> amdgpu_bo_create_kernel instead.
>
> Regards,
> Philip
> >
> > Kent
> >
> >> -----Original Message-----
> >> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Philip
> Yang
> >> Sent: Monday, December 1, 2025 9:29 AM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian
> >> <Christian.Koenig@amd.com>; Yat Sin, David <David.YatSin@amd.com>; Yang,
> >> Philip <Philip.Yang@amd.com>
> >> Subject: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
> >>
> >> To allocate kernel BO from VRAM domain for MQD in the following patch.
> >> No functional change because kernel BO allocate are all from GTT domain so far.
> >>
> >> amdgpu_amdkfd_alloc_gtt_mem has many duplicate code as
> >> function amdgpu_bo_create_kernel, with one extra flag MQD_GFX9
> >> to bind MQD and control stack in GART with different mtype,
> >> the duplicate code could be removed in future.
> >>
> >> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 +++---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
> >> drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 +
> >> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
> >> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
> >> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 +
> >> drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 ++
> >> 7 files changed, 11 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> >> index a2879d2b7c8e..9cd1660b8f60 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> >> @@ -317,7 +317,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device
> >> *adev)
> >> }
> >>
> >> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
> >> - void **mem_obj, uint64_t *gpu_addr,
> >> + u32 domain, void **mem_obj, uint64_t *gpu_addr,
> >> void **cpu_ptr, bool cp_mqd_gfx9)
> >> {
> >> struct amdgpu_bo *bo = NULL;
> >> @@ -328,7 +328,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
> amdgpu_device
> >> *adev, size_t size,
> >> memset(&bp, 0, sizeof(bp));
> >> bp.size = size;
> >> bp.byte_align = PAGE_SIZE;
> >> - bp.domain = AMDGPU_GEM_DOMAIN_GTT;
> >> + bp.domain = domain;
> >> bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> >> bp.type = ttm_bo_type_kernel;
> >> bp.resv = NULL;
> >> @@ -351,7 +351,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
> amdgpu_device
> >> *adev, size_t size,
> >> goto allocate_mem_reserve_bo_failed;
> >> }
> >>
> >> - r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
> >> + r = amdgpu_bo_pin(bo, domain);
> >> if (r) {
> >> dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
> >> goto allocate_mem_pin_bo_failed;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> >> index 335d733751cb..14b5ab6fa051 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> >> @@ -237,7 +237,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct
> >> amdgpu_bo *bo,
> >> #endif
> >> /* Shared API */
> >> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
> >> - void **mem_obj, uint64_t *gpu_addr,
> >> + u32 domain, void **mem_obj, uint64_t *gpu_addr,
> >> void **cpu_ptr, bool mqd_gfx9);
> >> void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void
> **mem_obj);
> >> int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
> >> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> >> b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> >> index ba9a09b6589a..494a563e072e 100644
> >> --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> >> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> >> @@ -359,6 +359,7 @@ int kfd_dbg_set_mes_debug_mode(struct
> >> kfd_process_device *pdd, bool sq_trap_en)
> >> if (!pdd->proc_ctx_cpu_ptr) {
> >> r = amdgpu_amdkfd_alloc_gtt_mem(adev,
> >> AMDGPU_MES_PROC_CTX_SIZE,
> >> + AMDGPU_GEM_DOMAIN_GTT,
> >> &pdd->proc_ctx_bo,
> >> &pdd->proc_ctx_gpu_addr,
> >> &pdd->proc_ctx_cpu_ptr,
> >> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> >> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> >> index 9f183d27a0ef..b0cfad750919 100644
> >> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> >> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> >> @@ -787,7 +787,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
> >> size += 512 * 1024;
> >>
> >> if (amdgpu_amdkfd_alloc_gtt_mem(
> >> - kfd->adev, size, &kfd->gtt_mem,
> >> + kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT,
> >> + &kfd->gtt_mem,
> >> &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
> >> false)) {
> >> dev_err(kfd_device, "Could not allocate %d bytes\n", size);
> >> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> >> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> >> index 36ac35d64126..028fca1d2755 100644
> >> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> >> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> >> @@ -2906,6 +2906,7 @@ static int allocate_hiq_sdma_mqd(struct
> >> device_queue_manager *dqm)
> >> NUM_XCC(dqm->dev->xcc_mask));
> >>
> >> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
> >> + AMDGPU_GEM_DOMAIN_GTT,
> >> &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
> >> (void *)&(mem_obj->cpu_ptr), false);
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> >> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> >> index 2e9b6bcf2704..a489d43d5f64 100644
> >> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> >> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> >> @@ -139,6 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node
> >> *node,
> >> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
> >> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
> >> NUM_XCC(node->xcc_mask),
> >> + AMDGPU_GEM_DOMAIN_GTT,
> >> &(mqd_mem_obj->gtt_mem),
> >> &(mqd_mem_obj->gpu_addr),
> >> (void *)&(mqd_mem_obj->cpu_ptr), true);
> >> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> >> b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> >> index 5f8cda4733f9..e0c5ec7e2fe9 100644
> >> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> >> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> >> @@ -266,6 +266,7 @@ static int init_user_queue(struct
> process_queue_manager
> >> *pqm,
> >> if (dev->kfd->shared_resources.enable_mes) {
> >> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
> >> AMDGPU_MES_GANG_CTX_SIZE,
> >> + AMDGPU_GEM_DOMAIN_GTT,
> >> &(*q)->gang_ctx_bo,
> >> &(*q)->gang_ctx_gpu_addr,
> >> &(*q)->gang_ctx_cpu_ptr,
> >> @@ -369,6 +370,7 @@ int pqm_create_queue(struct process_queue_manager
> >> *pqm,
> >> if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) {
> >> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
> >> AMDGPU_MES_PROC_CTX_SIZE,
> >> + AMDGPU_GEM_DOMAIN_GTT,
> >> &pdd->proc_ctx_bo,
> >> &pdd->proc_ctx_gpu_addr,
> >> &pdd->proc_ctx_cpu_ptr,
> >> --
> >> 2.50.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM
2025-12-01 14:28 [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
` (3 preceding siblings ...)
2025-12-01 14:28 ` [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART Philip Yang
@ 2025-12-03 15:52 ` Philip Yang
4 siblings, 0 replies; 20+ messages in thread
From: Philip Yang @ 2025-12-03 15:52 UTC (permalink / raw)
To: Philip Yang, amd-gfx; +Cc: Felix.Kuehling, christian.koenig, david.yatsin
ping...
On 2025-12-01 09:28, Philip Yang wrote:
> To reduce multiple queues switch latency, move user queues MQD to HBM,
> and map on GART with mtype RW.
>
> v2: patch 4 GART mapping use MC address, vram_base_offset + physical address
>
> Philip Yang (4):
> drm/amdkfd: Bind gfx9 MQD in GART with mtype RW
> drm/amdkfd: Add domain parameter to alloc kernel BO
> drm/amdkfd: Move gfx9 MQD to VRAM domain
> drm/amdkfd: Map VRAM MQD on GART
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 9 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 115 +++++++++++++++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +-
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 9 ++
> .../amd/amdkfd/kfd_process_queue_manager.c | 2 +
> 12 files changed, 124 insertions(+), 24 deletions(-)
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART
2025-12-01 14:28 ` [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART Philip Yang
@ 2025-12-03 16:06 ` Christian König
2025-12-04 22:43 ` Philip Yang
0 siblings, 1 reply; 20+ messages in thread
From: Christian König @ 2025-12-03 16:06 UTC (permalink / raw)
To: Philip Yang, amd-gfx; +Cc: Felix.Kuehling, david.yatsin
On 12/1/25 15:28, Philip Yang wrote:
> MQD BO on VRAM access via FB aperture is mtype UC uncaching, map to GART
> as mtype RW caching, to reduce queue switch latency.
>
> TTM bo only has one resource, add GART resource to amdgpu_bo in order to
> support dynamic GART resource and VRAM BO resource.
>
> Update amdgpu_ttm_gart_bind_gfx9_mqd to map MQD in system or VRAM.
>
> Add helper amdgpu_ttm_alloc_gart_for_vram_bo to alloc GART entries resource
> for MQD bo->gart_res and bind to GART mapping.
Clear NAK to that approach! That would completely confuse TTM.
We need to talk about that on the weekly meeting first.
Regards,
Christian.
>
> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 113 +++++++++++++++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 8 ++
> 5 files changed, 108 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 926a3f09a776..d267456cd181 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1297,6 +1297,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
>
> abo = ttm_to_amdgpu_bo(bo);
>
> + if (abo->gart_res)
> + ttm_resource_free(bo, &abo->gart_res);
> +
> WARN_ON(abo->vm_bo);
>
> if (abo->kfd_bo)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 52c2d1731aab..a412f5ec2a09 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -106,6 +106,7 @@ struct amdgpu_bo {
> struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
> struct ttm_placement placement;
> struct ttm_buffer_object tbo;
> + struct ttm_resource *gart_res;
> struct ttm_bo_kmap_obj kmap;
> u64 flags;
> /* per VM structure for page tables and with virtual addresses */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 5f58cff2c28b..1d8f5fc66acc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -832,14 +832,27 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
> * Ctrl stack and modify their memory type to NC.
> */
> static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
> - struct ttm_tt *ttm, uint64_t flags)
> + struct ttm_buffer_object *tbo,
> + uint64_t flags)
> {
> + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
> + struct ttm_tt *ttm = tbo->ttm;
> struct amdgpu_ttm_tt *gtt = (void *)ttm;
> - uint64_t total_pages = ttm->num_pages;
> + uint64_t total_pages;
> int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
> uint64_t page_idx, pages_per_xcc;
> - int i;
> uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
> + int i;
> +
> + if (!ttm && !abo->gart_res)
> + return;
> +
> + if (ttm) {
> + total_pages = ttm->num_pages;
> + } else {
> + WARN_ON_ONCE(abo->gart_res->size != tbo->resource->size);
> + total_pages = (abo->gart_res->size) >> PAGE_SHIFT;
> + }
>
> flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_RW);
>
> @@ -847,19 +860,33 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
> do_div(pages_per_xcc, num_xcc);
>
> for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
> - /* MQD page: use default flags */
> - amdgpu_gart_bind(adev,
> - gtt->offset + (page_idx << PAGE_SHIFT),
> - 1, >t->ttm.dma_address[page_idx], flags);
> - /*
> - * Ctrl pages - modify the memory type to NC (ctrl_flags) from
> - * the second page of the BO onward.
> - */
> - amdgpu_gart_bind(adev,
> - gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
> - pages_per_xcc - 1,
> - >t->ttm.dma_address[page_idx + 1],
> - ctrl_flags);
> + if (ttm) {
> + /* MQD page: use default flags */
> + amdgpu_gart_bind(adev,
> + gtt->offset + (page_idx << PAGE_SHIFT),
> + 1, >t->ttm.dma_address[page_idx], flags);
> + /*
> + * Ctrl pages - modify the memory type to NC (ctrl_flags) from
> + * the second page of the BO onward.
> + */
> + amdgpu_gart_bind(adev,
> + gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
> + pages_per_xcc - 1,
> + >t->ttm.dma_address[page_idx + 1],
> + ctrl_flags);
> + } else {
> + u64 pa = (tbo->resource->start + page_idx) << PAGE_SHIFT;
> + u64 start_page = abo->gart_res->start + page_idx;
> +
> + pa += adev->vm_manager.vram_base_offset;
> + amdgpu_gart_map_vram_range(adev, pa, start_page, 1,
> + flags, NULL);
> +
> + amdgpu_gart_map_vram_range(adev, pa + PAGE_SIZE,
> + start_page + 1,
> + pages_per_xcc - 1,
> + ctrl_flags, NULL);
> + }
> }
> }
>
> @@ -875,12 +902,14 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
> flags |= AMDGPU_PTE_TMZ;
>
> if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
> - amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
> + amdgpu_ttm_gart_bind_gfx9_mqd(adev, tbo, flags);
> } else {
> amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
> gtt->ttm.dma_address, flags);
> }
> - gtt->bound = true;
> +
> + if (ttm)
> + gtt->bound = true;
> }
>
> /*
> @@ -1000,6 +1029,54 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
> return 0;
> }
>
> +int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo,
> + u64 *gpu_addr)
> +{
> + struct ttm_buffer_object *bo = &abo->tbo;
> + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
> + struct ttm_operation_ctx ctx = { false, false };
> + struct ttm_placement placement;
> + struct ttm_place placements;
> + struct ttm_resource *res;
> + uint64_t flags;
> + int r;
> +
> + /* Only for valid VRAM bo resource */
> + if (bo->resource->start == AMDGPU_BO_INVALID_OFFSET)
> + return 0;
> +
> + r = amdgpu_bo_reserve(abo, false);
> + if (unlikely(r))
> + return r;
> +
> + /* allocate GART space */
> + placement.num_placement = 1;
> + placement.placement = &placements;
> + placements.fpfn = 0;
> + placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
> + placements.mem_type = TTM_PL_TT;
> + placements.flags = bo->resource->placement;
> +
> + r = ttm_bo_mem_space(bo, &placement, &res, &ctx);
> + if (unlikely(r))
> + goto out_unreserve;
> +
> + /* compute PTE flags for this buffer object */
> + flags = amdgpu_ttm_tt_pte_flags(adev, NULL, bo->resource);
> +
> + /* Bind VRAM pages */
> + abo->gart_res = res;
> +
> + amdgpu_ttm_gart_bind(adev, bo, flags);
> + amdgpu_gart_invalidate_tlb(adev);
> +
> + *gpu_addr = res->start << PAGE_SHIFT;
> +
> +out_unreserve:
> + amdgpu_bo_unreserve(abo);
> + return r;
> +}
> +
> /*
> * amdgpu_ttm_recover_gart - Rebind GTT pages
> *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 15e659575087..707654732759 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -179,6 +179,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
> u64 k_job_id);
>
> int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
> +int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo, u64 *gpu_addr);
> void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
> uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> index c6945c842267..d96de02c6bb9 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> @@ -148,6 +148,14 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
> kfree(mqd_mem_obj);
> return NULL;
> }
> +
> + retval = amdgpu_ttm_alloc_gart_vram_bo(mqd_mem_obj->gtt_mem,
> + &(mqd_mem_obj->gpu_addr));
> + if (retval) {
> + amdgpu_amdkfd_free_gtt_mem(node->adev, &(mqd_mem_obj->gtt_mem));
> + kfree(mqd_mem_obj);
> + return NULL;
> + }
> } else {
> retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd),
> &mqd_mem_obj);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW
2025-12-01 14:28 ` [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW Philip Yang
@ 2025-12-03 17:40 ` Kuehling, Felix
2025-12-04 15:10 ` Philip Yang
0 siblings, 1 reply; 20+ messages in thread
From: Kuehling, Felix @ 2025-12-03 17:40 UTC (permalink / raw)
To: Philip Yang, amd-gfx; +Cc: christian.koenig, david.yatsin
On 2025-12-01 09:28, Philip Yang wrote:
> For gfx9, bind MQD in GART with mtype RW to enable caching, to
> reduce queue switch latency.
>
> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index e553cf411191..5f58cff2c28b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -841,6 +841,8 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
> int i;
> uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
>
> + flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_RW);
> +
> pages_per_xcc = total_pages;
> do_div(pages_per_xcc, num_xcc);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 139642eacdd0..4dd15767a722 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -101,6 +101,7 @@ struct amdgpu_bo_vm;
> AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))
>
> #define AMDGPU_MTYPE_NC 0
> +#define AMDGPU_MTYPE_RW 1
This is probably not the right place to define this. MTYPE_RW is not
universally available on all our GPUs. Not even on all GFX9 GPUs. This
MTYPE definition needs to be in an ASIC-specific header file, and
probably already exists somewhere.
Also, we can't use MTYPE_RW on GPUs that don't support it. I believe it
was added in MI300.
Regards,
Felix
> #define AMDGPU_MTYPE_CC 2
>
> #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO
2025-12-01 20:31 ` Philip Yang
2025-12-01 22:48 ` Russell, Kent
@ 2025-12-03 17:45 ` Kuehling, Felix
1 sibling, 0 replies; 20+ messages in thread
From: Kuehling, Felix @ 2025-12-03 17:45 UTC (permalink / raw)
To: Philip Yang, Russell, Kent, Yang, Philip,
amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian, Yat Sin, David
On 2025-12-01 15:31, Philip Yang wrote:
>
>
> On 2025-12-01 12:38, Russell, Kent wrote:
>> [Public]
>>
>> I know that it makes the change more complicated, but should we be
>> renaming the function since we're no longer guaranteeing a GTT memory
>> allocation in the alloc_gtt_mem function?
> yes, you are right, I have the patch to
> s/alloc_gtt_mem/alloc_kernel_mem/g, s/free_gtt_mem/free_kernel_mem/g,
> and found it is too much changes,
I see amdgpu_amdkfd_alloc_gtt_mem being called in 7 places in KFD. I
don't think that's too much churn. You need to change all those places
anyway to add a new parameter, so you might as well change the function
name while you're there.
Regards,
Felix
> not related to the purpose of this patch series, so I dropped that
> patch. We can cleanup this in the followup patch, probably remove the
> alloc/free_gtt_mem functions and use amdgpu_bo_create_kernel instead.
>
> Regards,
> Philip
>>
>> Kent
>>
>>> -----Original Message-----
>>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>>> Philip Yang
>>> Sent: Monday, December 1, 2025 9:29 AM
>>> To: amd-gfx@lists.freedesktop.org
>>> Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian
>>> <Christian.Koenig@amd.com>; Yat Sin, David <David.YatSin@amd.com>;
>>> Yang,
>>> Philip <Philip.Yang@amd.com>
>>> Subject: [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc
>>> kernel BO
>>>
>>> To allocate kernel BO from VRAM domain for MQD in the following patch.
>>> No functional change because kernel BO allocate are all from GTT
>>> domain so far.
>>>
>>> amdgpu_amdkfd_alloc_gtt_mem has many duplicate code as
>>> function amdgpu_bo_create_kernel, with one extra flag MQD_GFX9
>>> to bind MQD and control stack in GART with different mtype,
>>> the duplicate code could be removed in future.
>>>
>>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 +++---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
>>> drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 +
>>> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
>>> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
>>> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 +
>>> drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 ++
>>> 7 files changed, 11 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> index a2879d2b7c8e..9cd1660b8f60 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> @@ -317,7 +317,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device
>>> *adev)
>>> }
>>>
>>> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t
>>> size,
>>> - void **mem_obj, uint64_t *gpu_addr,
>>> + u32 domain, void **mem_obj, uint64_t
>>> *gpu_addr,
>>> void **cpu_ptr, bool cp_mqd_gfx9)
>>> {
>>> struct amdgpu_bo *bo = NULL;
>>> @@ -328,7 +328,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
>>> amdgpu_device
>>> *adev, size_t size,
>>> memset(&bp, 0, sizeof(bp));
>>> bp.size = size;
>>> bp.byte_align = PAGE_SIZE;
>>> - bp.domain = AMDGPU_GEM_DOMAIN_GTT;
>>> + bp.domain = domain;
>>> bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>>> bp.type = ttm_bo_type_kernel;
>>> bp.resv = NULL;
>>> @@ -351,7 +351,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
>>> amdgpu_device
>>> *adev, size_t size,
>>> goto allocate_mem_reserve_bo_failed;
>>> }
>>>
>>> - r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
>>> + r = amdgpu_bo_pin(bo, domain);
>>> if (r) {
>>> dev_err(adev->dev, "(%d) failed to pin bo for
>>> amdkfd\n", r);
>>> goto allocate_mem_pin_bo_failed;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>>> index 335d733751cb..14b5ab6fa051 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>>> @@ -237,7 +237,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct
>>> amdgpu_bo *bo,
>>> #endif
>>> /* Shared API */
>>> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t
>>> size,
>>> - void **mem_obj, uint64_t *gpu_addr,
>>> + u32 domain, void **mem_obj, uint64_t
>>> *gpu_addr,
>>> void **cpu_ptr, bool mqd_gfx9);
>>> void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void
>>> **mem_obj);
>>> int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>>> index ba9a09b6589a..494a563e072e 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
>>> @@ -359,6 +359,7 @@ int kfd_dbg_set_mes_debug_mode(struct
>>> kfd_process_device *pdd, bool sq_trap_en)
>>> if (!pdd->proc_ctx_cpu_ptr) {
>>> r = amdgpu_amdkfd_alloc_gtt_mem(adev,
>>> AMDGPU_MES_PROC_CTX_SIZE,
>>> + AMDGPU_GEM_DOMAIN_GTT,
>>> &pdd->proc_ctx_bo,
>>> &pdd->proc_ctx_gpu_addr,
>>> &pdd->proc_ctx_cpu_ptr,
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>>> index 9f183d27a0ef..b0cfad750919 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>>> @@ -787,7 +787,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
>>> size += 512 * 1024;
>>>
>>> if (amdgpu_amdkfd_alloc_gtt_mem(
>>> - kfd->adev, size, &kfd->gtt_mem,
>>> + kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT,
>>> + &kfd->gtt_mem,
>>> &kfd->gtt_start_gpu_addr,
>>> &kfd->gtt_start_cpu_ptr,
>>> false)) {
>>> dev_err(kfd_device, "Could not allocate %d bytes\n",
>>> size);
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>>> index 36ac35d64126..028fca1d2755 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>>> @@ -2906,6 +2906,7 @@ static int allocate_hiq_sdma_mqd(struct
>>> device_queue_manager *dqm)
>>> NUM_XCC(dqm->dev->xcc_mask));
>>>
>>> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
>>> + AMDGPU_GEM_DOMAIN_GTT,
>>> &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
>>> (void *)&(mem_obj->cpu_ptr), false);
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> index 2e9b6bcf2704..a489d43d5f64 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> @@ -139,6 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct
>>> kfd_node
>>> *node,
>>> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
>>> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
>>> NUM_XCC(node->xcc_mask),
>>> + AMDGPU_GEM_DOMAIN_GTT,
>>> &(mqd_mem_obj->gtt_mem),
>>> &(mqd_mem_obj->gpu_addr),
>>> (void *)&(mqd_mem_obj->cpu_ptr), true);
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>>> index 5f8cda4733f9..e0c5ec7e2fe9 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
>>> @@ -266,6 +266,7 @@ static int init_user_queue(struct
>>> process_queue_manager
>>> *pqm,
>>> if (dev->kfd->shared_resources.enable_mes) {
>>> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
>>> AMDGPU_MES_GANG_CTX_SIZE,
>>> + AMDGPU_GEM_DOMAIN_GTT,
>>> &(*q)->gang_ctx_bo,
>>> &(*q)->gang_ctx_gpu_addr,
>>> &(*q)->gang_ctx_cpu_ptr,
>>> @@ -369,6 +370,7 @@ int pqm_create_queue(struct process_queue_manager
>>> *pqm,
>>> if (!pdd->proc_ctx_cpu_ptr &&
>>> dev->kfd->shared_resources.enable_mes) {
>>> retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
>>> AMDGPU_MES_PROC_CTX_SIZE,
>>> + AMDGPU_GEM_DOMAIN_GTT,
>>> &pdd->proc_ctx_bo,
>>> &pdd->proc_ctx_gpu_addr,
>>> &pdd->proc_ctx_cpu_ptr,
>>> --
>>> 2.50.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain
2025-12-01 14:28 ` [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain Philip Yang
@ 2025-12-03 17:55 ` Kuehling, Felix
2025-12-04 19:28 ` Philip Yang
2025-12-04 22:51 ` Philip Yang
0 siblings, 2 replies; 20+ messages in thread
From: Kuehling, Felix @ 2025-12-03 17:55 UTC (permalink / raw)
To: Philip Yang, amd-gfx; +Cc: christian.koenig, david.yatsin
On 2025-12-01 09:28, Philip Yang wrote:
> To reduce queue switch latency further, move MQD to VRAM domain, add
> AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag to allocate contiguous pages
> using one buddy block.
Why does it need to be contiguous? In the next patch you're mapping it
in the GART anyway.
Regards,
Felix
>
> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index 9cd1660b8f60..c11e37915365 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
> bp.size = size;
> bp.byte_align = PAGE_SIZE;
> bp.domain = domain;
> - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
> + AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> bp.type = ttm_bo_type_kernel;
> bp.resv = NULL;
> bp.bo_ptr_size = sizeof(struct amdgpu_bo);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> index a489d43d5f64..c6945c842267 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> @@ -139,7 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
> NUM_XCC(node->xcc_mask),
> - AMDGPU_GEM_DOMAIN_GTT,
> + AMDGPU_GEM_DOMAIN_VRAM,
> &(mqd_mem_obj->gtt_mem),
> &(mqd_mem_obj->gpu_addr),
> (void *)&(mqd_mem_obj->cpu_ptr), true);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW
2025-12-03 17:40 ` Kuehling, Felix
@ 2025-12-04 15:10 ` Philip Yang
0 siblings, 0 replies; 20+ messages in thread
From: Philip Yang @ 2025-12-04 15:10 UTC (permalink / raw)
To: Kuehling, Felix, Philip Yang, amd-gfx; +Cc: christian.koenig, david.yatsin
On 2025-12-03 12:40, Kuehling, Felix wrote:
> On 2025-12-01 09:28, Philip Yang wrote:
>> For gfx9, bind MQD in GART with mtype RW to enable caching, to
>> reduce queue switch latency.
>>
>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
>> 2 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index e553cf411191..5f58cff2c28b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -841,6 +841,8 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct
>> amdgpu_device *adev,
>> int i;
>> uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags,
>> AMDGPU_MTYPE_NC);
>> + flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_RW);
>> +
>> pages_per_xcc = total_pages;
>> do_div(pages_per_xcc, num_xcc);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index 139642eacdd0..4dd15767a722 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -101,6 +101,7 @@ struct amdgpu_bo_vm;
>> AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))
>> #define AMDGPU_MTYPE_NC 0
>> +#define AMDGPU_MTYPE_RW 1
>
> This is probably not the right place to define this. MTYPE_RW is not
> universally available on all our GPUs. Not even on all GFX9 GPUs. This
> MTYPE definition needs to be in an ASIC-specific header file, and
> probably already exists somewhere.
>
> Also, we can't use MTYPE_RW on GPUs that don't support it. I believe
> it was added in MI300.
Thanks, this is available for gfxv >= 9.4.1, will drop this patch and
setup mtype before calling amdgpu_ttm_gart_bind.
Philip
>
> Regards,
> Felix
>
>
>> #define AMDGPU_MTYPE_CC 2
>> #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain
2025-12-03 17:55 ` Kuehling, Felix
@ 2025-12-04 19:28 ` Philip Yang
2025-12-04 22:51 ` Philip Yang
1 sibling, 0 replies; 20+ messages in thread
From: Philip Yang @ 2025-12-04 19:28 UTC (permalink / raw)
To: Kuehling, Felix, Philip Yang, amd-gfx; +Cc: christian.koenig, david.yatsin
On 2025-12-03 12:55, Kuehling, Felix wrote:
> On 2025-12-01 09:28, Philip Yang wrote:
>> To reduce queue switch latency further, move MQD to VRAM domain, add
>> AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag to allocate contiguous pages
>> using one buddy block.
>
> Why does it need to be contiguous? In the next patch you're mapping it
> in the GART anyway.
Because MQD and control stack uses different mtype, for multiple XCCs,
it is complicated to update mapping using resource cursor with multiple
buddy blocks which depends on size alignment. Yes, with GART mapping, we
don't need contiguous pages, will remove this in next version.
Regards,
Philip
>
> Regards,
> Felix
>
>
>>
>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
>> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
>> 2 files changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> index 9cd1660b8f60..c11e37915365 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> @@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
>> amdgpu_device *adev, size_t size,
>> bp.size = size;
>> bp.byte_align = PAGE_SIZE;
>> bp.domain = domain;
>> - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>> + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
>> + AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>> bp.type = ttm_bo_type_kernel;
>> bp.resv = NULL;
>> bp.bo_ptr_size = sizeof(struct amdgpu_bo);
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> index a489d43d5f64..c6945c842267 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> @@ -139,7 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct
>> kfd_node *node,
>> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
>> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
>> NUM_XCC(node->xcc_mask),
>> - AMDGPU_GEM_DOMAIN_GTT,
>> + AMDGPU_GEM_DOMAIN_VRAM,
>> &(mqd_mem_obj->gtt_mem),
>> &(mqd_mem_obj->gpu_addr),
>> (void *)&(mqd_mem_obj->cpu_ptr), true);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART
2025-12-03 16:06 ` Christian König
@ 2025-12-04 22:43 ` Philip Yang
2025-12-05 9:30 ` Christian König
0 siblings, 1 reply; 20+ messages in thread
From: Philip Yang @ 2025-12-04 22:43 UTC (permalink / raw)
To: Christian König, Philip Yang, amd-gfx; +Cc: Felix.Kuehling, david.yatsin
On 2025-12-03 11:06, Christian König wrote:
> On 12/1/25 15:28, Philip Yang wrote:
>> MQD BO on VRAM access via FB aperture is mtype UC uncaching, map to GART
>> as mtype RW caching, to reduce queue switch latency.
>>
>> TTM bo only has one resource, add GART resource to amdgpu_bo in order to
>> support dynamic GART resource and VRAM BO resource.
>>
>> Update amdgpu_ttm_gart_bind_gfx9_mqd to map MQD in system or VRAM.
>>
>> Add helper amdgpu_ttm_alloc_gart_for_vram_bo to alloc GART entries resource
>> for MQD bo->gart_res and bind to GART mapping.
> Clear NAK to that approach! That would completely confuse TTM.
>
> We need to talk about that on the weekly meeting first.
I think that is becausettm_bo_mem_space also add GART resource into ttm
bo, which already hold
VRAM resource. Felix suggest to alloc gart space via drm_mm and store in
mqd structure, not in amdgpu_bo.
I will implement it in next version and we can discuss details in the
meeting.
Regards,
Philip
>
> Regards,
> Christian.
>
>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 113 +++++++++++++++---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
>> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 8 ++
>> 5 files changed, 108 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> index 926a3f09a776..d267456cd181 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> @@ -1297,6 +1297,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
>>
>> abo = ttm_to_amdgpu_bo(bo);
>>
>> + if (abo->gart_res)
>> + ttm_resource_free(bo, &abo->gart_res);
>> +
>> WARN_ON(abo->vm_bo);
>>
>> if (abo->kfd_bo)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>> index 52c2d1731aab..a412f5ec2a09 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>> @@ -106,6 +106,7 @@ struct amdgpu_bo {
>> struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
>> struct ttm_placement placement;
>> struct ttm_buffer_object tbo;
>> + struct ttm_resource *gart_res;
>> struct ttm_bo_kmap_obj kmap;
>> u64 flags;
>> /* per VM structure for page tables and with virtual addresses */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index 5f58cff2c28b..1d8f5fc66acc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -832,14 +832,27 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
>> * Ctrl stack and modify their memory type to NC.
>> */
>> static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
>> - struct ttm_tt *ttm, uint64_t flags)
>> + struct ttm_buffer_object *tbo,
>> + uint64_t flags)
>> {
>> + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
>> + struct ttm_tt *ttm = tbo->ttm;
>> struct amdgpu_ttm_tt *gtt = (void *)ttm;
>> - uint64_t total_pages = ttm->num_pages;
>> + uint64_t total_pages;
>> int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
>> uint64_t page_idx, pages_per_xcc;
>> - int i;
>> uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
>> + int i;
>> +
>> + if (!ttm && !abo->gart_res)
>> + return;
>> +
>> + if (ttm) {
>> + total_pages = ttm->num_pages;
>> + } else {
>> + WARN_ON_ONCE(abo->gart_res->size != tbo->resource->size);
>> + total_pages = (abo->gart_res->size) >> PAGE_SHIFT;
>> + }
>>
>> flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_RW);
>>
>> @@ -847,19 +860,33 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
>> do_div(pages_per_xcc, num_xcc);
>>
>> for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
>> - /* MQD page: use default flags */
>> - amdgpu_gart_bind(adev,
>> - gtt->offset + (page_idx << PAGE_SHIFT),
>> - 1, >t->ttm.dma_address[page_idx], flags);
>> - /*
>> - * Ctrl pages - modify the memory type to NC (ctrl_flags) from
>> - * the second page of the BO onward.
>> - */
>> - amdgpu_gart_bind(adev,
>> - gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
>> - pages_per_xcc - 1,
>> - >t->ttm.dma_address[page_idx + 1],
>> - ctrl_flags);
>> + if (ttm) {
>> + /* MQD page: use default flags */
>> + amdgpu_gart_bind(adev,
>> + gtt->offset + (page_idx << PAGE_SHIFT),
>> + 1, >t->ttm.dma_address[page_idx], flags);
>> + /*
>> + * Ctrl pages - modify the memory type to NC (ctrl_flags) from
>> + * the second page of the BO onward.
>> + */
>> + amdgpu_gart_bind(adev,
>> + gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
>> + pages_per_xcc - 1,
>> + >t->ttm.dma_address[page_idx + 1],
>> + ctrl_flags);
>> + } else {
>> + u64 pa = (tbo->resource->start + page_idx) << PAGE_SHIFT;
>> + u64 start_page = abo->gart_res->start + page_idx;
>> +
>> + pa += adev->vm_manager.vram_base_offset;
>> + amdgpu_gart_map_vram_range(adev, pa, start_page, 1,
>> + flags, NULL);
>> +
>> + amdgpu_gart_map_vram_range(adev, pa + PAGE_SIZE,
>> + start_page + 1,
>> + pages_per_xcc - 1,
>> + ctrl_flags, NULL);
>> + }
>> }
>> }
>>
>> @@ -875,12 +902,14 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
>> flags |= AMDGPU_PTE_TMZ;
>>
>> if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
>> - amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
>> + amdgpu_ttm_gart_bind_gfx9_mqd(adev, tbo, flags);
>> } else {
>> amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
>> gtt->ttm.dma_address, flags);
>> }
>> - gtt->bound = true;
>> +
>> + if (ttm)
>> + gtt->bound = true;
>> }
>>
>> /*
>> @@ -1000,6 +1029,54 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
>> return 0;
>> }
>>
>> +int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo,
>> + u64 *gpu_addr)
>> +{
>> + struct ttm_buffer_object *bo = &abo->tbo;
>> + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
>> + struct ttm_operation_ctx ctx = { false, false };
>> + struct ttm_placement placement;
>> + struct ttm_place placements;
>> + struct ttm_resource *res;
>> + uint64_t flags;
>> + int r;
>> +
>> + /* Only for valid VRAM bo resource */
>> + if (bo->resource->start == AMDGPU_BO_INVALID_OFFSET)
>> + return 0;
>> +
>> + r = amdgpu_bo_reserve(abo, false);
>> + if (unlikely(r))
>> + return r;
>> +
>> + /* allocate GART space */
>> + placement.num_placement = 1;
>> + placement.placement = &placements;
>> + placements.fpfn = 0;
>> + placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
>> + placements.mem_type = TTM_PL_TT;
>> + placements.flags = bo->resource->placement;
>> +
>> + r = ttm_bo_mem_space(bo, &placement, &res, &ctx);
>> + if (unlikely(r))
>> + goto out_unreserve;
>> +
>> + /* compute PTE flags for this buffer object */
>> + flags = amdgpu_ttm_tt_pte_flags(adev, NULL, bo->resource);
>> +
>> + /* Bind VRAM pages */
>> + abo->gart_res = res;
>> +
>> + amdgpu_ttm_gart_bind(adev, bo, flags);
>> + amdgpu_gart_invalidate_tlb(adev);
>> +
>> + *gpu_addr = res->start << PAGE_SHIFT;
>> +
>> +out_unreserve:
>> + amdgpu_bo_unreserve(abo);
>> + return r;
>> +}
>> +
>> /*
>> * amdgpu_ttm_recover_gart - Rebind GTT pages
>> *
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> index 15e659575087..707654732759 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> @@ -179,6 +179,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
>> u64 k_job_id);
>>
>> int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
>> +int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo, u64 *gpu_addr);
>> void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
>> uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> index c6945c842267..d96de02c6bb9 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> @@ -148,6 +148,14 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
>> kfree(mqd_mem_obj);
>> return NULL;
>> }
>> +
>> + retval = amdgpu_ttm_alloc_gart_vram_bo(mqd_mem_obj->gtt_mem,
>> + &(mqd_mem_obj->gpu_addr));
>> + if (retval) {
>> + amdgpu_amdkfd_free_gtt_mem(node->adev, &(mqd_mem_obj->gtt_mem));
>> + kfree(mqd_mem_obj);
>> + return NULL;
>> + }
>> } else {
>> retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd),
>> &mqd_mem_obj);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain
2025-12-03 17:55 ` Kuehling, Felix
2025-12-04 19:28 ` Philip Yang
@ 2025-12-04 22:51 ` Philip Yang
2025-12-05 19:46 ` Felix Kuehling
1 sibling, 1 reply; 20+ messages in thread
From: Philip Yang @ 2025-12-04 22:51 UTC (permalink / raw)
To: Kuehling, Felix, Philip Yang, amd-gfx; +Cc: christian.koenig, david.yatsin
On 2025-12-03 12:55, Kuehling, Felix wrote:
> On 2025-12-01 09:28, Philip Yang wrote:
>> To reduce queue switch latency further, move MQD to VRAM domain, add
>> AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag to allocate contiguous pages
>> using one buddy block.
>
> Why does it need to be contiguous? In the next patch you're mapping it
> in the GART anyway.
Without AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag, amdgpu_bo_gpu_offset
trigger this warning
WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
!(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
This makes senses because we pass the FB aperture address to CP, this
should be contiguous pages.
Regards,
Philip
>
> Regards,
> Felix
>
>
>>
>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
>> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
>> 2 files changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> index 9cd1660b8f60..c11e37915365 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> @@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
>> amdgpu_device *adev, size_t size,
>> bp.size = size;
>> bp.byte_align = PAGE_SIZE;
>> bp.domain = domain;
>> - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>> + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
>> + AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>> bp.type = ttm_bo_type_kernel;
>> bp.resv = NULL;
>> bp.bo_ptr_size = sizeof(struct amdgpu_bo);
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> index a489d43d5f64..c6945c842267 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>> @@ -139,7 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct
>> kfd_node *node,
>> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
>> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
>> NUM_XCC(node->xcc_mask),
>> - AMDGPU_GEM_DOMAIN_GTT,
>> + AMDGPU_GEM_DOMAIN_VRAM,
>> &(mqd_mem_obj->gtt_mem),
>> &(mqd_mem_obj->gpu_addr),
>> (void *)&(mqd_mem_obj->cpu_ptr), true);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART
2025-12-04 22:43 ` Philip Yang
@ 2025-12-05 9:30 ` Christian König
0 siblings, 0 replies; 20+ messages in thread
From: Christian König @ 2025-12-05 9:30 UTC (permalink / raw)
To: Philip Yang, Philip Yang, amd-gfx; +Cc: Felix.Kuehling, david.yatsin
On 12/4/25 23:43, Philip Yang wrote:
> On 2025-12-03 11:06, Christian König wrote:
>> On 12/1/25 15:28, Philip Yang wrote:
>>> MQD BO on VRAM access via FB aperture is mtype UC uncaching, map to GART
>>> as mtype RW caching, to reduce queue switch latency.
>>>
>>> TTM bo only has one resource, add GART resource to amdgpu_bo in order to
>>> support dynamic GART resource and VRAM BO resource.
>>>
>>> Update amdgpu_ttm_gart_bind_gfx9_mqd to map MQD in system or VRAM.
>>>
>>> Add helper amdgpu_ttm_alloc_gart_for_vram_bo to alloc GART entries resource
>>> for MQD bo->gart_res and bind to GART mapping.
>> Clear NAK to that approach! That would completely confuse TTM.
>>
>> We need to talk about that on the weekly meeting first.
> I think that is becausettm_bo_mem_space also add GART resource into ttm bo, which already hold
> VRAM resource. Felix suggest to alloc gart space via drm_mm and store in mqd structure, not in amdgpu_bo.
> I will implement it in next version and we can discuss details in the meeting.
Yes, that sounds like a good approach to me.
We could implement GART as separate TTM domain and then have the ability to map anything to it, but that is a much wider change.
Probably good to do that in the long term, but also tricky to get right.
Regards,
Christian.
>
> Regards,
> Philip
>>
>> Regards,
>> Christian.
>>
>>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 113 +++++++++++++++---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
>>> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 8 ++
>>> 5 files changed, 108 insertions(+), 18 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> index 926a3f09a776..d267456cd181 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> @@ -1297,6 +1297,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
>>> abo = ttm_to_amdgpu_bo(bo);
>>> + if (abo->gart_res)
>>> + ttm_resource_free(bo, &abo->gart_res);
>>> +
>>> WARN_ON(abo->vm_bo);
>>> if (abo->kfd_bo)
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>>> index 52c2d1731aab..a412f5ec2a09 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>>> @@ -106,6 +106,7 @@ struct amdgpu_bo {
>>> struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
>>> struct ttm_placement placement;
>>> struct ttm_buffer_object tbo;
>>> + struct ttm_resource *gart_res;
>>> struct ttm_bo_kmap_obj kmap;
>>> u64 flags;
>>> /* per VM structure for page tables and with virtual addresses */
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> index 5f58cff2c28b..1d8f5fc66acc 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> @@ -832,14 +832,27 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
>>> * Ctrl stack and modify their memory type to NC.
>>> */
>>> static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
>>> - struct ttm_tt *ttm, uint64_t flags)
>>> + struct ttm_buffer_object *tbo,
>>> + uint64_t flags)
>>> {
>>> + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
>>> + struct ttm_tt *ttm = tbo->ttm;
>>> struct amdgpu_ttm_tt *gtt = (void *)ttm;
>>> - uint64_t total_pages = ttm->num_pages;
>>> + uint64_t total_pages;
>>> int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
>>> uint64_t page_idx, pages_per_xcc;
>>> - int i;
>>> uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
>>> + int i;
>>> +
>>> + if (!ttm && !abo->gart_res)
>>> + return;
>>> +
>>> + if (ttm) {
>>> + total_pages = ttm->num_pages;
>>> + } else {
>>> + WARN_ON_ONCE(abo->gart_res->size != tbo->resource->size);
>>> + total_pages = (abo->gart_res->size) >> PAGE_SHIFT;
>>> + }
>>> flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_RW);
>>> @@ -847,19 +860,33 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
>>> do_div(pages_per_xcc, num_xcc);
>>> for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
>>> - /* MQD page: use default flags */
>>> - amdgpu_gart_bind(adev,
>>> - gtt->offset + (page_idx << PAGE_SHIFT),
>>> - 1, >t->ttm.dma_address[page_idx], flags);
>>> - /*
>>> - * Ctrl pages - modify the memory type to NC (ctrl_flags) from
>>> - * the second page of the BO onward.
>>> - */
>>> - amdgpu_gart_bind(adev,
>>> - gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
>>> - pages_per_xcc - 1,
>>> - >t->ttm.dma_address[page_idx + 1],
>>> - ctrl_flags);
>>> + if (ttm) {
>>> + /* MQD page: use default flags */
>>> + amdgpu_gart_bind(adev,
>>> + gtt->offset + (page_idx << PAGE_SHIFT),
>>> + 1, >t->ttm.dma_address[page_idx], flags);
>>> + /*
>>> + * Ctrl pages - modify the memory type to NC (ctrl_flags) from
>>> + * the second page of the BO onward.
>>> + */
>>> + amdgpu_gart_bind(adev,
>>> + gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
>>> + pages_per_xcc - 1,
>>> + >t->ttm.dma_address[page_idx + 1],
>>> + ctrl_flags);
>>> + } else {
>>> + u64 pa = (tbo->resource->start + page_idx) << PAGE_SHIFT;
>>> + u64 start_page = abo->gart_res->start + page_idx;
>>> +
>>> + pa += adev->vm_manager.vram_base_offset;
>>> + amdgpu_gart_map_vram_range(adev, pa, start_page, 1,
>>> + flags, NULL);
>>> +
>>> + amdgpu_gart_map_vram_range(adev, pa + PAGE_SIZE,
>>> + start_page + 1,
>>> + pages_per_xcc - 1,
>>> + ctrl_flags, NULL);
>>> + }
>>> }
>>> }
>>> @@ -875,12 +902,14 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
>>> flags |= AMDGPU_PTE_TMZ;
>>> if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
>>> - amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
>>> + amdgpu_ttm_gart_bind_gfx9_mqd(adev, tbo, flags);
>>> } else {
>>> amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
>>> gtt->ttm.dma_address, flags);
>>> }
>>> - gtt->bound = true;
>>> +
>>> + if (ttm)
>>> + gtt->bound = true;
>>> }
>>> /*
>>> @@ -1000,6 +1029,54 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
>>> return 0;
>>> }
>>> +int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo,
>>> + u64 *gpu_addr)
>>> +{
>>> + struct ttm_buffer_object *bo = &abo->tbo;
>>> + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
>>> + struct ttm_operation_ctx ctx = { false, false };
>>> + struct ttm_placement placement;
>>> + struct ttm_place placements;
>>> + struct ttm_resource *res;
>>> + uint64_t flags;
>>> + int r;
>>> +
>>> + /* Only for valid VRAM bo resource */
>>> + if (bo->resource->start == AMDGPU_BO_INVALID_OFFSET)
>>> + return 0;
>>> +
>>> + r = amdgpu_bo_reserve(abo, false);
>>> + if (unlikely(r))
>>> + return r;
>>> +
>>> + /* allocate GART space */
>>> + placement.num_placement = 1;
>>> + placement.placement = &placements;
>>> + placements.fpfn = 0;
>>> + placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
>>> + placements.mem_type = TTM_PL_TT;
>>> + placements.flags = bo->resource->placement;
>>> +
>>> + r = ttm_bo_mem_space(bo, &placement, &res, &ctx);
>>> + if (unlikely(r))
>>> + goto out_unreserve;
>>> +
>>> + /* compute PTE flags for this buffer object */
>>> + flags = amdgpu_ttm_tt_pte_flags(adev, NULL, bo->resource);
>>> +
>>> + /* Bind VRAM pages */
>>> + abo->gart_res = res;
>>> +
>>> + amdgpu_ttm_gart_bind(adev, bo, flags);
>>> + amdgpu_gart_invalidate_tlb(adev);
>>> +
>>> + *gpu_addr = res->start << PAGE_SHIFT;
>>> +
>>> +out_unreserve:
>>> + amdgpu_bo_unreserve(abo);
>>> + return r;
>>> +}
>>> +
>>> /*
>>> * amdgpu_ttm_recover_gart - Rebind GTT pages
>>> *
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> index 15e659575087..707654732759 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> @@ -179,6 +179,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
>>> u64 k_job_id);
>>> int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
>>> +int amdgpu_ttm_alloc_gart_vram_bo(struct amdgpu_bo *abo, u64 *gpu_addr);
>>> void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
>>> uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> index c6945c842267..d96de02c6bb9 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> @@ -148,6 +148,14 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
>>> kfree(mqd_mem_obj);
>>> return NULL;
>>> }
>>> +
>>> + retval = amdgpu_ttm_alloc_gart_vram_bo(mqd_mem_obj->gtt_mem,
>>> + &(mqd_mem_obj->gpu_addr));
>>> + if (retval) {
>>> + amdgpu_amdkfd_free_gtt_mem(node->adev, &(mqd_mem_obj->gtt_mem));
>>> + kfree(mqd_mem_obj);
>>> + return NULL;
>>> + }
>>> } else {
>>> retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd),
>>> &mqd_mem_obj);
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain
2025-12-04 22:51 ` Philip Yang
@ 2025-12-05 19:46 ` Felix Kuehling
2025-12-05 21:22 ` Philip Yang
0 siblings, 1 reply; 20+ messages in thread
From: Felix Kuehling @ 2025-12-05 19:46 UTC (permalink / raw)
To: Philip Yang, Philip Yang, amd-gfx; +Cc: christian.koenig, david.yatsin
On 2025-12-04 17:51, Philip Yang wrote:
>
>
> On 2025-12-03 12:55, Kuehling, Felix wrote:
>> On 2025-12-01 09:28, Philip Yang wrote:
>>> To reduce queue switch latency further, move MQD to VRAM domain, add
>>> AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag to allocate contiguous pages
>>> using one buddy block.
>>
>> Why does it need to be contiguous? In the next patch you're mapping
>> it in the GART anyway.
> Without AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag, amdgpu_bo_gpu_offset
> trigger this warning
>
> WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
> !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
>
> This makes senses because we pass the FB aperture address to CP, this
> should be contiguous pages.
That's right, if you query the VRAM offset of the BO, you're assuming
that it's contiguous. If you're mapping it in the GART, you wouldn't use
that VRAM offset, you'd use the GART address instead. Since you don't
want to use the mapping of the BO in the FB aperture (because that gives
you the wrong MTYPE), you should not need to use amdgpu_bo_gpu_offset at
all.
Regards,
Felix
>
> Regards,
> Philip
>>
>> Regards,
>> Felix
>>
>>
>>>
>>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
>>> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
>>> 2 files changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> index 9cd1660b8f60..c11e37915365 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>> @@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
>>> amdgpu_device *adev, size_t size,
>>> bp.size = size;
>>> bp.byte_align = PAGE_SIZE;
>>> bp.domain = domain;
>>> - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>>> + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
>>> + AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>>> bp.type = ttm_bo_type_kernel;
>>> bp.resv = NULL;
>>> bp.bo_ptr_size = sizeof(struct amdgpu_bo);
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> index a489d43d5f64..c6945c842267 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>> @@ -139,7 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct
>>> kfd_node *node,
>>> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
>>> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
>>> NUM_XCC(node->xcc_mask),
>>> - AMDGPU_GEM_DOMAIN_GTT,
>>> + AMDGPU_GEM_DOMAIN_VRAM,
>>> &(mqd_mem_obj->gtt_mem),
>>> &(mqd_mem_obj->gpu_addr),
>>> (void *)&(mqd_mem_obj->cpu_ptr), true);
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain
2025-12-05 19:46 ` Felix Kuehling
@ 2025-12-05 21:22 ` Philip Yang
0 siblings, 0 replies; 20+ messages in thread
From: Philip Yang @ 2025-12-05 21:22 UTC (permalink / raw)
To: Felix Kuehling, Philip Yang, amd-gfx; +Cc: christian.koenig, david.yatsin
On 2025-12-05 14:46, Felix Kuehling wrote:
> On 2025-12-04 17:51, Philip Yang wrote:
>>
>>
>> On 2025-12-03 12:55, Kuehling, Felix wrote:
>>> On 2025-12-01 09:28, Philip Yang wrote:
>>>> To reduce queue switch latency further, move MQD to VRAM domain, add
>>>> AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag to allocate contiguous pages
>>>> using one buddy block.
>>>
>>> Why does it need to be contiguous? In the next patch you're mapping
>>> it in the GART anyway.
>> Without AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag, amdgpu_bo_gpu_offset
>> trigger this warning
>>
>> WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
>> !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
>>
>> This makes senses because we pass the FB aperture address to CP, this
>> should be contiguous pages.
>
> That's right, if you query the VRAM offset of the BO, you're assuming
> that it's contiguous. If you're mapping it in the GART, you wouldn't
> use that VRAM offset, you'd use the GART address instead. Since you
> don't want to use the mapping of the BO in the FB aperture (because
> that gives you the wrong MTYPE), you should not need to use
> amdgpu_bo_gpu_offset at all.
With this patch, MQD move to VRAM and pass amdgpu_bo_gpu_offset to CP,
this works with FB aperture mtype, so need contiguous flag.
The next patch with GART mapping, yes, we can remove contiguous flag.
Because MQD size is small, pinned, use contiguous allocation is also
simpler to update GART mapping.
Regards,
Philip
>
> Regards,
> Felix
>
>
>>
>> Regards,
>> Philip
>>>
>>> Regards,
>>> Felix
>>>
>>>
>>>>
>>>> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
>>>> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
>>>> 2 files changed, 3 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>>> index 9cd1660b8f60..c11e37915365 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>>>> @@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct
>>>> amdgpu_device *adev, size_t size,
>>>> bp.size = size;
>>>> bp.byte_align = PAGE_SIZE;
>>>> bp.domain = domain;
>>>> - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>>>> + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
>>>> + AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>>>> bp.type = ttm_bo_type_kernel;
>>>> bp.resv = NULL;
>>>> bp.bo_ptr_size = sizeof(struct amdgpu_bo);
>>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>>> index a489d43d5f64..c6945c842267 100644
>>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>>>> @@ -139,7 +139,7 @@ static struct kfd_mem_obj *allocate_mqd(struct
>>>> kfd_node *node,
>>>> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
>>>> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
>>>> NUM_XCC(node->xcc_mask),
>>>> - AMDGPU_GEM_DOMAIN_GTT,
>>>> + AMDGPU_GEM_DOMAIN_VRAM,
>>>> &(mqd_mem_obj->gtt_mem),
>>>> &(mqd_mem_obj->gpu_addr),
>>>> (void *)&(mqd_mem_obj->cpu_ptr), true);
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2025-12-05 21:22 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-01 14:28 [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
2025-12-01 14:28 ` [PATCH v2 1/4] drm/amdkfd: Bind gfx9 MQD in GART with mtype RW Philip Yang
2025-12-03 17:40 ` Kuehling, Felix
2025-12-04 15:10 ` Philip Yang
2025-12-01 14:28 ` [PATCH v2 2/4] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
2025-12-01 17:38 ` Russell, Kent
2025-12-01 20:31 ` Philip Yang
2025-12-01 22:48 ` Russell, Kent
2025-12-03 17:45 ` Kuehling, Felix
2025-12-01 14:28 ` [PATCH v2 3/4] drm/amdkfd: Move gfx9 MQD to VRAM domain Philip Yang
2025-12-03 17:55 ` Kuehling, Felix
2025-12-04 19:28 ` Philip Yang
2025-12-04 22:51 ` Philip Yang
2025-12-05 19:46 ` Felix Kuehling
2025-12-05 21:22 ` Philip Yang
2025-12-01 14:28 ` [PATCH v2 4/4] drm/amdkfd: Map VRAM MQD on GART Philip Yang
2025-12-03 16:06 ` Christian König
2025-12-04 22:43 ` Philip Yang
2025-12-05 9:30 ` Christian König
2025-12-03 15:52 ` [PATCH v2 0/4] drm/amdkfd: Move gfx9 MQD to HBM Philip Yang
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