* [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 @ 2022-01-09 8:01 Thomas Petazzoni 2022-01-09 8:01 ` [Buildroot] [PATCH 2/2] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 Thomas Petazzoni 2022-01-09 10:33 ` [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 Yann E. MORIN 0 siblings, 2 replies; 5+ messages in thread From: Thomas Petazzoni @ 2022-01-09 8:01 UTC (permalink / raw) To: buildroot; +Cc: Thomas Petazzoni We already have support for a wide range of x86-64 CPUs, but we don't have any option to build for the most generic possible x86-64 CPU, as made available by the -march=x86-64 GCC option. This commit makes this option available in Buildroot. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> --- arch/Config.in.x86 | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 index 7aae3cafb7..794d808d96 100644 --- a/arch/Config.in.x86 +++ b/arch/Config.in.x86 @@ -81,6 +81,16 @@ config BR2_x86_prescott select BR2_X86_CPU_HAS_SSE select BR2_X86_CPU_HAS_SSE2 select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_x86_64 + bool "x86-64" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + help + This option corresponds to -march=x86-64, documented as a + "Generic CPU with 64-bit extensions" by the GCC + documentation. It is a 64-bit CPU with MMX, SSE and SSE2 + support. config BR2_x86_nocona bool "nocona" select BR2_X86_CPU_HAS_MMX @@ -281,6 +291,7 @@ config BR2_GCC_TARGET_ARCH default "pentium3" if BR2_x86_pentium3 default "pentium4" if BR2_x86_pentium4 default "prescott" if BR2_x86_prescott + default "x86-64" if BR2_x86_x86_64 default "nocona" if BR2_x86_nocona default "core2" if BR2_x86_core2 default "corei7" if BR2_x86_corei7 -- 2.33.1 _______________________________________________ buildroot mailing list buildroot@buildroot.org https://lists.buildroot.org/mailman/listinfo/buildroot ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Buildroot] [PATCH 2/2] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 2022-01-09 8:01 [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 Thomas Petazzoni @ 2022-01-09 8:01 ` Thomas Petazzoni 2022-01-09 10:36 ` Yann E. MORIN 2022-01-09 10:33 ` [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 Yann E. MORIN 1 sibling, 1 reply; 5+ messages in thread From: Thomas Petazzoni @ 2022-01-09 8:01 UTC (permalink / raw) To: buildroot; +Cc: Thomas Petazzoni In the face of the vast amount of x86-64 CPU architecture variants, Linux distributions have worked together to define "micro-architecture levels" in the x86-64 psABI, called x86-64-v2, x86-64-v3 and x86-64-v4. They standardize a set of CPU features, and GCC since its version 11.x has support for these micro-architecture levels as -march= options. It makes sense to support them in Buildroot, especially for those who want to build toolchains that aim at targeting a reasonably broad family of x86-64 processors. More details: https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x86-64-Feature-Levels Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> --- arch/Config.in.x86 | 60 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 index 794d808d96..153c8bad38 100644 --- a/arch/Config.in.x86 +++ b/arch/Config.in.x86 @@ -91,6 +91,63 @@ config BR2_x86_x86_64 "Generic CPU with 64-bit extensions" by the GCC documentation. It is a 64-bit CPU with MMX, SSE and SSE2 support. +config BR2_x86_x86_64_v2 + bool "x86-64-v2" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 + help + This option corresponds to the x86-64-v2 micro-architecture + level, as defined by the x86-64 psABI document, see + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. + + It is close to the Nehalem CPU architecture, and is + applicable for CPUs that support CMPXCHG16B, LAHF-SAHF, + POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3. +config BR2_x86_x86_64_v3 + bool "x86-64-v3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_X86_CPU_HAS_AVX + select BR2_X86_CPU_HAS_AVX2 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 + help + This option corresponds to the x86-64-v3 micro-architecture + level, as defined by the x86-64 psABI document, see + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. + + It is close to the Haswell CPU architecture, and is + applicable for CPUs that support all of x86-64-v2 plus AVX, + AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE. +config BR2_x86_x86_64_v4 + bool "x86-64-v4" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_X86_CPU_HAS_AVX + select BR2_X86_CPU_HAS_AVX2 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 + help + This option corresponds to the x86-64-v4 micro-architecture + level, as defined by the x86-64 psABI document, see + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. + + It is applicable for CPUs that support all of x86-64-v3 plus + AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL. config BR2_x86_nocona bool "nocona" select BR2_X86_CPU_HAS_MMX @@ -292,6 +349,9 @@ config BR2_GCC_TARGET_ARCH default "pentium4" if BR2_x86_pentium4 default "prescott" if BR2_x86_prescott default "x86-64" if BR2_x86_x86_64 + default "x86-64-v2" if BR2_x86_x86_64_v2 + default "x86-64-v3" if BR2_x86_x86_64_v3 + default "x86-64-v4" if BR2_x86_x86_64_v4 default "nocona" if BR2_x86_nocona default "core2" if BR2_x86_core2 default "corei7" if BR2_x86_corei7 -- 2.33.1 _______________________________________________ buildroot mailing list buildroot@buildroot.org https://lists.buildroot.org/mailman/listinfo/buildroot ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Buildroot] [PATCH 2/2] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 2022-01-09 8:01 ` [Buildroot] [PATCH 2/2] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 Thomas Petazzoni @ 2022-01-09 10:36 ` Yann E. MORIN 2022-01-09 10:46 ` Romain Naour 0 siblings, 1 reply; 5+ messages in thread From: Yann E. MORIN @ 2022-01-09 10:36 UTC (permalink / raw) To: Thomas Petazzoni; +Cc: buildroot Thomas, All, On 2022-01-09 09:01 +0100, Thomas Petazzoni spake thusly: > In the face of the vast amount of x86-64 CPU architecture variants, > Linux distributions have worked together to define "micro-architecture > levels" in the x86-64 psABI, called x86-64-v2, x86-64-v3 and > x86-64-v4. They standardize a set of CPU features, and GCC since its > version 11.x has support for these micro-architecture levels as > -march= options. > > It makes sense to support them in Buildroot, especially for those who > want to build toolchains that aim at targeting a reasonably broad > family of x86-64 processors. As for x86-64, I've added a dependency on BR2_x86_64. > More details: > > https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex > https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level > https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x86-64-Feature-Levels I've added a URL to the upstream commit too. > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Applied to master, thanks. Regards, Yann E. MORIN. > --- > arch/Config.in.x86 | 60 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 > index 794d808d96..153c8bad38 100644 > --- a/arch/Config.in.x86 > +++ b/arch/Config.in.x86 > @@ -91,6 +91,63 @@ config BR2_x86_x86_64 > "Generic CPU with 64-bit extensions" by the GCC > documentation. It is a 64-bit CPU with MMX, SSE and SSE2 > support. > +config BR2_x86_x86_64_v2 > + bool "x86-64-v2" > + select BR2_X86_CPU_HAS_MMX > + select BR2_X86_CPU_HAS_SSE > + select BR2_X86_CPU_HAS_SSE2 > + select BR2_X86_CPU_HAS_SSE3 > + select BR2_X86_CPU_HAS_SSSE3 > + select BR2_X86_CPU_HAS_SSE4 > + select BR2_X86_CPU_HAS_SSE42 > + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 > + help > + This option corresponds to the x86-64-v2 micro-architecture > + level, as defined by the x86-64 psABI document, see > + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. > + > + It is close to the Nehalem CPU architecture, and is > + applicable for CPUs that support CMPXCHG16B, LAHF-SAHF, > + POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3. > +config BR2_x86_x86_64_v3 > + bool "x86-64-v3" > + select BR2_X86_CPU_HAS_MMX > + select BR2_X86_CPU_HAS_SSE > + select BR2_X86_CPU_HAS_SSE2 > + select BR2_X86_CPU_HAS_SSE3 > + select BR2_X86_CPU_HAS_SSSE3 > + select BR2_X86_CPU_HAS_SSE4 > + select BR2_X86_CPU_HAS_SSE42 > + select BR2_X86_CPU_HAS_AVX > + select BR2_X86_CPU_HAS_AVX2 > + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 > + help > + This option corresponds to the x86-64-v3 micro-architecture > + level, as defined by the x86-64 psABI document, see > + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. > + > + It is close to the Haswell CPU architecture, and is > + applicable for CPUs that support all of x86-64-v2 plus AVX, > + AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE. > +config BR2_x86_x86_64_v4 > + bool "x86-64-v4" > + select BR2_X86_CPU_HAS_MMX > + select BR2_X86_CPU_HAS_SSE > + select BR2_X86_CPU_HAS_SSE2 > + select BR2_X86_CPU_HAS_SSE3 > + select BR2_X86_CPU_HAS_SSSE3 > + select BR2_X86_CPU_HAS_SSE4 > + select BR2_X86_CPU_HAS_SSE42 > + select BR2_X86_CPU_HAS_AVX > + select BR2_X86_CPU_HAS_AVX2 > + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 > + help > + This option corresponds to the x86-64-v4 micro-architecture > + level, as defined by the x86-64 psABI document, see > + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. > + > + It is applicable for CPUs that support all of x86-64-v3 plus > + AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL. > config BR2_x86_nocona > bool "nocona" > select BR2_X86_CPU_HAS_MMX > @@ -292,6 +349,9 @@ config BR2_GCC_TARGET_ARCH > default "pentium4" if BR2_x86_pentium4 > default "prescott" if BR2_x86_prescott > default "x86-64" if BR2_x86_x86_64 > + default "x86-64-v2" if BR2_x86_x86_64_v2 > + default "x86-64-v3" if BR2_x86_x86_64_v3 > + default "x86-64-v4" if BR2_x86_x86_64_v4 > default "nocona" if BR2_x86_nocona > default "core2" if BR2_x86_core2 > default "corei7" if BR2_x86_corei7 > -- > 2.33.1 > > _______________________________________________ > buildroot mailing list > buildroot@buildroot.org > https://lists.buildroot.org/mailman/listinfo/buildroot -- .-----------------.--------------------.------------------.--------------------. | Yann E. MORIN | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: | | +33 662 376 056 | Software Designer | \ / CAMPAIGN | ___ | | +33 561 099 427 `------------.-------: X AGAINST | \e/ There is no | | http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL | v conspiracy. | '------------------------------^-------^------------------^--------------------' _______________________________________________ buildroot mailing list buildroot@buildroot.org https://lists.buildroot.org/mailman/listinfo/buildroot ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Buildroot] [PATCH 2/2] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 2022-01-09 10:36 ` Yann E. MORIN @ 2022-01-09 10:46 ` Romain Naour 0 siblings, 0 replies; 5+ messages in thread From: Romain Naour @ 2022-01-09 10:46 UTC (permalink / raw) To: Yann E. MORIN, Thomas Petazzoni; +Cc: buildroot Hello Thomas, Yann, Le 09/01/2022 à 11:36, Yann E. MORIN a écrit : > Thomas, All, > > On 2022-01-09 09:01 +0100, Thomas Petazzoni spake thusly: >> In the face of the vast amount of x86-64 CPU architecture variants, >> Linux distributions have worked together to define "micro-architecture >> levels" in the x86-64 psABI, called x86-64-v2, x86-64-v3 and >> x86-64-v4. They standardize a set of CPU features, and GCC since its >> version 11.x has support for these micro-architecture levels as >> -march= options. >> >> It makes sense to support them in Buildroot, especially for those who >> want to build toolchains that aim at targeting a reasonably broad >> family of x86-64 processors. > > As for x86-64, I've added a dependency on BR2_x86_64. > >> More details: >> >> https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex >> https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level >> https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x86-64-Feature-Levels > > I've added a URL to the upstream commit too. Sorry I'm late, but I had a look at this series to use x86-64-v3 and x86-64-v4 for Qemu runtime testing. There are some limitation with the current version of Qemu (6.2.0): "Note that TCG is not capable of supporting the 2 newest ABI levels currently: * x86-64-abi3: CPUID.01H:ECX.fma [bit 12] CPUID.01H:ECX.avx [bit 28] CPUID.01H:ECX.f16c [bit 29] CPUID.07H:EBX.avx2 [bit 5] * x86-64-abi4: CPUID.01H:ECX.pcid [bit 17] CPUID.01H:ECX.x2apic [bit 21] CPUID.01H:ECX.tsc-deadline [bit 24] CPUID.07H:EBX.invpcid [bit 10] CPUID.07H:EBX.avx512f [bit 16] CPUID.07H:EBX.avx512dq [bit 17] CPUID.07H:EBX.rdseed [bit 18] CPUID.07H:EBX.avx512cd [bit 28] CPUID.07H:EBX.avx512bw [bit 30] CPUID.07H:EBX.avx512vl [bit 31] CPUID.80000001H:ECX.3dnowprefetch [bit 8] CPUID.0DH:EAX.xsavec [bit 1]" https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg00170.html I wanted to reply to add this info in the commit log. Best regards, Romain > >> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> > > Applied to master, thanks. > > Regards, > Yann E. MORIN. > _______________________________________________ buildroot mailing list buildroot@buildroot.org https://lists.buildroot.org/mailman/listinfo/buildroot ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 2022-01-09 8:01 [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 Thomas Petazzoni 2022-01-09 8:01 ` [Buildroot] [PATCH 2/2] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 Thomas Petazzoni @ 2022-01-09 10:33 ` Yann E. MORIN 1 sibling, 0 replies; 5+ messages in thread From: Yann E. MORIN @ 2022-01-09 10:33 UTC (permalink / raw) To: Thomas Petazzoni; +Cc: buildroot Thomas, All, On 2022-01-09 09:01 +0100, Thomas Petazzoni spake thusly: > We already have support for a wide range of x86-64 CPUs, but we don't > have any option to build for the most generic possible x86-64 CPU, as > made available by the -march=x86-64 GCC option. As discussed, it only really makes sense to use them as a 64-bit CPU, so I've added a dependency on BR2_x86_64. > This commit makes this option available in Buildroot. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Applied to master, thanks. Regards, Yann E. MORIN. > --- > arch/Config.in.x86 | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 > index 7aae3cafb7..794d808d96 100644 > --- a/arch/Config.in.x86 > +++ b/arch/Config.in.x86 > @@ -81,6 +81,16 @@ config BR2_x86_prescott > select BR2_X86_CPU_HAS_SSE > select BR2_X86_CPU_HAS_SSE2 > select BR2_X86_CPU_HAS_SSE3 > +config BR2_x86_x86_64 > + bool "x86-64" > + select BR2_X86_CPU_HAS_MMX > + select BR2_X86_CPU_HAS_SSE > + select BR2_X86_CPU_HAS_SSE2 > + help > + This option corresponds to -march=x86-64, documented as a > + "Generic CPU with 64-bit extensions" by the GCC > + documentation. It is a 64-bit CPU with MMX, SSE and SSE2 > + support. > config BR2_x86_nocona > bool "nocona" > select BR2_X86_CPU_HAS_MMX > @@ -281,6 +291,7 @@ config BR2_GCC_TARGET_ARCH > default "pentium3" if BR2_x86_pentium3 > default "pentium4" if BR2_x86_pentium4 > default "prescott" if BR2_x86_prescott > + default "x86-64" if BR2_x86_x86_64 > default "nocona" if BR2_x86_nocona > default "core2" if BR2_x86_core2 > default "corei7" if BR2_x86_corei7 > -- > 2.33.1 > > _______________________________________________ > buildroot mailing list > buildroot@buildroot.org > https://lists.buildroot.org/mailman/listinfo/buildroot -- .-----------------.--------------------.------------------.--------------------. | Yann E. MORIN | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: | | +33 662 376 056 | Software Designer | \ / CAMPAIGN | ___ | | +33 561 099 427 `------------.-------: X AGAINST | \e/ There is no | | http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL | v conspiracy. | '------------------------------^-------^------------------^--------------------' _______________________________________________ buildroot mailing list buildroot@buildroot.org https://lists.buildroot.org/mailman/listinfo/buildroot ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-01-09 10:46 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-01-09 8:01 [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 Thomas Petazzoni 2022-01-09 8:01 ` [Buildroot] [PATCH 2/2] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 Thomas Petazzoni 2022-01-09 10:36 ` Yann E. MORIN 2022-01-09 10:46 ` Romain Naour 2022-01-09 10:33 ` [Buildroot] [PATCH 1/2] arch/Config.in.x86: add option for -march=x86-64 Yann E. MORIN
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