* [Buildroot] [RFC PATCH 2/2] package/gcc: microblaze atomic support
2025-07-01 9:30 [Buildroot] [RFC PATCH 1/2] package/Makefile.in: microblaze: enable -mxl-barrel-shift as default Neal Frager via buildroot
@ 2025-07-01 9:30 ` Neal Frager via buildroot
2025-07-01 9:40 ` Frager, Neal via buildroot
2025-07-01 10:13 ` [Buildroot] [RFC PATCH 1/2] package/Makefile.in: microblaze: enable -mxl-barrel-shift as default Thomas Petazzoni via buildroot
1 sibling, 1 reply; 5+ messages in thread
From: Neal Frager via buildroot @ 2025-07-01 9:30 UTC (permalink / raw)
To: buildroot; +Cc: Giulio Benetti, Romain Naour, Thomas Petazzoni, Neal Frager
This patch adds atomic test and set support for the microblaze arch. A patch
is required to use atomic test and set with gcc 14 and 15 which will soon be
submitted upstream.
In order to atomic instructions to work, the microblaze CFLAG
-mxl-barrel-shift must be enabled.
As I have only tested this with gcc 14 so far, I am not sure if I have handled
all potential cases. For this reason, I am requesting comment on this patch
before submitting a final version.
To test this patch:
$ cat > .config<<EOF
BR2_microblazeel=y
BR2_GCC_VERSION_14_X=y
BR2_TOOLCHAIN_BUILDROOT_CXX=y
BR2_PACKAGE_ACPITOOL=y
EOF
$ make olddefconfig
$ make
Fixes: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118280
Upstream: to be done with final version
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
...laze-add-atomic-test-and-set-support.patch | 158 ++++++++++++++++++
package/gcc/Config.in.host | 6 -
2 files changed, 158 insertions(+), 6 deletions(-)
create mode 100644 package/gcc/14.3.0/0003-microblaze-add-atomic-test-and-set-support.patch
diff --git a/package/gcc/14.3.0/0003-microblaze-add-atomic-test-and-set-support.patch b/package/gcc/14.3.0/0003-microblaze-add-atomic-test-and-set-support.patch
new file mode 100644
index 0000000000..a79659301d
--- /dev/null
+++ b/package/gcc/14.3.0/0003-microblaze-add-atomic-test-and-set-support.patch
@@ -0,0 +1,158 @@
+From fe1a0a590c4ed079db36c34b0907f0e99c6dd31f Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager@amd.com>
+Date: Mon, 30 Jun 2025 10:26:49 +0100
+Subject: [PATCH] microblaze: add atomic test and set support
+
+This patch adds atomic test and set support for the microblaze arch.
+
+Upstream: to be done soon
+
+Signed-off-by: Neal Frager <neal.frager@amd.com>
+---
+ gcc/config/microblaze/microblaze.md | 6 +-
+ gcc/config/microblaze/sync.md | 103 +++++++++++++++++++++++-----
+ 2 files changed, 90 insertions(+), 19 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index f1f57e6d702..36d786b1d10 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -43,6 +43,10 @@
+ (UNSPEC_TLS 106) ;; jump table
+ (UNSPEC_SET_TEXT 107) ;; set text start
+ (UNSPEC_TEXT 108) ;; data text relative
++ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool)
++ (UNSPECV_CAS_VAL 202) ;; compare and swap (val)
++ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem)
++ (UNSPECV_ATS 204) ;; atomic test and set
+ ])
+
+ (define_c_enum "unspec" [
+@@ -79,7 +83,7 @@
+ ;; bshift Shift operations
+
+ (define_attr "type"
+- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
++"unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap,atomic"
+ (const_string "unknown"))
+
+ ;; Main data type used by the insn
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index 939168a2d0e..b5fbe1431cc 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -18,26 +18,93 @@
+ ;; <http://www.gnu.org/licenses/>.
+
+ (define_insn "atomic_compare_and_swapsi"
+- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
+- (match_operand:SI 1 "register_operand" "=&d") ;; val output
+- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
+- (match_operand:SI 3 "register_operand" "d") ;; expected value
+- (match_operand:SI 4 "register_operand" "d") ;; desired value
+- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
+- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
+- (match_operand:SI 7 "const_int_operand" "") ;; mod_f
++[(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
++ (unspec_volatile:SI
++ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
++ (match_operand:SI 3 "register_operand" "d") ;; expected value
++ (match_operand:SI 4 "register_operand" "d")] ;; desired value
++ UNSPECV_CAS_BOOL))
++ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
++ (set (match_dup 2)
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
++ (match_operand:SI 5 "const_int_operand" "") ;; is_weak
++ (match_operand:SI 6 "const_int_operand" "") ;; mod_s
++ (match_operand:SI 7 "const_int_operand" "") ;; mod_f
+ (clobber (match_scratch:SI 8 "=&d"))]
+ ""
+ {
+- output_asm_insn ("addc \tr0,r0,r0", operands);
+- output_asm_insn ("lwx \t%1,%y2,r0", operands);
+- output_asm_insn ("addic\t%8,r0,0", operands);
+- output_asm_insn ("bnei \t%8,.-8", operands);
+- output_asm_insn ("cmp \t%0,%1,%3", operands);
+- output_asm_insn ("bnei \t%0,.+16", operands);
+- output_asm_insn ("swx \t%4,%y2,r0", operands);
+- output_asm_insn ("addic\t%8,r0,0", operands);
+- output_asm_insn ("bnei \t%8,.-28", operands);
+- return "";
++ return "add \t%0,r0,r0\n\t"
++ "lwx \t%1,%y2,r0\n\t"
++ "addic\t%8,r0,0\n\t"
++ "bnei \t%8,.-8\n\t"
++ "cmp \t%8,%1,%3\n\t"
++ "bnei \t%8,.+20\n\t"
++ "swx \t%4,%y2,r0\n\t"
++ "addic\t%8,r0,0\n\t"
++ "bnei \t%8,.-28\n\t"
++ "addi \t%0,r0,1";
+ }
++ [(set_attr "type" "atomic")
++ (set_attr "mode" "SI")
++ (set_attr "length" "40")]
++)
++
++;;
++;; MicroBlaze has no atomic load/store instruction pair for QImode
++;;
++;; Use load/store reserved word with necessary mem align,shift,mask magic
++;;
++(define_insn "atomic_test_and_set"
++ [(set (match_operand:QI 0 "register_operand" "=&d") ;; bool output
++ (unspec_volatile:QI
++ [(match_operand:QI 1 "nonimmediate_operand" "+Q") ;; memory
++ (match_operand:SI 2 "const_int_operand" "") ;; model
++ ]
++ UNSPECV_ATS))
++ (clobber (match_scratch:SI 3 "=&d")) ; old word
++ (clobber (match_scratch:SI 4 "=&d")) ; tmp
++ (clobber (match_scratch:SI 5 "=&d")) ; aligned address
++ (clobber (match_scratch:SI 6 "=&d")) ; shift
++ (clobber (match_scratch:SI 7 "=&d")) ; mask
++ (clobber (match_scratch:SI 8 "=&d")) ; old value
++ ]
++ "TARGET_BARREL_SHIFT"
++ {
++ return
++ /* word align memory address, compute shift */
++ "andi \t%5,%y1,-4\n\t"
++ "andi \t%6,%y1,3\n\t"
++ "bslli \t%6,%6,3\n\t"
++
++ /* compute set value and mask */
++ "addik \t%7,r0,1\n\t"
++ "bsll \t%7,%7,%6\n\t"
++
++ /* Load and reserve word */
++ "lwx \t%3,%5,r0\n\t"
++ "addic\t%4,r0,0\n\t"
++ "bnei \t%4,.-8\n\t"
++
++ /* Compute old value */
++ "and \t%8,%3,%7\n\t"
++
++ /* Test Old Value */
++ "cmp \t%4,%8,r0\n\t"
++ "bnei \t%4,.+20\n\t"
++
++ /* Compute Set Word */
++ "or \t%4,%3,%7\n\t"
++
++ /* Try Reserved store */
++ "swx \t%4,%5,r0\n\t"
++ "addic\t%4,r0,0\n\t"
++ "bnei \t%4,.-36\n\t"
++
++ /* Set result */
++ "bsrl \t%0,%8,%6\n\t";
++ }
++ [(set_attr "type" "atomic")
++ (set_attr "mode" "QI")
++ (set_attr "length" "64")]
+ )
+--
+2.25.1
+
diff --git a/package/gcc/Config.in.host b/package/gcc/Config.in.host
index 8640280fdf..e6c10d3e20 100644
--- a/package/gcc/Config.in.host
+++ b/package/gcc/Config.in.host
@@ -36,9 +36,6 @@ config BR2_GCC_VERSION_14_X
# powerpc spe support has been deprecated since gcc 8.x.
# https://gcc.gnu.org/ml/gcc/2018-04/msg00102.html
depends on !BR2_POWERPC_CPU_HAS_SPE
- # Severely broken on Microblaze
- # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118280
- depends on !BR2_microblaze
select BR2_TOOLCHAIN_GCC_AT_LEAST_14
config BR2_GCC_VERSION_15_X
@@ -46,9 +43,6 @@ config BR2_GCC_VERSION_15_X
# powerpc spe support has been deprecated since gcc 8.x.
# https://gcc.gnu.org/ml/gcc/2018-04/msg00102.html
depends on !BR2_POWERPC_CPU_HAS_SPE
- # Severely broken on Microblaze
- # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118280
- depends on !BR2_microblaze
select BR2_TOOLCHAIN_GCC_AT_LEAST_15
endchoice
--
2.25.1
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