* [Buildroot] [PATCH v2 1/4] package/elf2flt: add RISC-V 32-bits support
2022-12-17 5:13 [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
@ 2022-12-17 5:13 ` Jesse Taube
2022-12-17 5:13 ` [Buildroot] [PATCH v2 2/4] package/uclibc: Add RISC-V 32-bit support Jesse Taube
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Jesse Taube @ 2022-12-17 5:13 UTC (permalink / raw)
To: buildroot
Cc: Mark Corbin, Jesse Taube, Thomas Petazzoni, Romain Naour,
Charles Lohr, Yimin Gu, Giulio Benetti
From: Yimin Gu <ustcymgu@gmail.com>
Enable selecting elf2flt for RISC-V 32-bits no MMU builds.
Also modify the package Makefile.in file to add the -fPIC option to
the target CFLAGS for RISC-V 32-bits no MMU builds.
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
Cc: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
package/Makefile.in | 4 +-
.../0007-Added-RISC-V-32-bit-support.patch | 87 +++++++++++++++++++
2 files changed, 89 insertions(+), 2 deletions(-)
create mode 100644 package/elf2flt/0007-Added-RISC-V-32-bit-support.patch
diff --git a/package/Makefile.in b/package/Makefile.in
index 43d214bcbe..4f554f48eb 100644
--- a/package/Makefile.in
+++ b/package/Makefile.in
@@ -41,7 +41,7 @@ GNU_TARGET_NAME = $(ARCH)-$(TARGET_VENDOR)-$(TARGET_OS)-$(LIBC)$(ABI)
# FLAT binary format needs uclinux, except RISC-V 64-bits which needs
# the regular linux name.
-ifeq ($(BR2_BINFMT_FLAT):$(BR2_RISCV_64),y:)
+ifeq ($(BR2_BINFMT_FLAT):$(BR2_riscv),y:)
TARGET_OS = uclinux
else
TARGET_OS = linux
@@ -174,7 +174,7 @@ TARGET_CXXFLAGS += -fno-dwarf2-cfi-asm
endif
ifeq ($(BR2_BINFMT_FLAT),y)
-ifeq ($(BR2_RISCV_64),y)
+ifeq ($(BR2_riscv),y)
TARGET_CFLAGS += -fPIC
endif
ifeq ($(BR2_BINFMT_FLAT_ONE),y)
diff --git a/package/elf2flt/0007-Added-RISC-V-32-bit-support.patch b/package/elf2flt/0007-Added-RISC-V-32-bit-support.patch
new file mode 100644
index 0000000000..93ee955552
--- /dev/null
+++ b/package/elf2flt/0007-Added-RISC-V-32-bit-support.patch
@@ -0,0 +1,87 @@
+From 4a4e8551b7f14ecd2092debbe256c667497a256d Mon Sep 17 00:00:00 2001
+From: Yimin Gu <ustcymgu@gmail.com>
+Date: Wed, 14 Dec 2022 06:49:46 -0500
+Subject: [PATCH] Added RISC-V 32-bit support
+
+Allow elf2flt to work with RISC-V 32-bit targets. With these changes, the
+uclibc toolchain and busybox can work fine for rv32 no MMU systems with
+no noticable problem.
+Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
+[Add more ELF relco types and edit commit message]
+Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
+---
+ elf2flt.c | 18 +++++++++++++++---
+ ld-elf2flt.c | 2 +-
+ 2 files changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/elf2flt.c b/elf2flt.c
+index 99ad2a8..23c9907 100644
+--- a/elf2flt.c
++++ b/elf2flt.c
+@@ -81,7 +81,7 @@ const char *elf2flt_progname;
+ #include <elf/v850.h>
+ #elif defined(TARGET_xtensa)
+ #include <elf/xtensa.h>
+-#elif defined(TARGET_riscv64)
++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
+ #include <elf/riscv.h>
+ #endif
+
+@@ -127,6 +127,8 @@ const char *elf2flt_progname;
+ #define ARCH "xtensa"
+ #elif defined(TARGET_riscv64)
+ #define ARCH "riscv64"
++#elif defined(TARGET_riscv32)
++#define ARCH "riscv32"
+ #else
+ #error "Don't know how to support your CPU architecture??"
+ #endif
+@@ -351,7 +353,8 @@ ro_reloc_data_section_should_be_in_text(asection *s)
+ {
+ if ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) ==
+ (SEC_DATA | SEC_READONLY | SEC_RELOC)) {
+-#if defined(TARGET_m68k) || defined(TARGET_riscv64) || defined(TARGET_xtensa)
++#if defined(TARGET_m68k) || defined(TARGET_riscv64) || \
++ defined(TARGET_riscv32) || defined(TARGET_xtensa)
+ if (!strcmp(".eh_frame", s->name))
+ return false;
+ #endif
+@@ -851,12 +854,21 @@ output_relocs (
+ break;
+ default:
+ goto bad_resolved_reloc;
+-#elif defined(TARGET_riscv64)
++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
+ case R_RISCV_32_PCREL:
++ case R_RISCV_ADD8:
++ case R_RISCV_ADD16:
+ case R_RISCV_ADD32:
+ case R_RISCV_ADD64:
++ case R_RISCV_SUB6:
++ case R_RISCV_SUB8:
++ case R_RISCV_SUB16:
+ case R_RISCV_SUB32:
+ case R_RISCV_SUB64:
++ case R_RISCV_SET6:
++ case R_RISCV_SET8:
++ case R_RISCV_SET16:
++ case R_RISCV_SET32:
+ continue;
+ case R_RISCV_32:
+ case R_RISCV_64:
+diff --git a/ld-elf2flt.c b/ld-elf2flt.c
+index 75ee1bb..68b2a4a 100644
+--- a/ld-elf2flt.c
++++ b/ld-elf2flt.c
+@@ -327,7 +327,7 @@ static int do_final_link(void)
+ /* riscv adds a global pointer symbol to the linker file with the
+ "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
+ the entire line for other architectures. */
+- if (streq(TARGET_CPU, "riscv64"))
++ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
+ append_sed(&sed, "^RISCV_GP:", "");
+ else
+ append_sed(&sed, "^RISCV_GP:", NULL);
+--
+2.38.1
+
--
2.39.0
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [Buildroot] [PATCH v2 2/4] package/uclibc: Add RISC-V 32-bit support
2022-12-17 5:13 [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
2022-12-17 5:13 ` [Buildroot] [PATCH v2 1/4] package/elf2flt: add RISC-V 32-bits support Jesse Taube
@ 2022-12-17 5:13 ` Jesse Taube
2023-09-30 21:31 ` Romain Naour
2022-12-17 5:13 ` [Buildroot] [PATCH v2 3/4] arch: Enable support for RISC-V 32-bit NOMMU Jesse Taube
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Jesse Taube @ 2022-12-17 5:13 UTC (permalink / raw)
To: buildroot
Cc: Mark Corbin, Jesse Taube, Thomas Petazzoni, Romain Naour,
Charles Lohr, Yimin Gu, Giulio Benetti
From: Yimin Gu <ustcymgu@gmail.com>
riscv32 can be built with or without MMU. This patch adds support for
building uClibc for riscv32. The patch is based on the
existing riscv64 support.
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
Cc: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
.../uclibc/0001-RISC-V-32-bit-support.patch | 145 ++++++++++++++++++
package/uclibc/Config.in | 2 +
2 files changed, 147 insertions(+)
create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch
diff --git a/package/uclibc/0001-RISC-V-32-bit-support.patch b/package/uclibc/0001-RISC-V-32-bit-support.patch
new file mode 100644
index 0000000000..71fb401519
--- /dev/null
+++ b/package/uclibc/0001-RISC-V-32-bit-support.patch
@@ -0,0 +1,145 @@
+From 537b2ef6350fdf7604d59bc2a50388cb98045d7f Mon Sep 17 00:00:00 2001
+From: Yimin Gu <ustcymgu at gmail.com>
+Date: Mon, 1 Aug 2022 15:22:40 +0900
+Subject: [PATCH] uclibc: RISC-V 32-bit support
+
+Added 32-bit RISC-V support. With these changes, elf2flt patch
+6055525082d1, and kernel patch 700b2f0ce371, no MMU rv32 buildroot
+system can work without any noticable problem.
+
+There's no substantial code change except definations and config
+options.
+
+Signed-off-by: Yimin Gu <ustcymgu at gmail.com>
+---
+ Rules.mak | 2 ++
+ extra/Configs/Config.in | 9 +++++++++
+ extra/Configs/Config.riscv32 | 14 ++++++++++++++
+ libc/sysdeps/linux/riscv32 | 1 +
+ libc/sysdeps/linux/riscv64/bits/wordsize.h | 3 ++-
+ libc/sysdeps/linux/riscv64/sys/asm.h | 6 +++++-
+ 6 files changed, 33 insertions(+), 2 deletions(-)
+ create mode 100644 extra/Configs/Config.riscv32
+ create mode 120000 libc/sysdeps/linux/riscv32
+
+diff --git a/Rules.mak b/Rules.mak
+index 3fb64c728..71a14fc38 100644
+--- a/Rules.mak
++++ b/Rules.mak
+@@ -305,6 +305,7 @@ ifneq ($(TARGET_ARCH),c6x)
+ ifneq ($(TARGET_ARCH),h8300)
+ ifneq ($(TARGET_ARCH),arc)
+ ifneq ($(TARGET_ARCH),aarch64)
++ifneq ($(TARGET_ARCH),riscv32)
+ CPU_CFLAGS-y += -msoft-float
+ endif
+ endif
+@@ -316,6 +317,7 @@ endif
+ endif
+ endif
+ endif
++endif
+
+ ifeq ($(TARGET_ARCH),aarch64)
+ CPU_CFLAGS-y += -ftls-model=initial-exec
+diff --git a/extra/Configs/Config.in b/extra/Configs/Config.in
+index a58ceb265..5e6af800d 100644
+--- a/extra/Configs/Config.in
++++ b/extra/Configs/Config.in
+@@ -39,6 +39,7 @@ choice
+ default TARGET_or1k if DESIRED_TARGET_ARCH = "or1k"
+ default TARGET_powerpc if DESIRED_TARGET_ARCH = "powerpc"
+ default TARGET_riscv64 if DESIRED_TARGET_ARCH = "riscv64"
++ default TARGET_riscv32 if DESIRED_TARGET_ARCH = "riscv32"
+ default TARGET_sh if DESIRED_TARGET_ARCH = "sh"
+ default TARGET_sparc if DESIRED_TARGET_ARCH = "sparc"
+ default TARGET_sparc64 if DESIRED_TARGET_ARCH = "sparc64"
+@@ -125,6 +126,9 @@ config TARGET_powerpc
+ config TARGET_riscv64
+ bool "riscv64"
+
++config TARGET_riscv32
++ bool "riscv32"
++
+ config TARGET_sh
+ bool "superh"
+
+@@ -240,6 +244,10 @@ if TARGET_riscv64
+ source "extra/Configs/Config.riscv64"
+ endif
+
++if TARGET_riscv32
++source "extra/Configs/Config.riscv32"
++endif
++
+ if TARGET_sh
+ source "extra/Configs/Config.sh"
+ endif
+@@ -538,6 +546,7 @@ config UCLIBC_HAS_LINUXTHREADS
+ select UCLIBC_HAS_REALTIME
+ depends on !TARGET_aarch64 && \
+ !TARGET_riscv64 && \
++ !TARGET_riscv32 && \
+ !TARGET_metag
+ help
+ If you want to compile uClibc with Linuxthreads support, then answer Y.
+diff --git a/extra/Configs/Config.riscv32 b/extra/Configs/Config.riscv32
+new file mode 100644
+index 000000000..304d30f70
+--- /dev/null
++++ b/extra/Configs/Config.riscv32
+@@ -0,0 +1,14 @@
++#
++# For a description of the syntax of this configuration file,
++# see extra/config/Kconfig-language.txt
++#
++
++config TARGET_ARCH
++ string
++ default "riscv32"
++
++config FORCE_OPTIONS_FOR_ARCH
++ bool
++ default y
++ select ARCH_LITTLE_ENDIAN
++ select ARCH_HAS_MMU
+diff --git a/libc/sysdeps/linux/riscv32 b/libc/sysdeps/linux/riscv32
+new file mode 120000
+index 000000000..11677ef05
+--- /dev/null
++++ b/libc/sysdeps/linux/riscv32
+@@ -0,0 +1 @@
++riscv64
+\ No newline at end of file
+diff --git a/libc/sysdeps/linux/riscv64/bits/wordsize.h b/libc/sysdeps/linux/riscv64/bits/wordsize.h
+index 67a16ba62..1fc649aad 100644
+--- a/libc/sysdeps/linux/riscv64/bits/wordsize.h
++++ b/libc/sysdeps/linux/riscv64/bits/wordsize.h
+@@ -25,5 +25,6 @@
+ #if __riscv_xlen == 64
+ # define __WORDSIZE_TIME64_COMPAT32 1
+ #else
+-# error "rv32i-based targets are not supported"
++# define __WORDSIZE_TIME64_COMPAT32 1
++// # warning "rv32i-based targets are experimental"
+ #endif
+diff --git a/libc/sysdeps/linux/riscv64/sys/asm.h b/libc/sysdeps/linux/riscv64/sys/asm.h
+index ddb84b683..3c94c9a70 100644
+--- a/libc/sysdeps/linux/riscv64/sys/asm.h
++++ b/libc/sysdeps/linux/riscv64/sys/asm.h
+@@ -26,7 +26,11 @@
+ # define REG_S sd
+ # define REG_L ld
+ #elif __riscv_xlen == 32
+-# error "rv32i-based targets are not supported"
++# define PTRLOG 2
++# define SZREG 4
++# define REG_S sw
++# define REG_L lw
++// # warning "rv32i-based targets are experimental"
+ #else
+ # error __riscv_xlen must equal 32 or 64
+ #endif
+--
+2.37.1
+
diff --git a/package/uclibc/Config.in b/package/uclibc/Config.in
index 2555487f06..a1e9305ca0 100644
--- a/package/uclibc/Config.in
+++ b/package/uclibc/Config.in
@@ -17,6 +17,7 @@ config BR2_PACKAGE_UCLIBC_ARCH_SUPPORTS
default y if BR2_powerpc
# see libc/sysdeps/linux/riscv64/sys/asm.h
default y if BR2_RISCV_64 && (BR2_RISCV_ABI_LP64 || BR2_RISCV_ABI_LP64D)
+ default y if BR2_RISCV_32
default y if BR2_sh4
default y if BR2_sh4eb
default y if BR2_sparc
@@ -138,6 +139,7 @@ config BR2_UCLIBC_TARGET_ARCH
default "i386" if BR2_i386
default "x86_64" if BR2_x86_64
default "riscv64" if BR2_RISCV_64
+ default "riscv32" if BR2_RISCV_32
config BR2_UCLIBC_MIPS_ABI
string
--
2.39.0
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https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Buildroot] [PATCH v2 2/4] package/uclibc: Add RISC-V 32-bit support
2022-12-17 5:13 ` [Buildroot] [PATCH v2 2/4] package/uclibc: Add RISC-V 32-bit support Jesse Taube
@ 2023-09-30 21:31 ` Romain Naour
0 siblings, 0 replies; 12+ messages in thread
From: Romain Naour @ 2023-09-30 21:31 UTC (permalink / raw)
To: Jesse Taube, buildroot
Cc: Mark Corbin, Thomas Petazzoni, Romain Naour, Charles Lohr,
Yimin Gu, Giulio Benetti
Hello,
Le 17/12/2022 à 06:13, Jesse Taube a écrit :
> From: Yimin Gu <ustcymgu@gmail.com>
>
> riscv32 can be built with or without MMU. This patch adds support for
> building uClibc for riscv32. The patch is based on the
> existing riscv64 support.
>
> Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
> Cc: Jesse Taube <Mr.Bossman075@gmail.com>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> .../uclibc/0001-RISC-V-32-bit-support.patch | 145 ++++++++++++++++++
> package/uclibc/Config.in | 2 +
> 2 files changed, 147 insertions(+)
> create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch
>
> diff --git a/package/uclibc/0001-RISC-V-32-bit-support.patch b/package/uclibc/0001-RISC-V-32-bit-support.patch
> new file mode 100644
> index 0000000000..71fb401519
> --- /dev/null
> +++ b/package/uclibc/0001-RISC-V-32-bit-support.patch
Since then this patch has been merged in uClibc-ng repository and released with
v1.0.43.
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/commit/?id=0a5466d8d53bc8045ff56ff76cc1880aa85761c2
So, AFAIK this patch can be removed from this series.
Best regards,
Romain
> @@ -0,0 +1,145 @@
> +From 537b2ef6350fdf7604d59bc2a50388cb98045d7f Mon Sep 17 00:00:00 2001
> +From: Yimin Gu <ustcymgu at gmail.com>
> +Date: Mon, 1 Aug 2022 15:22:40 +0900
> +Subject: [PATCH] uclibc: RISC-V 32-bit support
> +
> +Added 32-bit RISC-V support. With these changes, elf2flt patch
> +6055525082d1, and kernel patch 700b2f0ce371, no MMU rv32 buildroot
> +system can work without any noticable problem.
> +
> +There's no substantial code change except definations and config
> +options.
> +
> +Signed-off-by: Yimin Gu <ustcymgu at gmail.com>
> +---
> + Rules.mak | 2 ++
> + extra/Configs/Config.in | 9 +++++++++
> + extra/Configs/Config.riscv32 | 14 ++++++++++++++
> + libc/sysdeps/linux/riscv32 | 1 +
> + libc/sysdeps/linux/riscv64/bits/wordsize.h | 3 ++-
> + libc/sysdeps/linux/riscv64/sys/asm.h | 6 +++++-
> + 6 files changed, 33 insertions(+), 2 deletions(-)
> + create mode 100644 extra/Configs/Config.riscv32
> + create mode 120000 libc/sysdeps/linux/riscv32
> +
> +diff --git a/Rules.mak b/Rules.mak
> +index 3fb64c728..71a14fc38 100644
> +--- a/Rules.mak
> ++++ b/Rules.mak
> +@@ -305,6 +305,7 @@ ifneq ($(TARGET_ARCH),c6x)
> + ifneq ($(TARGET_ARCH),h8300)
> + ifneq ($(TARGET_ARCH),arc)
> + ifneq ($(TARGET_ARCH),aarch64)
> ++ifneq ($(TARGET_ARCH),riscv32)
> + CPU_CFLAGS-y += -msoft-float
> + endif
> + endif
> +@@ -316,6 +317,7 @@ endif
> + endif
> + endif
> + endif
> ++endif
> +
> + ifeq ($(TARGET_ARCH),aarch64)
> + CPU_CFLAGS-y += -ftls-model=initial-exec
> +diff --git a/extra/Configs/Config.in b/extra/Configs/Config.in
> +index a58ceb265..5e6af800d 100644
> +--- a/extra/Configs/Config.in
> ++++ b/extra/Configs/Config.in
> +@@ -39,6 +39,7 @@ choice
> + default TARGET_or1k if DESIRED_TARGET_ARCH = "or1k"
> + default TARGET_powerpc if DESIRED_TARGET_ARCH = "powerpc"
> + default TARGET_riscv64 if DESIRED_TARGET_ARCH = "riscv64"
> ++ default TARGET_riscv32 if DESIRED_TARGET_ARCH = "riscv32"
> + default TARGET_sh if DESIRED_TARGET_ARCH = "sh"
> + default TARGET_sparc if DESIRED_TARGET_ARCH = "sparc"
> + default TARGET_sparc64 if DESIRED_TARGET_ARCH = "sparc64"
> +@@ -125,6 +126,9 @@ config TARGET_powerpc
> + config TARGET_riscv64
> + bool "riscv64"
> +
> ++config TARGET_riscv32
> ++ bool "riscv32"
> ++
> + config TARGET_sh
> + bool "superh"
> +
> +@@ -240,6 +244,10 @@ if TARGET_riscv64
> + source "extra/Configs/Config.riscv64"
> + endif
> +
> ++if TARGET_riscv32
> ++source "extra/Configs/Config.riscv32"
> ++endif
> ++
> + if TARGET_sh
> + source "extra/Configs/Config.sh"
> + endif
> +@@ -538,6 +546,7 @@ config UCLIBC_HAS_LINUXTHREADS
> + select UCLIBC_HAS_REALTIME
> + depends on !TARGET_aarch64 && \
> + !TARGET_riscv64 && \
> ++ !TARGET_riscv32 && \
> + !TARGET_metag
> + help
> + If you want to compile uClibc with Linuxthreads support, then answer Y.
> +diff --git a/extra/Configs/Config.riscv32 b/extra/Configs/Config.riscv32
> +new file mode 100644
> +index 000000000..304d30f70
> +--- /dev/null
> ++++ b/extra/Configs/Config.riscv32
> +@@ -0,0 +1,14 @@
> ++#
> ++# For a description of the syntax of this configuration file,
> ++# see extra/config/Kconfig-language.txt
> ++#
> ++
> ++config TARGET_ARCH
> ++ string
> ++ default "riscv32"
> ++
> ++config FORCE_OPTIONS_FOR_ARCH
> ++ bool
> ++ default y
> ++ select ARCH_LITTLE_ENDIAN
> ++ select ARCH_HAS_MMU
> +diff --git a/libc/sysdeps/linux/riscv32 b/libc/sysdeps/linux/riscv32
> +new file mode 120000
> +index 000000000..11677ef05
> +--- /dev/null
> ++++ b/libc/sysdeps/linux/riscv32
> +@@ -0,0 +1 @@
> ++riscv64
> +\ No newline at end of file
> +diff --git a/libc/sysdeps/linux/riscv64/bits/wordsize.h b/libc/sysdeps/linux/riscv64/bits/wordsize.h
> +index 67a16ba62..1fc649aad 100644
> +--- a/libc/sysdeps/linux/riscv64/bits/wordsize.h
> ++++ b/libc/sysdeps/linux/riscv64/bits/wordsize.h
> +@@ -25,5 +25,6 @@
> + #if __riscv_xlen == 64
> + # define __WORDSIZE_TIME64_COMPAT32 1
> + #else
> +-# error "rv32i-based targets are not supported"
> ++# define __WORDSIZE_TIME64_COMPAT32 1
> ++// # warning "rv32i-based targets are experimental"
> + #endif
> +diff --git a/libc/sysdeps/linux/riscv64/sys/asm.h b/libc/sysdeps/linux/riscv64/sys/asm.h
> +index ddb84b683..3c94c9a70 100644
> +--- a/libc/sysdeps/linux/riscv64/sys/asm.h
> ++++ b/libc/sysdeps/linux/riscv64/sys/asm.h
> +@@ -26,7 +26,11 @@
> + # define REG_S sd
> + # define REG_L ld
> + #elif __riscv_xlen == 32
> +-# error "rv32i-based targets are not supported"
> ++# define PTRLOG 2
> ++# define SZREG 4
> ++# define REG_S sw
> ++# define REG_L lw
> ++// # warning "rv32i-based targets are experimental"
> + #else
> + # error __riscv_xlen must equal 32 or 64
> + #endif
> +--
> +2.37.1
> +
> diff --git a/package/uclibc/Config.in b/package/uclibc/Config.in
> index 2555487f06..a1e9305ca0 100644
> --- a/package/uclibc/Config.in
> +++ b/package/uclibc/Config.in
> @@ -17,6 +17,7 @@ config BR2_PACKAGE_UCLIBC_ARCH_SUPPORTS
> default y if BR2_powerpc
> # see libc/sysdeps/linux/riscv64/sys/asm.h
> default y if BR2_RISCV_64 && (BR2_RISCV_ABI_LP64 || BR2_RISCV_ABI_LP64D)
> + default y if BR2_RISCV_32
> default y if BR2_sh4
> default y if BR2_sh4eb
> default y if BR2_sparc
> @@ -138,6 +139,7 @@ config BR2_UCLIBC_TARGET_ARCH
> default "i386" if BR2_i386
> default "x86_64" if BR2_x86_64
> default "riscv64" if BR2_RISCV_64
> + default "riscv32" if BR2_RISCV_32
>
> config BR2_UCLIBC_MIPS_ABI
> string
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [Buildroot] [PATCH v2 3/4] arch: Enable support for RISC-V 32-bit NOMMU
2022-12-17 5:13 [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
2022-12-17 5:13 ` [Buildroot] [PATCH v2 1/4] package/elf2flt: add RISC-V 32-bits support Jesse Taube
2022-12-17 5:13 ` [Buildroot] [PATCH v2 2/4] package/uclibc: Add RISC-V 32-bit support Jesse Taube
@ 2022-12-17 5:13 ` Jesse Taube
2022-12-17 5:13 ` [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig Jesse Taube
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Jesse Taube @ 2022-12-17 5:13 UTC (permalink / raw)
To: buildroot
Cc: Mark Corbin, Jesse Taube, Thomas Petazzoni, Romain Naour,
Charles Lohr, Yimin Gu, Giulio Benetti
From: Yimin Gu <ustcymgu@gmail.com>
Allow RV32 to select to be built as a NOMMU architecture.
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
Cc: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
arch/Config.in.riscv | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index b5e84389e0..c79cf9b410 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -71,7 +71,6 @@ choice
config BR2_RISCV_32
bool "32-bit"
- select BR2_USE_MMU
config BR2_RISCV_64
bool "64-bit"
@@ -82,7 +81,6 @@ endchoice
config BR2_RISCV_USE_MMU
bool "MMU support"
default y
- depends on BR2_RISCV_64
select BR2_USE_MMU
help
Enable this option if your RISC-V core has a MMU (Memory
--
2.39.0
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig
2022-12-17 5:13 [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
` (2 preceding siblings ...)
2022-12-17 5:13 ` [Buildroot] [PATCH v2 3/4] arch: Enable support for RISC-V 32-bit NOMMU Jesse Taube
@ 2022-12-17 5:13 ` Jesse Taube
2023-10-01 7:15 ` Romain Naour
2023-01-08 19:40 ` [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
2023-02-12 20:59 ` Jesse Taube
5 siblings, 1 reply; 12+ messages in thread
From: Jesse Taube @ 2022-12-17 5:13 UTC (permalink / raw)
To: buildroot
Cc: Mark Corbin, Jesse Taube, Thomas Petazzoni, Romain Naour,
Charles Lohr, Yimin Gu, Giulio Benetti
Add RISC-V 32-bit nommu defconfig for QEMU virt machine with MMU
disabled.
Unlike qemu_riscv32_virt, qemu_riscv32_nommu_virt does not use OpenSBI,
since the kernel is running in machine mode (M-mode).
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Cc: Yimin Gu <ustcymgu@gmail.com>
---
board/qemu/riscv32-virt/nommu/defconfig | 16 +++++++
| 1 +
...nfig-Allow-RV32-to-build-with-no-MMU.patch | 43 +++++++++++++++++++
...le-stat64-and-time32-for-RV32-uclibc.patch | 40 +++++++++++++++++
board/qemu/riscv32-virt/readme.txt | 6 ++-
configs/qemu_riscv32_nommu_virt_defconfig | 31 +++++++++++++
6 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 board/qemu/riscv32-virt/nommu/defconfig
create mode 120000 board/qemu/riscv32-virt/nommu/patches/linux-headers
create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
diff --git a/board/qemu/riscv32-virt/nommu/defconfig b/board/qemu/riscv32-virt/nommu/defconfig
new file mode 100644
index 0000000000..460907253a
--- /dev/null
+++ b/board/qemu/riscv32-virt/nommu/defconfig
@@ -0,0 +1,16 @@
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_MMU is not set
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_SOC_VIRT=y
+CONFIG_NONPORTABLE=y
+CONFIG_ARCH_RV32I=y
+CONFIG_BINFMT_FLAT=y
+CONFIG_SLOB=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_EXT2_FS=y
+CONFIG_PRINTK_TIME=y
--git a/board/qemu/riscv32-virt/nommu/patches/linux-headers b/board/qemu/riscv32-virt/nommu/patches/linux-headers
new file mode 120000
index 0000000000..ce5e2c77b2
--- /dev/null
+++ b/board/qemu/riscv32-virt/nommu/patches/linux-headers
@@ -0,0 +1 @@
+linux/
\ No newline at end of file
diff --git a/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
new file mode 100644
index 0000000000..af11ddf953
--- /dev/null
+++ b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
@@ -0,0 +1,43 @@
+From 57800c87e422375ec0df4d5ad7f33659f7b60093 Mon Sep 17 00:00:00 2001
+From: Yimin Gu <ustcymgu@gmail.com>
+Date: Sat, 10 Dec 2022 22:27:47 -0500
+Subject: [PATCH] riscv: Kconfig: Allow RV32 to build with no MMU
+
+Some RISC-V 32bit ores do not have an MMU, and the kernel should be
+able to build for them. This patch enables the RV32 to be built with
+no MMU support.
+
+Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
+CC=c: Jesse Taube <Mr.Bossman075@gmail.com>
+Tested-By: Waldemar Brodkorb <wbx@openadk.org>
+Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
+---
+ arch/riscv/Kconfig | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
+index 59d18881f35b..49759dbe6a8f 100644
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -163,8 +163,8 @@ config MMU
+
+ config PAGE_OFFSET
+ hex
+- default 0xC0000000 if 32BIT
+- default 0x80000000 if 64BIT && !MMU
++ default 0xC0000000 if 32BIT && MMU
++ default 0x80000000 if !MMU
+ default 0xff60000000000000 if 64BIT
+
+ config KASAN_SHADOW_OFFSET
+@@ -262,7 +262,6 @@ config ARCH_RV32I
+ select GENERIC_LIB_ASHRDI3
+ select GENERIC_LIB_LSHRDI3
+ select GENERIC_LIB_UCMPDI2
+- select MMU
+
+ config ARCH_RV64I
+ bool "RV64I"
+--
+2.38.1
+
diff --git a/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
new file mode 100644
index 0000000000..f654cca7a6
--- /dev/null
+++ b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
@@ -0,0 +1,40 @@
+From 1d985b3cd0fdb37567b4b8263cae740b49a1f46a Mon Sep 17 00:00:00 2001
+From: Yimin Gu <ustcymgu@gmail.com>
+Date: Sat, 10 Dec 2022 22:31:06 -0500
+Subject: [PATCH] riscv: Enable stat64 and time32 for RV32 uclibc
+
+To comply with current uclibc, macros __ARCH_WANT_STAT64 and
+__ARCH_WANT_TIME32_SYSCALLS are defined. CONFIG_COMPAT_32BIT_TIME also
+has to be turned on.
+
+Tested-By: Waldemar Brodkorb <wbx@openadk.org>
+Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
+Cc: Jesse Taube <Mr.Bossman075@gmail.com>
+Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
+---
+ arch/riscv/include/uapi/asm/unistd.h | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h
+index 73d7cdd2ec49..3dc774bc201f 100644
+--- a/arch/riscv/include/uapi/asm/unistd.h
++++ b/arch/riscv/include/uapi/asm/unistd.h
+@@ -15,9 +15,14 @@
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+-#if defined(__LP64__) && !defined(__SYSCALL_COMPAT)
++#ifndef __SYSCALL_COMPAT
+ #define __ARCH_WANT_NEW_STAT
+ #define __ARCH_WANT_SET_GET_RLIMIT
++#endif /* __SYSCALL_COMPAT */
++
++#ifndef __LP64__
++#define __ARCH_WANT_STAT64
++#define __ARCH_WANT_TIME32_SYSCALLS
+ #endif /* __LP64__ */
+
+ #define __ARCH_WANT_SYS_CLONE3
+--
+2.38.1
+
diff --git a/board/qemu/riscv32-virt/readme.txt b/board/qemu/riscv32-virt/readme.txt
index 32b4333512..067bb9f436 100644
--- a/board/qemu/riscv32-virt/readme.txt
+++ b/board/qemu/riscv32-virt/readme.txt
@@ -1,5 +1,9 @@
Run Linux in emulation with:
- qemu-system-riscv32 -M virt -bios output/images/fw_jump.elf -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic # qemu_riscv32_virt_defconfig
+qemu_riscv32_virt_defconfig:
+ qemu-system-riscv32 -M virt -bios output/images/fw_jump.elf -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic
+
+qemu_riscv32_nommu_virt_defconfig:
+ qemu-system-riscv32 -M virt -bios none -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -nographic -cpu rv32,mmu=off
The login prompt will appear in the terminal that started Qemu.
diff --git a/configs/qemu_riscv32_nommu_virt_defconfig b/configs/qemu_riscv32_nommu_virt_defconfig
new file mode 100644
index 0000000000..8bfa1f7435
--- /dev/null
+++ b/configs/qemu_riscv32_nommu_virt_defconfig
@@ -0,0 +1,31 @@
+# Architecture
+BR2_riscv=y
+BR2_RISCV_32=y
+# BR2_RISCV_USE_MMU is not set
+
+# System
+BR2_TARGET_GENERIC_GETTY=y
+BR2_PTHREADS_NONE=y
+
+# Filesystem
+BR2_TARGET_ROOTFS_EXT2=y
+
+# Image
+BR2_ROOTFS_POST_IMAGE_SCRIPT="board/qemu/post-image.sh"
+BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_DEFCONFIG)"
+
+# Linux headers same as kernel
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_0=y
+
+# Kernel
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.0"
+BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
+BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/qemu/riscv32-virt/nommu/defconfig"
+BR2_LINUX_KERNEL_IMAGE=y
+BR2_GLOBAL_PATCH_DIR="board/qemu/riscv32-virt/nommu/patches"
+
+# host-qemu for gitlab testing
+BR2_PACKAGE_HOST_QEMU=y
+BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y
--
2.39.0
_______________________________________________
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https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig
2022-12-17 5:13 ` [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig Jesse Taube
@ 2023-10-01 7:15 ` Romain Naour
2023-10-01 11:39 ` Waldemar Brodkorb
0 siblings, 1 reply; 12+ messages in thread
From: Romain Naour @ 2023-10-01 7:15 UTC (permalink / raw)
To: Jesse Taube, buildroot
Cc: Mark Corbin, Thomas Petazzoni, Romain Naour, Charles Lohr,
Yimin Gu, Giulio Benetti
Hello,
Le 17/12/2022 à 06:13, Jesse Taube a écrit :
> Add RISC-V 32-bit nommu defconfig for QEMU virt machine with MMU
> disabled.
>
> Unlike qemu_riscv32_virt, qemu_riscv32_nommu_virt does not use OpenSBI,
> since the kernel is running in machine mode (M-mode).
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> Cc: Yimin Gu <ustcymgu@gmail.com>
I rebased the elf2flt patch for risc32 [1] on top of elf2flt 2023.09 release,
then I enabled the risc32 uclibc-ng support [2] without patching it since we use
the latest release (v1.0.44) containing this commit [3].
But the system doesn't boot due to a reloc issue:
binfmt_flat: reloc outside program 0xfff7b6dc (0 - 0x9cec0/0x8a180), killing sh!
Starting init: /bin/sh exists but couldn't execute it (error -8)
This issue may be related to the toolchain used to build this defconfig (gcc
12.3.0 and binutils 2.40) that is newer than the toolchain used at the time this
series was tested.
[1]
http://patchwork.ozlabs.org/project/buildroot/patch/20221217051337.3778405-2-Mr.Bossman075@gmail.com/
[2]
http://patchwork.ozlabs.org/project/buildroot/patch/20221217051337.3778405-3-Mr.Bossman075@gmail.com/
[3]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/commit/?id=0a5466d8d53bc8045ff56ff76cc1880aa85761c2
> ---
> board/qemu/riscv32-virt/nommu/defconfig | 16 +++++++
> .../riscv32-virt/nommu/patches/linux-headers | 1 +
> ...nfig-Allow-RV32-to-build-with-no-MMU.patch | 43 +++++++++++++++++++
> ...le-stat64-and-time32-for-RV32-uclibc.patch | 40 +++++++++++++++++
> board/qemu/riscv32-virt/readme.txt | 6 ++-
> configs/qemu_riscv32_nommu_virt_defconfig | 31 +++++++++++++
> 6 files changed, 136 insertions(+), 1 deletion(-)
> create mode 100644 board/qemu/riscv32-virt/nommu/defconfig
> create mode 120000 board/qemu/riscv32-virt/nommu/patches/linux-headers
> create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
> create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
> create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
>
> diff --git a/board/qemu/riscv32-virt/nommu/defconfig b/board/qemu/riscv32-virt/nommu/defconfig
> new file mode 100644
> index 0000000000..460907253a
> --- /dev/null
> +++ b/board/qemu/riscv32-virt/nommu/defconfig
> @@ -0,0 +1,16 @@
> +CONFIG_BLK_DEV_INITRD=y
> +# CONFIG_MMU is not set
> +CONFIG_COMPAT_32BIT_TIME=y
> +CONFIG_SOC_VIRT=y
> +CONFIG_NONPORTABLE=y
> +CONFIG_ARCH_RV32I=y
> +CONFIG_BINFMT_FLAT=y
> +CONFIG_SLOB=y
> +CONFIG_VIRTIO_BLK=y
> +CONFIG_SERIAL_8250=y
> +CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_VIRTIO_MMIO=y
> +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
> +CONFIG_EXT2_FS=y
> +CONFIG_PRINTK_TIME=y
> diff --git a/board/qemu/riscv32-virt/nommu/patches/linux-headers b/board/qemu/riscv32-virt/nommu/patches/linux-headers
> new file mode 120000
> index 0000000000..ce5e2c77b2
> --- /dev/null
> +++ b/board/qemu/riscv32-virt/nommu/patches/linux-headers
> @@ -0,0 +1 @@
> +linux/
> \ No newline at end of file
> diff --git a/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
> new file mode 100644
> index 0000000000..af11ddf953
> --- /dev/null
> +++ b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
> @@ -0,0 +1,43 @@
> +From 57800c87e422375ec0df4d5ad7f33659f7b60093 Mon Sep 17 00:00:00 2001
> +From: Yimin Gu <ustcymgu@gmail.com>
> +Date: Sat, 10 Dec 2022 22:27:47 -0500
> +Subject: [PATCH] riscv: Kconfig: Allow RV32 to build with no MMU
> +
> +Some RISC-V 32bit ores do not have an MMU, and the kernel should be
> +able to build for them. This patch enables the RV32 to be built with
> +no MMU support.
> +
> +Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
> +CC=c: Jesse Taube <Mr.Bossman075@gmail.com>
> +Tested-By: Waldemar Brodkorb <wbx@openadk.org>
> +Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> +---
> + arch/riscv/Kconfig | 5 ++---
> + 1 file changed, 2 insertions(+), 3 deletions(-)
> +
> +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> +index 59d18881f35b..49759dbe6a8f 100644
> +--- a/arch/riscv/Kconfig
> ++++ b/arch/riscv/Kconfig
> +@@ -163,8 +163,8 @@ config MMU
> +
> + config PAGE_OFFSET
> + hex
> +- default 0xC0000000 if 32BIT
> +- default 0x80000000 if 64BIT && !MMU
> ++ default 0xC0000000 if 32BIT && MMU
> ++ default 0x80000000 if !MMU
> + default 0xff60000000000000 if 64BIT
> +
> + config KASAN_SHADOW_OFFSET
> +@@ -262,7 +262,6 @@ config ARCH_RV32I
> + select GENERIC_LIB_ASHRDI3
> + select GENERIC_LIB_LSHRDI3
> + select GENERIC_LIB_UCMPDI2
> +- select MMU
> +
> + config ARCH_RV64I
> + bool "RV64I"
> +--
> +2.38.1
> +
> diff --git a/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
> new file mode 100644
> index 0000000000..f654cca7a6
> --- /dev/null
> +++ b/board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
> @@ -0,0 +1,40 @@
> +From 1d985b3cd0fdb37567b4b8263cae740b49a1f46a Mon Sep 17 00:00:00 2001
> +From: Yimin Gu <ustcymgu@gmail.com>
> +Date: Sat, 10 Dec 2022 22:31:06 -0500
> +Subject: [PATCH] riscv: Enable stat64 and time32 for RV32 uclibc
> +
> +To comply with current uclibc, macros __ARCH_WANT_STAT64 and
> +__ARCH_WANT_TIME32_SYSCALLS are defined. CONFIG_COMPAT_32BIT_TIME also
> +has to be turned on.
It would be great if this patch could be upstreamed since we have to patch not
only the kernel running at runtime but also the kernel headers used by the
toolchain.
> +
> +Tested-By: Waldemar Brodkorb <wbx@openadk.org>
> +Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
> +Cc: Jesse Taube <Mr.Bossman075@gmail.com>
> +Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> +---
> + arch/riscv/include/uapi/asm/unistd.h | 7 ++++++-
> + 1 file changed, 6 insertions(+), 1 deletion(-)
> +
> +diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h
> +index 73d7cdd2ec49..3dc774bc201f 100644
> +--- a/arch/riscv/include/uapi/asm/unistd.h
> ++++ b/arch/riscv/include/uapi/asm/unistd.h
> +@@ -15,9 +15,14 @@
> + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> + */
> +
> +-#if defined(__LP64__) && !defined(__SYSCALL_COMPAT)
> ++#ifndef __SYSCALL_COMPAT
> + #define __ARCH_WANT_NEW_STAT
> + #define __ARCH_WANT_SET_GET_RLIMIT
> ++#endif /* __SYSCALL_COMPAT */
> ++
> ++#ifndef __LP64__
> ++#define __ARCH_WANT_STAT64
> ++#define __ARCH_WANT_TIME32_SYSCALLS
> + #endif /* __LP64__ */
> +
> + #define __ARCH_WANT_SYS_CLONE3
> +--
> +2.38.1
> +
> diff --git a/board/qemu/riscv32-virt/readme.txt b/board/qemu/riscv32-virt/readme.txt
> index 32b4333512..067bb9f436 100644
> --- a/board/qemu/riscv32-virt/readme.txt
> +++ b/board/qemu/riscv32-virt/readme.txt
> @@ -1,5 +1,9 @@
> Run Linux in emulation with:
>
> - qemu-system-riscv32 -M virt -bios output/images/fw_jump.elf -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic # qemu_riscv32_virt_defconfig
> +qemu_riscv32_virt_defconfig:
> + qemu-system-riscv32 -M virt -bios output/images/fw_jump.elf -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic
Please, don't modify "# qemu_riscv32_virt_defconfig" here, it used by the script
that generate the start-qemu.sh script.
> +
> +qemu_riscv32_nommu_virt_defconfig:
remove "qemu_riscv32_nommu_virt_defconfig:"
> + qemu-system-riscv32 -M virt -bios none -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -nographic -cpu rv32,mmu=off
add "# qemu_riscv32_nommu_virt_defconfig" at the end of this line.
Can you have a look and resend an updated version of this series?
Best regards,
Romain
>
> The login prompt will appear in the terminal that started Qemu.
> diff --git a/configs/qemu_riscv32_nommu_virt_defconfig b/configs/qemu_riscv32_nommu_virt_defconfig
> new file mode 100644
> index 0000000000..8bfa1f7435
> --- /dev/null
> +++ b/configs/qemu_riscv32_nommu_virt_defconfig
> @@ -0,0 +1,31 @@
> +# Architecture
> +BR2_riscv=y
> +BR2_RISCV_32=y
> +# BR2_RISCV_USE_MMU is not set
> +
> +# System
> +BR2_TARGET_GENERIC_GETTY=y
> +BR2_PTHREADS_NONE=y
> +
> +# Filesystem
> +BR2_TARGET_ROOTFS_EXT2=y
> +
> +# Image
> +BR2_ROOTFS_POST_IMAGE_SCRIPT="board/qemu/post-image.sh"
> +BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_DEFCONFIG)"
> +
> +# Linux headers same as kernel
> +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_0=y
> +
> +# Kernel
> +BR2_LINUX_KERNEL=y
> +BR2_LINUX_KERNEL_CUSTOM_VERSION=y
> +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.0"
> +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
> +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/qemu/riscv32-virt/nommu/defconfig"
> +BR2_LINUX_KERNEL_IMAGE=y
> +BR2_GLOBAL_PATCH_DIR="board/qemu/riscv32-virt/nommu/patches"
> +
> +# host-qemu for gitlab testing
> +BR2_PACKAGE_HOST_QEMU=y
> +BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig
2023-10-01 7:15 ` Romain Naour
@ 2023-10-01 11:39 ` Waldemar Brodkorb
2023-10-01 12:02 ` Romain Naour
0 siblings, 1 reply; 12+ messages in thread
From: Waldemar Brodkorb @ 2023-10-01 11:39 UTC (permalink / raw)
To: Romain Naour
Cc: Mark Corbin, Jesse Taube, Thomas Petazzoni, buildroot,
Romain Naour, Charles Lohr, Yimin Gu, Giulio Benetti
Hi Romain,
Romain Naour wrote,
> Hello,
>
> Le 17/12/2022 à 06:13, Jesse Taube a écrit :
> > Add RISC-V 32-bit nommu defconfig for QEMU virt machine with MMU
> > disabled.
> >
> > Unlike qemu_riscv32_virt, qemu_riscv32_nommu_virt does not use OpenSBI,
> > since the kernel is running in machine mode (M-mode).
> >
> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> > Cc: Yimin Gu <ustcymgu@gmail.com>
>
> I rebased the elf2flt patch for risc32 [1] on top of elf2flt 2023.09 release,
> then I enabled the risc32 uclibc-ng support [2] without patching it since we use
> the latest release (v1.0.44) containing this commit [3].
>
> But the system doesn't boot due to a reloc issue:
>
> binfmt_flat: reloc outside program 0xfff7b6dc (0 - 0x9cec0/0x8a180), killing sh!
> Starting init: /bin/sh exists but couldn't execute it (error -8)
>
> This issue may be related to the toolchain used to build this defconfig (gcc
> 12.3.0 and binutils 2.40) that is newer than the toolchain used at the time this
> series was tested.
Can you share your elf2flt patch, please.
best regards
Waldemar
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig
2023-10-01 11:39 ` Waldemar Brodkorb
@ 2023-10-01 12:02 ` Romain Naour
2023-10-01 14:09 ` Waldemar Brodkorb
0 siblings, 1 reply; 12+ messages in thread
From: Romain Naour @ 2023-10-01 12:02 UTC (permalink / raw)
To: Waldemar Brodkorb
Cc: Mark Corbin, Jesse Taube, Thomas Petazzoni, buildroot,
Romain Naour, Charles Lohr, Yimin Gu, Giulio Benetti
[-- Attachment #1: Type: text/plain, Size: 1444 bytes --]
Hi Waldemar,
Le 01/10/2023 à 13:39, Waldemar Brodkorb a écrit :
> Hi Romain,
>
> Romain Naour wrote,
>
>> Hello,
>>
>> Le 17/12/2022 à 06:13, Jesse Taube a écrit :
>>> Add RISC-V 32-bit nommu defconfig for QEMU virt machine with MMU
>>> disabled.
>>>
>>> Unlike qemu_riscv32_virt, qemu_riscv32_nommu_virt does not use OpenSBI,
>>> since the kernel is running in machine mode (M-mode).
>>>
>>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>>> Cc: Yimin Gu <ustcymgu@gmail.com>
>>
>> I rebased the elf2flt patch for risc32 [1] on top of elf2flt 2023.09 release,
>> then I enabled the risc32 uclibc-ng support [2] without patching it since we use
>> the latest release (v1.0.44) containing this commit [3].
>>
>> But the system doesn't boot due to a reloc issue:
>>
>> binfmt_flat: reloc outside program 0xfff7b6dc (0 - 0x9cec0/0x8a180), killing sh!
>> Starting init: /bin/sh exists but couldn't execute it (error -8)
>>
>> This issue may be related to the toolchain used to build this defconfig (gcc
>> 12.3.0 and binutils 2.40) that is newer than the toolchain used at the time this
>> series was tested.
>
> Can you share your elf2flt patch, please.
Sure, It the initial patch from Jesse Taube but without the relocation part that
was part of riscv64 commit:
https://github.com/uclinux-dev/elf2flt/commit/c5c8043c4d79a1cdd9bd359a542e6fdf3b04d5a1
I hope this can help.
Best regards,
Romain
>
> best regards
> Waldemar
[-- Attachment #2: 0001-Added-RISC-V-32-bit-support.patch --]
[-- Type: text/x-patch, Size: 1843 bytes --]
From ae74a9f9b2282ec90d0eb1b7358c2e0ed474a4ef Mon Sep 17 00:00:00 2001
From: Yimin Gu <ustcymgu@gmail.com>
Date: Wed, 14 Dec 2022 06:49:46 -0500
Subject: [PATCH] Added RISC-V 32-bit support
Allow elf2flt to work with RISC-V 32-bit targets. With these changes, the
uclibc toolchain and busybox can work fine for rv32 no MMU systems with
no noticable problem.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Add more ELF relco types and edit commit message]
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
[Romain: rebase on 2023.09]
Signed-off-by: Romain Naour <romain.naour@smile.fr>
---
elf2flt.c | 4 +++-
ld-elf2flt.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/elf2flt.c b/elf2flt.c
index f37cfa2..d46c328 100644
--- a/elf2flt.c
+++ b/elf2flt.c
@@ -81,7 +81,7 @@ const char *elf2flt_progname;
#include <elf/v850.h>
#elif defined(TARGET_xtensa)
#include <elf/xtensa.h>
-#elif defined(TARGET_riscv64)
+#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
#include <elf/riscv.h>
#endif
@@ -127,6 +127,8 @@ const char *elf2flt_progname;
#define ARCH "xtensa"
#elif defined(TARGET_riscv64)
#define ARCH "riscv64"
+#elif defined(TARGET_riscv32)
+#define ARCH "riscv32"
#else
#error "Don't know how to support your CPU architecture??"
#endif
diff --git a/ld-elf2flt.c b/ld-elf2flt.c
index 75ee1bb..68b2a4a 100644
--- a/ld-elf2flt.c
+++ b/ld-elf2flt.c
@@ -327,7 +327,7 @@ static int do_final_link(void)
/* riscv adds a global pointer symbol to the linker file with the
"RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
the entire line for other architectures. */
- if (streq(TARGET_CPU, "riscv64"))
+ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
append_sed(&sed, "^RISCV_GP:", "");
else
append_sed(&sed, "^RISCV_GP:", NULL);
--
2.41.0
[-- Attachment #3: Type: text/plain, Size: 150 bytes --]
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig
2023-10-01 12:02 ` Romain Naour
@ 2023-10-01 14:09 ` Waldemar Brodkorb
0 siblings, 0 replies; 12+ messages in thread
From: Waldemar Brodkorb @ 2023-10-01 14:09 UTC (permalink / raw)
To: Romain Naour
Cc: Mark Corbin, Jesse Taube, Thomas Petazzoni, buildroot,
Romain Naour, Charles Lohr, Yimin Gu, Giulio Benetti
[-- Attachment #1: Type: text/plain, Size: 1601 bytes --]
Hi Romain,
Romain Naour wrote,
> Hi Waldemar,
>
> Le 01/10/2023 à 13:39, Waldemar Brodkorb a écrit :
> > Hi Romain,
> >
> > Romain Naour wrote,
> >
> >> Hello,
> >>
> >> Le 17/12/2022 à 06:13, Jesse Taube a écrit :
> >>> Add RISC-V 32-bit nommu defconfig for QEMU virt machine with MMU
> >>> disabled.
> >>>
> >>> Unlike qemu_riscv32_virt, qemu_riscv32_nommu_virt does not use OpenSBI,
> >>> since the kernel is running in machine mode (M-mode).
> >>>
> >>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> >>> Cc: Yimin Gu <ustcymgu@gmail.com>
> >>
> >> I rebased the elf2flt patch for risc32 [1] on top of elf2flt 2023.09 release,
> >> then I enabled the risc32 uclibc-ng support [2] without patching it since we use
> >> the latest release (v1.0.44) containing this commit [3].
> >>
> >> But the system doesn't boot due to a reloc issue:
> >>
> >> binfmt_flat: reloc outside program 0xfff7b6dc (0 - 0x9cec0/0x8a180), killing sh!
> >> Starting init: /bin/sh exists but couldn't execute it (error -8)
> >>
> >> This issue may be related to the toolchain used to build this defconfig (gcc
> >> 12.3.0 and binutils 2.40) that is newer than the toolchain used at the time this
> >> series was tested.
> >
> > Can you share your elf2flt patch, please.
>
> Sure, It the initial patch from Jesse Taube but without the relocation part that
> was part of riscv64 commit:
>
> https://github.com/uclinux-dev/elf2flt/commit/c5c8043c4d79a1cdd9bd359a542e6fdf3b04d5a1
>
> I hope this can help.
See attached patch I am using, there is one change missing in your
patch.
best regards
Waldemar
[-- Attachment #2: 0001-riscv32.patch --]
[-- Type: text/x-diff, Size: 1555 bytes --]
diff -Nur elf2flt-v2023.04.orig/elf2flt.c elf2flt-v2023.04/elf2flt.c
--- elf2flt-v2023.04.orig/elf2flt.c 2023-09-04 11:29:05.952417209 +0200
+++ elf2flt-v2023.04/elf2flt.c 2023-09-04 11:30:05.371065966 +0200
@@ -81,7 +81,7 @@
#include <elf/v850.h>
#elif defined(TARGET_xtensa)
#include <elf/xtensa.h>
-#elif defined(TARGET_riscv64)
+#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
#include <elf/riscv.h>
#endif
@@ -127,6 +127,8 @@
#define ARCH "xtensa"
#elif defined(TARGET_riscv64)
#define ARCH "riscv64"
+#elif defined(TARGET_riscv32)
+#define ARCH "riscv32"
#else
#error "Don't know how to support your CPU architecture??"
#endif
@@ -822,7 +824,7 @@
goto good_32bit_resolved_reloc_update_text;
default:
goto bad_resolved_reloc;
-#elif defined(TARGET_riscv64)
+#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
case R_RISCV_NONE:
case R_RISCV_32_PCREL:
case R_RISCV_ADD8:
diff -Nur elf2flt-v2023.04.orig/ld-elf2flt.c elf2flt-v2023.04/ld-elf2flt.c
--- elf2flt-v2023.04.orig/ld-elf2flt.c 2023-09-04 11:28:59.072573514 +0200
+++ elf2flt-v2023.04/ld-elf2flt.c 2023-09-04 11:29:32.507813592 +0200
@@ -327,7 +327,7 @@
/* riscv adds a global pointer symbol to the linker file with the
"RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
the entire line for other architectures. */
- if (streq(TARGET_CPU, "riscv64"))
+ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
append_sed(&sed, "^RISCV_GP:", "");
else
append_sed(&sed, "^RISCV_GP:", NULL);
[-- Attachment #3: Type: text/plain, Size: 150 bytes --]
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support
2022-12-17 5:13 [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
` (3 preceding siblings ...)
2022-12-17 5:13 ` [Buildroot] [PATCH v2 4/4] configs/qemu_riscv32_nommu_virt_defconfig: New defconfig Jesse Taube
@ 2023-01-08 19:40 ` Jesse Taube
2023-02-12 20:59 ` Jesse Taube
5 siblings, 0 replies; 12+ messages in thread
From: Jesse Taube @ 2023-01-08 19:40 UTC (permalink / raw)
To: buildroot
Cc: Mark Corbin, jacmet, Thomas Petazzoni, Romain Naour, Charles Lohr,
Yimin Gu, Giulio Benetti
Hi,
Peter Korsgaard would you be willing to review this set?
Thanks,
Jesse
On 12/17/22 00:13, Jesse Taube wrote:
> This patch-set aims to add NOMMU support to RV32.
> Many people want to build simple emulators or HDL
> models of RISC-V this patch makes it posible to
> run linux on them.
>
> Yimin Gu is the original author of this set.
> Submitted here:
> https://lists.buildroot.org/pipermail/buildroot/2022-November/656134.html
>
> Though Jesse T made the configs more concise.
> Aswell fixed the 1k line Dconf,
> and split into 3 distinct patches.
>
> A couple things to note:
> - UcLibc seems to want __ARCH_WANT_TIME32_SYSCALLS
> for adjtimex, but Linux doesnt provide this for RV32.
> - Patch 2 adds __ARCH_WANT_STAT64,
> but I'm not sure if this is needed.
> - Busybox doesnt build umask or unset for NOMMU systems.
> I have seen this happen on STM32 aswell as I.MXRT
>
> [__ARCH_WANT_TIME32_SYSCALLS]:
> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20190218210712.3503891-5-arnd@arndb.de/
>
> Jesse Taube (1):
> configs/qemu_riscv32_nommu_virt_defconfig: New defconfig
>
> Yimin Gu (3):
> package/elf2flt: add RISC-V 32-bits support
> package/uclibc: Add RISC-V 32-bit support
> arch: Enable support for RISC-V 32-bit NOMMU
>
> arch/Config.in.riscv | 2 -
> board/qemu/riscv32-virt/nommu/defconfig | 16 ++
> .../riscv32-virt/nommu/patches/linux-headers | 1 +
> ...nfig-Allow-RV32-to-build-with-no-MMU.patch | 43 ++++++
> ...le-stat64-and-time32-for-RV32-uclibc.patch | 40 +++++
> board/qemu/riscv32-virt/readme.txt | 6 +-
> configs/qemu_riscv32_nommu_virt_defconfig | 31 ++++
> package/Makefile.in | 4 +-
> .../0007-Added-RISC-V-32-bit-support.patch | 87 +++++++++++
> .../uclibc/0001-RISC-V-32-bit-support.patch | 145 ++++++++++++++++++
> package/uclibc/Config.in | 2 +
> 11 files changed, 372 insertions(+), 5 deletions(-)
> create mode 100644 board/qemu/riscv32-virt/nommu/defconfig
> create mode 120000 board/qemu/riscv32-virt/nommu/patches/linux-headers
> create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
> create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
> create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
> create mode 100644 package/elf2flt/0007-Added-RISC-V-32-bit-support.patch
> create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch
>
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support
2022-12-17 5:13 [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
` (4 preceding siblings ...)
2023-01-08 19:40 ` [Buildroot] [PATCH v2 0/4] Add RISC-V 32 NOMMU support Jesse Taube
@ 2023-02-12 20:59 ` Jesse Taube
5 siblings, 0 replies; 12+ messages in thread
From: Jesse Taube @ 2023-02-12 20:59 UTC (permalink / raw)
To: buildroot
Cc: Mark Corbin, Thomas Petazzoni, Romain Naour, Charles Lohr,
Yimin Gu, Giulio Benetti
Any updates on this set?
On 12/17/22 00:13, Jesse Taube wrote:
> This patch-set aims to add NOMMU support to RV32.
> Many people want to build simple emulators or HDL
> models of RISC-V this patch makes it posible to
> run linux on them.
>
> Yimin Gu is the original author of this set.
> Submitted here:
> https://lists.buildroot.org/pipermail/buildroot/2022-November/656134.html
>
> Though Jesse T made the configs more concise.
> Aswell fixed the 1k line Dconf,
> and split into 3 distinct patches.
>
> A couple things to note:
> - UcLibc seems to want __ARCH_WANT_TIME32_SYSCALLS
> for adjtimex, but Linux doesnt provide this for RV32.
> - Patch 2 adds __ARCH_WANT_STAT64,
> but I'm not sure if this is needed.
> - Busybox doesnt build umask or unset for NOMMU systems.
> I have seen this happen on STM32 aswell as I.MXRT
>
> [__ARCH_WANT_TIME32_SYSCALLS]:
> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20190218210712.3503891-5-arnd@arndb.de/
>
> Jesse Taube (1):
> configs/qemu_riscv32_nommu_virt_defconfig: New defconfig
>
> Yimin Gu (3):
> package/elf2flt: add RISC-V 32-bits support
> package/uclibc: Add RISC-V 32-bit support
> arch: Enable support for RISC-V 32-bit NOMMU
>
> arch/Config.in.riscv | 2 -
> board/qemu/riscv32-virt/nommu/defconfig | 16 ++
> .../riscv32-virt/nommu/patches/linux-headers | 1 +
> ...nfig-Allow-RV32-to-build-with-no-MMU.patch | 43 ++++++
> ...le-stat64-and-time32-for-RV32-uclibc.patch | 40 +++++
> board/qemu/riscv32-virt/readme.txt | 6 +-
> configs/qemu_riscv32_nommu_virt_defconfig | 31 ++++
> package/Makefile.in | 4 +-
> .../0007-Added-RISC-V-32-bit-support.patch | 87 +++++++++++
> .../uclibc/0001-RISC-V-32-bit-support.patch | 145 ++++++++++++++++++
> package/uclibc/Config.in | 2 +
> 11 files changed, 372 insertions(+), 5 deletions(-)
> create mode 100644 board/qemu/riscv32-virt/nommu/defconfig
> create mode 120000 board/qemu/riscv32-virt/nommu/patches/linux-headers
> create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0001-riscv-Kconfig-Allow-RV32-to-build-with-no-MMU.patch
> create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/6.0/0002-riscv-Enable-stat64-and-time32-for-RV32-uclibc.patch
> create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
> create mode 100644 package/elf2flt/0007-Added-RISC-V-32-bit-support.patch
> create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch
>
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