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From: Pavel Machek <pavel@nabladev.com>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>,
	Pavel Machek <pavel@nabladev.com>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 6.12.y-cip 2/8] clk: renesas: r9a09g077: Add xSPI core and module clocks
Date: Thu, 16 Jul 2026 12:48:15 +0200	[thread overview]
Message-ID: <ali274E3aNG2-Rtx@duo.ucw.cz> (raw)
In-Reply-To: <20260706182328.5237-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

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Hi!

Minor details here:

> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> [PL: manually applied the changes]
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -295,6 +334,151 @@ r9a09g077_cpg_mux_clk_register(struct device *dev,
>  	return clk_hw->clk;
>  }
>  
> +static unsigned int r9a09g077_cpg_fselxspi_get_divider(struct clk_hw *hw, unsigned long rate,
> +						       unsigned int num_parents)
> +{
> +	struct clk_fixed_factor *ff;
> +	struct clk_hw *parent_hw;
> +	unsigned long best_rate;
> +	unsigned int i;
> +
> +	for (i = 0; i < num_parents; i++) {
> +		parent_hw = clk_hw_get_parent_by_index(hw, i);
> +		best_rate = clk_hw_round_rate(parent_hw, rate);
> +
> +		if (best_rate == rate) {
> +			ff = to_clk_fixed_factor(parent_hw);
> +			return ff->div;
> +		}
> +	}
> +
> +	/* No parent could provide the exact rate - this should not happen */
> +	return 0;
> +}

If it can't happen, WARN() may be suitable?

> +
> +static struct clk * __init
> +r9a09g077_cpg_fselxspi_div_clk_register(struct device *dev,
> +					const struct cpg_core_clk *core,
> +					void __iomem *addr,
...
> +	if (!xspi_div_ops) {
> +		xspi_div_ops = devm_kzalloc(dev, sizeof(*xspi_div_ops), GFP_KERNEL);
> +		if (!xspi_div_ops)
> +			return  ERR_PTR(-ENOMEM);

One space would be enough between return and ERR.

> +		memcpy(xspi_div_ops, &clk_divider_ops,
> +		       sizeof(const struct clk_ops));

And the memcpy does fit on single line.

(May not be worth cleaning up unless you are doing changes for that anyway).

Thanks and best regards,
										Pavel

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  reply	other threads:[~2026-07-16 10:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06 18:23 [PATCH 6.12.y-cip 0/8] Add xSPI support to RZ/T2H and RZ/N2H SoCs Lad Prabhakar
2026-07-06 18:23 ` [PATCH 6.12.y-cip 1/8] mtd: spi-nor: add support for Macronix Octal flash Lad Prabhakar
2026-07-06 18:23 ` [PATCH 6.12.y-cip 2/8] clk: renesas: r9a09g077: Add xSPI core and module clocks Lad Prabhakar
2026-07-16 10:48   ` Pavel Machek [this message]
2026-07-06 18:23 ` [PATCH 6.12.y-cip 3/8] dt-bindings: memory: renesas,rzg3e-xspi: Add RZ/T2H and RZ/N2H support Lad Prabhakar
2026-07-06 18:23 ` [PATCH 6.12.y-cip 4/8] memory: renesas-rpc-if: Fix duplicate device name on multi-instance platforms Lad Prabhakar
2026-07-06 18:23 ` [PATCH 6.12.y-cip 5/8] memory: renesas-rpc-if: Add suspend/resume support Lad Prabhakar
2026-07-16 10:49   ` Pavel Machek
2026-07-06 18:23 ` [PATCH 6.12.y-cip 6/8] arm64: dts: renesas: r9a09g077: Add xSPI nodes Lad Prabhakar
2026-07-06 18:23 ` [PATCH 6.12.y-cip 7/8] arm64: dts: renesas: r9a09g087: " Lad Prabhakar
2026-07-06 18:23 ` [PATCH 6.12.y-cip 8/8] arm64: dts: renesas: rzt2h-n2h-evk: Enable " Lad Prabhakar
2026-07-16 10:50   ` Pavel Machek
2026-07-16  7:30 ` [PATCH 6.12.y-cip 0/8] Add xSPI support to RZ/T2H and RZ/N2H SoCs nobuhiro.iwamatsu.x90
2026-07-16 10:51   ` [cip-dev] " Pavel Machek

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