Re: [PATCH] transition latency of speedstep-ich (third try)

[Mattia Dongili <malattia@linux.it>]

On Sat, Nov 26, 2005 at 11:40:20PM +0100, Eric Piel wrote:
> 05.10.2005 22:39, Pallipadi, Venkatesh wrote/a écrit:
[...]
> >Do you have ACPI PM timer on your system? May be we can measure the 
> >latency using that. 
> >
> Hello,
> 
> Sorry for the looonnnggg delay of the reply. I've finally found time to 
> hunt for the PM timer on my computer, found it, and kludged 
> speedstep-ich to read it :-) For verification and completeness, the 
> patch is attached. (the PM timer address is hard-coded, it has to be 
> changed before running it on another system, it's indicated at boot in 
> dmesg).
> 
> So the results are quite interesting and confirm your expectations, 
> Venki. After few hours with the ondemand governor, I checked the logs 
> and the transition latency seems very stable: around 735 to 742 PM timer 
> ticks (~206 us). So indeed, 100us of transition latency was quite 
> under-estimating it!

So here's some measurement on my P3M (seems a little faster than yours
in switching):

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 11
model name	: Intel(R) Pentium(R) III Mobile CPU      1000MHz
stepping	: 1
cpu MHz		: 994.394
cache size	: 512 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse
bogomips	: 1991.49


cpufrequtils 0.3: cpufreq-info (C) Dominik Brodowski 2004
Report errors and bugs to linux@brodo.de, please.
analyzing CPU 0:
  driver: speedstep-ich
  CPUs which need to switch frequency at the same time: 0
  hardware limits: 732 MHz - 998 MHz
  available frequency steps: 998 MHz, 732 MHz
  available cpufreq governors: powersave, performance
  current policy: frequency should be within 732 MHz and 998 MHz.
                  The governor "performance" may decide which speed to use
                  within this range.
  current CPU frequency is 998 MHz.

Some stats while switching from the 2 available frequencies while
doing some random compile and/or disk intensive operation:

| min->MAX                      | MAX->min
+---------                      +---------
| 709 PM cicles - occurences 1  | 709 PM cicles - occurences 1
| 710 PM cicles - occurences 1  | 710 PM cicles - occurences 5
| 711 PM cicles - occurences 3  | 711 PM cicles - occurences 2
| 712 PM cicles - occurences 2  | 712 PM cicles - occurences 3
| 713 PM cicles - occurences 9  | 713 PM cicles - occurences 3
| 714 PM cicles - occurences 1  | 714 PM cicles - occurences 3
| 715 PM cicles - occurences 4  | 715 PM cicles - occurences 3
| 716 PM cicles - occurences 5  | 716 PM cicles - occurences 6
| 717 PM cicles - occurences 5  | 717 PM cicles - occurences 6
| 718 PM cicles - occurences 2  | 718 PM cicles - occurences 5
| 719 PM cicles - occurences 6  | 719 PM cicles - occurences 4
| 720 PM cicles - occurences 1  | 720 PM cicles - occurences 2
| 721 PM cicles - occurences 3  | 721 PM cicles - occurences 1
| 722 PM cicles - occurences 4  | 722 PM cicles - occurences 4
| 723 PM cicles - occurences 1  | 723 PM cicles - occurences 2
| 724 PM cicles - occurences 3  | 724 PM cicles - occurences 1

PM cicles weighted average: 716.412
TSC cicles weighted average: 6009.422

(you don't want to see the perl script that generated it) :)

> Now back to the original problem, from those measurements, which time 
> should we put as the maximal transition latency for speedstep-ich? Do 
> you think we can simply put something like 300us and that's it? Maybe we 

I just build speedstep-ich with transition_latency = 250
I'll let you know how it goes. Are you interested?

> could distinguish between PIII and P4 ? It would require someone to 
> rerun the measurement on a P4 hardware. Do we need to take into account 
> as a parameter the CPU frequency?

Maybe it's already been discussed, but how bad would be trying to
measure transition latency at runtime?

-- 
mattia
:wq!