Re: [PATCH] transition latency of speedstep-ich (third try)

[Eric Piel <Eric.Piel@tremplin-utc.net>]

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28.09.2005 03:26, Pallipadi, Venkatesh wrote/a écrit:
> 
> Great work! Getting those useful numbers form those documents :).
> 
> I think the 100uS and 50uS looks proper from what the documents describe. However, there is one factor that we are missing though. Speedstep-ich uses IO ports to initiate these transitions. Right? These IO port accesses trap into BIOS code which actually initiaites the trasntion. And this trap into BIOS code happens through SMM. And whenvever SMM's are involved I have seen latencies of upto 500uS! And in speedstep_ich:speedstep_set_state(), I see more than one in/out instructions. So, it can easily be higher than this.
It's great to know that I've managed to read in between the line of the 
intel documents succesfully ;-)

> 
> I think we need to add a guestimate for SMM latency number as well.
> 
> Eric,
> Can you put rdtsc's around these in/out on your system and check how long do they really take. On P4M, rdtsc should be running all the time other than the Cpu being in deep_sleep state. That should give us some idea about the SMM latency.
> 
Ok, I've just done it. It's on a P3 coppermine though (not a P4M). So 
I've measure the difference of tsc before and after the in/out 
instructions (not included the local_irq_*()). The patch is attached for 
double check (or if someone wants to try on another CPU). The values 
seem very small compare to the 500uS you mentioned.

After few minutes with ondemand governor, there was a log like this:
Sep 28 23:30:32 circle kernel: cpufreq transition took 4862 cycles
Sep 28 23:30:33 circle kernel: cpufreq transition took 4473 cycles
Sep 28 23:30:33 circle kernel: cpufreq transition took 4836 cycles
Sep 28 23:30:35 circle kernel: cpufreq transition took 4723 cycles
Sep 28 23:30:35 circle kernel: cpufreq transition took 5640 cycles
Sep 28 23:30:48 circle kernel: cpufreq transition took 4515 cycles
Sep 28 23:30:48 circle kernel: cpufreq transition took 4904 cycles
Sep 28 23:31:02 circle kernel: cpufreq transition took 4286 cycles
Sep 28 23:31:02 circle kernel: cpufreq transition took 4607 cycles
Sep 28 23:31:03 circle kernel: cpufreq transition took 4279 cycles
Sep 28 23:31:03 circle kernel: cpufreq transition took 4605 cycles
Sep 28 23:31:04 circle kernel: cpufreq transition took 4694 cycles
Sep 28 23:31:04 circle kernel: cpufreq transition took 4605 cycles
Sep 28 23:31:13 circle kernel: cpufreq transition took 4683 cycles
Sep 28 23:31:14 circle kernel: cpufreq transition took 4676 cycles
Sep 28 23:31:14 circle kernel: cpufreq transition took 4515 cycles
Sep 28 23:31:15 circle kernel: cpufreq transition took 4522 cycles

Maximum I've seen is 5640 cycles, minimum is about 4200c. My CPU is 
clocked 1GHz so the result can be easily summarized to a maximum of 
about 6uS.

As it's very different from the numbers you got, I wonder if I mistook 
somewhere ?

Eric

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--- arch/i386/kernel/cpu/cpufreq/speedstep-ich.c-beforetsc	2005-09-28 23:23:49.000000000 +0200
+++ arch/i386/kernel/cpu/cpufreq/speedstep-ich.c	2005-09-28 23:23:18.000000000 +0200
@@ -66,6 +66,7 @@ static void speedstep_set_state (unsigne
 	u8 pm2_blk;
 	u8 value;
 	unsigned long flags;
+	unsigned long long tsc1, tsc2;
 
 	if (!speedstep_chipset_dev || (state > 0x1))
 		return;
@@ -86,6 +87,8 @@ static void speedstep_set_state (unsigne
 	/* Disable IRQs */
 	local_irq_save(flags);
 
+	rdtscll(tsc1);
+	
 	/* read state */
 	value = inb(pmbase + 0x50);
 
@@ -111,6 +114,8 @@ static void speedstep_set_state (unsigne
 
 	/* check if transition was successful */
 	value = inb(pmbase + 0x50);
+	
+	rdtscll(tsc2);
 
 	/* Enable IRQs */
 	local_irq_restore(flags);
@@ -123,6 +128,7 @@ static void speedstep_set_state (unsigne
 		printk (KERN_ERR "cpufreq: change failed - I/O error\n");
 	}
 
+	printk(KERN_ERR "cpufreq transition took %llu cycles\n", tsc2 - tsc1);
 	return;
 }
 

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