Re: [PATCH] transition latency of speedstep-ich (third try)

[Eric Piel <Eric.Piel@tremplin-utc.net>]

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05.10.2005 22:39, Pallipadi, Venkatesh wrote/a écrit:
>>-----Original Message-----
>>From: Eric Piel [mailto:Eric.Piel@tremplin-utc.net] 
>>Sent: Thursday, September 29, 2005 3:06 PM
>>
>>>>As it's very different from the numbers you got, I wonder if 
>>
>>I mistook 
>>
>>>>somewhere ?
>>>>
>>>
>>>
>>>I don't have any numbers with Coppermine or P4-M. Probably the reason
>>>For low numbers is TSC itself stops at certain times during 
>>
>>this whole
>>
>>>Operation. And it will also run at slower frequency once you 
>>
>>change the
>>
>>>Freq (On coppermine). 6uS is too low in my opinion. We may not be 
>>>measuring correctly here.
>>
>>Could it happen that on a P4M the TSC doesn't stop? Then maybe someone 
>>with such a harware could try? Otherwise, what do you suggest 
>>to obtain 
>>the maximum transition latency? Take 500uS and multiply by the 
>>number of 
>>I/O in the code ?
>>
>>Eric
>>
> 
> 
> Do you have ACPI PM timer on your system? May be we can measure the 
> latency using that. 
> 
Hello,

Sorry for the looonnnggg delay of the reply. I've finally found time to 
hunt for the PM timer on my computer, found it, and kludged 
speedstep-ich to read it :-) For verification and completeness, the 
patch is attached. (the PM timer address is hard-coded, it has to be 
changed before running it on another system, it's indicated at boot in 
dmesg).

So the results are quite interesting and confirm your expectations, 
Venki. After few hours with the ondemand governor, I checked the logs 
and the transition latency seems very stable: around 735 to 742 PM timer 
ticks (~206 us). So indeed, 100us of transition latency was quite 
under-estimating it!

Now back to the original problem, from those measurements, which time 
should we put as the maximal transition latency for speedstep-ich? Do 
you think we can simply put something like 300us and that's it? Maybe we 
could distinguish between PIII and P4 ? It would require someone to 
rerun the measurement on a P4 hardware. Do we need to take into account 
as a parameter the CPU frequency?

Hoping we can finally get the ondemand governor working with speedstep-ich!

Eric

[-- Attachment #2: speedstep-ich-measure-transition-2.6.14.patch --]
[-- Type: text/x-patch, Size: 2180 bytes --]

--- linux-2.6.14.bak/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c	2005-11-06 14:50:34.000000000 +0100
+++ linux-2.6.14/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c	2005-11-26 22:26:28.000000000 +0100
@@ -55,6 +55,32 @@ static struct cpufreq_frequency_table sp
 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-ich", msg)
 
 
+/* from timer_pm.c */
+u32 pmtmr_ioport =  0x1008; // from dmesg , to avoid having to export it
+
+#define ACPI_PM_MASK 0xFFFFFF /* limit it to 24 bits */
+
+/*helper function to safely read acpi pm timesource*/
+static inline u32 read_pmtmr(void)
+{
+	u32 v1=0,v2=0,v3=0;
+	/* It has been reported that because of various broken
+	 * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM time
+	 * source is not latched, so you must read it multiple
+	 * times to insure a safe value is read.
+	 */
+	do {
+		v1 = inl(pmtmr_ioport);
+		v2 = inl(pmtmr_ioport);
+		v3 = inl(pmtmr_ioport);
+	} while ((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
+			|| (v3 > v1 && v3 < v2));
+
+	/* mask the output to 24 bits */
+	return v2 & ACPI_PM_MASK;
+}
+
+
 /**
  * speedstep_set_state - set the SpeedStep state
  * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
@@ -67,6 +93,8 @@ static void speedstep_set_state (unsigne
 	u8 pm2_blk;
 	u8 value;
 	unsigned long flags;
+	unsigned long long tsc1, tsc2;
+	u32 pmt1, pmt2;
 
 	if (!speedstep_chipset_dev || (state > 0x1))
 		return;
@@ -87,6 +115,9 @@ static void speedstep_set_state (unsigne
 	/* Disable IRQs */
 	local_irq_save(flags);
 
+	rdtscll(tsc1);
+	pmt1 = read_pmtmr();
+	
 	/* read state */
 	value = inb(pmbase + 0x50);
 
@@ -112,6 +143,9 @@ static void speedstep_set_state (unsigne
 
 	/* check if transition was successful */
 	value = inb(pmbase + 0x50);
+	
+	rdtscll(tsc2);
+	pmt2 = read_pmtmr();
 
 	/* Enable IRQs */
 	local_irq_restore(flags);
@@ -124,6 +158,8 @@ static void speedstep_set_state (unsigne
 		printk (KERN_ERR "cpufreq: change failed - I/O error\n");
 	}
 
+	printk(KERN_ERR "cpufreq transition took %llu TSC cycles\n", tsc2 - tsc1);
+	printk(KERN_ERR "cpufreq transition took %u PM timer cycles\n", pmt2 - pmt1);
 	return;
 }
 

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