From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Lizhi Hou <lizhi.hou@amd.com>, Brian Xu <brian.xu@amd.com>,
Raj Kumar Rampelli <raj.kumar.rampelli@amd.com>,
Vinod Koul <vkoul@kernel.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Michal Simek <monstr@monstr.eu>,
dmaengine@vger.kernel.org,
Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH v2 3/4] dmaengine: xilinx: xdma: Better handling of the busy variable
Date: Thu, 30 Nov 2023 12:13:14 +0100 [thread overview]
Message-ID: <20231130111315.729430-4-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20231130111315.729430-1-miquel.raynal@bootlin.com>
The driver internal scatter-gather logic is:
* set busy to true
* start transfer
<irq>
* set busy to false
* trigger next transfer if any
* set busy to true
</irq>
Setting busy to false in cyclic transfers does not make any sense and is
conceptually wrong. In order to ease the integration of additional
callbacks let's move this change to the scatter-gather path.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
---
drivers/dma/xilinx/xdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c
index 4efef1b5f89c..e931ff42209c 100644
--- a/drivers/dma/xilinx/xdma.c
+++ b/drivers/dma/xilinx/xdma.c
@@ -745,7 +745,6 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id)
if (!vd)
goto out;
- xchan->busy = false;
desc = to_xdma_desc(vd);
xdev = xchan->xdev_hdl;
@@ -766,6 +765,7 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id)
vchan_cyclic_callback(vd);
} else {
+ xchan->busy = false;
desc->completed_desc_num += complete_desc_num;
/* if all data blocks are transferred, remove and complete the request */
--
2.34.1
next prev parent reply other threads:[~2023-11-30 11:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-30 11:13 [PATCH v2 0/4] dmaengine: xilinx: Misc (cyclic) transfers fixes Miquel Raynal
2023-11-30 11:13 ` [PATCH v2 1/4] dmaengine: xilinx: xdma: Fix the count of elapsed periods in cyclic mode Miquel Raynal
2023-11-30 11:13 ` [PATCH v2 2/4] dmaengine: xilinx: xdma: Clarify the logic between cyclic/sg modes Miquel Raynal
2023-11-30 11:13 ` Miquel Raynal [this message]
2023-11-30 11:13 ` [PATCH v2 4/4] dmaengine: xilinx: xdma: Add terminate_all/synchronize callbacks Miquel Raynal
2023-11-30 17:28 ` Lizhi Hou
2023-11-30 19:06 ` Jan Kuliga
2023-11-30 19:23 ` Miquel Raynal
2023-12-04 9:34 ` Jan Kuliga
2023-12-04 11:02 ` Miquel Raynal
2023-12-04 13:13 ` Jan Kuliga
2023-12-04 14:36 ` Miquel Raynal
2023-12-04 16:41 ` Lizhi Hou
2023-12-08 14:27 ` Jan Kuliga
2023-12-21 16:30 ` [PATCH v2 0/4] dmaengine: xilinx: Misc (cyclic) transfers fixes Vinod Koul
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