From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Jan Kuliga <jankul@alatek.krakow.pl>
Cc: Lizhi Hou <lizhi.hou@amd.com>, Brian Xu <brian.xu@amd.com>,
Raj Kumar Rampelli <raj.kumar.rampelli@amd.com>,
Vinod Koul <vkoul@kernel.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Michal Simek <monstr@monstr.eu>,
dmaengine@vger.kernel.org
Subject: Re: [PATCH v2 4/4] dmaengine: xilinx: xdma: Add terminate_all/synchronize callbacks
Date: Mon, 4 Dec 2023 12:02:53 +0100 [thread overview]
Message-ID: <20231204120253.2591eb0b@xps-13> (raw)
In-Reply-To: <d27730fb-1c45-41e6-8cad-da172adf99d0@alatek.krakow.pl>
Hi Jan,
> >>>> + vchan_synchronize(&xdma_chan->vchan);
> >>>> +}
> >>>> +
> >>>> /**
> >>>> * xdma_prep_device_sg - prepare a descriptor for a DMA
> tr
> >> ansaction
> >>>> * @chan: DMA channel pointer
> >>>> @@ -1088,6 +1154,8 @@ static int xdma_probe(struct platform_device *
> pd
> >> ev)
> >>>> xdev->dma_dev.device_prep_slave_sg =
> xdma_prep_device_sg;
> >>>> xdev->dma_dev.device_config = xdma
> _de
> >> vice_config;
> >>>> xdev->dma_dev.device_issue_pending =
> xdma_issue_pending;
> >>>> + xdev->dma_dev.device_terminate_all = xdma_term
> in
> >> ate_all;
> >>>> + xdev->dma_dev.device_synchronize = xdma_synchr
> on
> >> ize;
> >>>> xdev->dma_dev.filter.map = pdata->
> dev
> >> ice_map;
> >>>> xdev->dma_dev.filter.mapcnt = pdat
> a->
> >> device_map_cnt;
> >>>> xdev->dma_dev.filter.fn = xdma_fil
> ter
> >> _fn;
Not related, but if you could fix your mailer, it is a bit hard to
track your answers.
> >>
> >> I have already prepared a patch with an appropriate fix, which I'm goi
> ng to submit with the whole patch series, once I have interleaved DMA tra
> nsfers properly sorted out (hopefully soon). Or maybe should I post this patch with fix, immediately as a reply to the already sent one? What do y
> ou prefer?
> >
> > I see. Well in the case of cyclic transfers it looks like this is enoug
> h
> > (I don't have any way to test interleaved/SG transfers) so maybe
> > maintainers can take this now as it is ready and fixes cyclic
> > transfers, so when the interleaved transfers are ready you can
> > improve these functions with a series on top of it?
> >
> So I decided to base my new patchset on my previous one, as I haven't seen any ack from any maintainer yet on both mine and your patchset. I'm going to submit it this week.
Well, the difference between the two approaches is that I am fixing
something upstream, and you're adding a new feature, which is not
ready yet. I don't mind about using your patch though, I just want
upstream to be fixed.
> This specific commit of yours (PATCH 4/4) basically does the same thing as mine patch, so there will be no difference in its functionality, i.e. it will also fix cyclic transfers.
Thanks,
Miquèl
next prev parent reply other threads:[~2023-12-04 11:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-30 11:13 [PATCH v2 0/4] dmaengine: xilinx: Misc (cyclic) transfers fixes Miquel Raynal
2023-11-30 11:13 ` [PATCH v2 1/4] dmaengine: xilinx: xdma: Fix the count of elapsed periods in cyclic mode Miquel Raynal
2023-11-30 11:13 ` [PATCH v2 2/4] dmaengine: xilinx: xdma: Clarify the logic between cyclic/sg modes Miquel Raynal
2023-11-30 11:13 ` [PATCH v2 3/4] dmaengine: xilinx: xdma: Better handling of the busy variable Miquel Raynal
2023-11-30 11:13 ` [PATCH v2 4/4] dmaengine: xilinx: xdma: Add terminate_all/synchronize callbacks Miquel Raynal
2023-11-30 17:28 ` Lizhi Hou
2023-11-30 19:06 ` Jan Kuliga
2023-11-30 19:23 ` Miquel Raynal
2023-12-04 9:34 ` Jan Kuliga
2023-12-04 11:02 ` Miquel Raynal [this message]
2023-12-04 13:13 ` Jan Kuliga
2023-12-04 14:36 ` Miquel Raynal
2023-12-04 16:41 ` Lizhi Hou
2023-12-08 14:27 ` Jan Kuliga
2023-12-21 16:30 ` [PATCH v2 0/4] dmaengine: xilinx: Misc (cyclic) transfers fixes Vinod Koul
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