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* [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters
@ 2024-01-05 10:59 Peter Korsgaard
  2024-01-05 18:48 ` Pandey, Radhey Shyam
  2024-01-22 16:25 ` Vinod Koul
  0 siblings, 2 replies; 3+ messages in thread
From: Peter Korsgaard @ 2024-01-05 10:59 UTC (permalink / raw)
  To: Vinod Koul, dmaengine; +Cc: Michal Simek, Peter Korsgaard

The VDMA HSIZE register (corresponding to sgl[0].size) is only 16bit wide /
the VSIZE register (corresponding to numf) is only 13bit wide, so reject
requests not fitting within that rather than silently transferring too
little data.

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
---
 drivers/dma/xilinx/xilinx_dma.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index e40696f6f864..5eb51ae93e89 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -112,7 +112,9 @@
 
 /* Register Direct Mode Registers */
 #define XILINX_DMA_REG_VSIZE			0x0000
+#define XILINX_DMA_VSIZE_MASK			GENMASK(12, 0)
 #define XILINX_DMA_REG_HSIZE			0x0004
+#define XILINX_DMA_HSIZE_MASK			GENMASK(15, 0)
 
 #define XILINX_DMA_REG_FRMDLY_STRIDE		0x0008
 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT	24
@@ -2050,6 +2052,10 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
 	if (!xt->numf || !xt->sgl[0].size)
 		return NULL;
 
+	if (xt->numf & ~XILINX_DMA_VSIZE_MASK ||
+	    xt->sgl[0].size & ~XILINX_DMA_HSIZE_MASK)
+		return NULL;
+
 	if (xt->frame_size != 1)
 		return NULL;
 
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* RE: [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters
  2024-01-05 10:59 [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters Peter Korsgaard
@ 2024-01-05 18:48 ` Pandey, Radhey Shyam
  2024-01-22 16:25 ` Vinod Koul
  1 sibling, 0 replies; 3+ messages in thread
From: Pandey, Radhey Shyam @ 2024-01-05 18:48 UTC (permalink / raw)
  To: Peter Korsgaard, Vinod Koul, dmaengine@vger.kernel.org; +Cc: Simek, Michal

> -----Original Message-----
> From: Peter Korsgaard <peter@korsgaard.com>
> Sent: Friday, January 5, 2024 4:30 PM
> To: Vinod Koul <vkoul@kernel.org>; dmaengine@vger.kernel.org
> Cc: Michal Simek <michal.simek@amd.com>; Peter Korsgaard
> <peter@korsgaard.com>
> Subject: [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved
> parameters
> 
> The VDMA HSIZE register (corresponding to sgl[0].size) is only 16bit wide /
> the VSIZE register (corresponding to numf) is only 13bit wide, so reject
> requests not fitting within that rather than silently transferring too little data.
> 
> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!

> ---
>  drivers/dma/xilinx/xilinx_dma.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/dma/xilinx/xilinx_dma.c
> b/drivers/dma/xilinx/xilinx_dma.c index e40696f6f864..5eb51ae93e89
> 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -112,7 +112,9 @@
> 
>  /* Register Direct Mode Registers */
>  #define XILINX_DMA_REG_VSIZE			0x0000
> +#define XILINX_DMA_VSIZE_MASK			GENMASK(12, 0)
>  #define XILINX_DMA_REG_HSIZE			0x0004
> +#define XILINX_DMA_HSIZE_MASK			GENMASK(15, 0)
> 
>  #define XILINX_DMA_REG_FRMDLY_STRIDE		0x0008
>  #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT	24
> @@ -2050,6 +2052,10 @@ xilinx_vdma_dma_prep_interleaved(struct
> dma_chan *dchan,
>  	if (!xt->numf || !xt->sgl[0].size)
>  		return NULL;
> 
> +	if (xt->numf & ~XILINX_DMA_VSIZE_MASK ||
> +	    xt->sgl[0].size & ~XILINX_DMA_HSIZE_MASK)
> +		return NULL;
> +
>  	if (xt->frame_size != 1)
>  		return NULL;
> 
> --
> 2.39.2


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters
  2024-01-05 10:59 [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters Peter Korsgaard
  2024-01-05 18:48 ` Pandey, Radhey Shyam
@ 2024-01-22 16:25 ` Vinod Koul
  1 sibling, 0 replies; 3+ messages in thread
From: Vinod Koul @ 2024-01-22 16:25 UTC (permalink / raw)
  To: dmaengine, Peter Korsgaard; +Cc: Michal Simek


On Fri, 05 Jan 2024 11:59:56 +0100, Peter Korsgaard wrote:
> The VDMA HSIZE register (corresponding to sgl[0].size) is only 16bit wide /
> the VSIZE register (corresponding to numf) is only 13bit wide, so reject
> requests not fitting within that rather than silently transferring too
> little data.
> 
> 

Applied, thanks!

[1/1] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters
      commit: 8fcc3f7dbdaeff3c3be47a15d1acd7863dfee92d

Best regards,
-- 
~Vinod



^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2024-01-22 16:25 UTC | newest]

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2024-01-05 10:59 [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters Peter Korsgaard
2024-01-05 18:48 ` Pandey, Radhey Shyam
2024-01-22 16:25 ` Vinod Koul

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