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From: sashiko-bot@kernel.org
To: "Claudiu Beznea" <claudiu.beznea.uj@bp.renesas.com>
Cc: dmaengine@vger.kernel.org, Frank.Li@kernel.org, vkoul@kernel.org,
	wsa+renesas@sang-engineering.com
Subject: Re: [PATCH v5 10/17] dmaengine: sh: rz-dmac: Refactor pause/resume code
Date: Thu, 14 May 2026 00:57:06 +0000	[thread overview]
Message-ID: <20260514005707.63ECEC19425@smtp.kernel.org> (raw)
In-Reply-To: <20260512121219.216159-11-claudiu.beznea.uj@bp.renesas.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Hardware is prematurely resumed when multiple pause sources are active.
- [High] Software status bitmask is incorrectly updated even if the hardware resume operation times out.
--

commit 6c32a478012b8f47e162dfe05b689182e89ba6c2
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

dmaengine: sh: rz-dmac: Refactor pause/resume code

This commit refactors the pause/resume functionality to introduce _set
variants using a channel->status bitmask. This prepares the driver for
suspend/resume and cyclic DMA support where multiple pause sources might
exist.

> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
[ ... ]
> @@ -795,35 +811,70 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan,
[ ... ]
> +static int rz_dmac_device_resume_set(struct rz_dmac_chan *channel,
> +				     unsigned long clear_bitmask)
> +{
> +	int ret = 0;
> +	u32 val;
> +
> +	lockdep_assert_held(&channel->vc.lock);
> +
> +	/* Do not check CHSTAT_SUS but rely on HW capabilities. */
> +
> +	rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1);

If there are multiple active pause sources (for example, paused by the DMA
client and by system suspend), will writing CHCTRL_CLRSUS here resume the
hardware prematurely?

Since this function is designed to clear a specific bitmask from the channel
status, should the hardware resume operation only be performed if there are
no other pause bits remaining in channel->status?

> +	ret = read_poll_timeout_atomic(rz_dmac_ch_readl, val,
> +				       !(val & CHSTAT_SUS), 1, 1024, false,
> +				       channel, CHSTAT, 1);
> +
> +	channel->status &= ~clear_bitmask;

If the hardware resume operation times out and returns an error, is it
expected to clear the status bitmask anyway?

If a caller receives an error and attempts to retry the resume operation,
the channel->status bit will already be cleared. Does this prevent the retry
from succeeding, leaving the hardware stuck in a paused state?

> +
> +	return ret;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260512121219.216159-1-claudiu.beznea.uj@bp.renesas.com?part=10

  parent reply	other threads:[~2026-05-14  0:57 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-12 12:12 [PATCH v5 00/17] Renesas: dmaengine and ASoC fixes Claudiu Beznea
2026-05-12 12:12 ` [PATCH v5 01/17] dmaengine: sh: rz-dmac: Move interrupt request after everything is set up Claudiu Beznea
2026-05-12 20:28   ` Frank Li
2026-05-13 21:44   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 02/17] dmaengine: sh: rz-dmac: Fix incorrect NULL check on list_first_entry() Claudiu Beznea
2026-05-12 20:35   ` Frank Li
2026-05-13 13:31     ` Claudiu Beznea
2026-05-13 22:00   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 03/17] dmaengine: sh: rz-dmac: Use list_first_entry_or_null() Claudiu Beznea
2026-05-12 20:38   ` Frank Li
2026-05-13 22:18   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 04/17] dmaengine: sh: rz-dmac: Use rz_dmac_disable_hw() Claudiu Beznea
2026-05-12 20:42   ` Frank Li
2026-05-12 12:12 ` [PATCH v5 05/17] dmaengine: sh: rz-dmac: Add helper to compute the lmdesc address Claudiu Beznea
2026-05-12 20:44   ` Frank Li
2026-05-12 12:12 ` [PATCH v5 06/17] dmaengine: sh: rz-dmac: Save the start LM descriptor Claudiu Beznea
2026-05-12 20:48   ` Frank Li
2026-05-13 13:33     ` Claudiu Beznea
2026-05-13 23:52   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 07/17] dmaengine: sh: rz-dmac: Add helper to check if the channel is enabled Claudiu Beznea
2026-05-12 20:49   ` Frank Li
2026-05-13 23:59   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 08/17] dmaengine: sh: rz-dmac: Add helper to check if the channel is paused Claudiu Beznea
2026-05-12 20:57   ` Frank Li
2026-05-12 12:12 ` [PATCH v5 09/17] dmaengine: sh: rz-dmac: Use virt-dma APIs for channel descriptor processing Claudiu Beznea
2026-05-12 21:38   ` Frank Li
2026-05-13 13:34     ` Claudiu Beznea
2026-05-14  0:42   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 10/17] dmaengine: sh: rz-dmac: Refactor pause/resume code Claudiu Beznea
2026-05-12 21:43   ` Frank Li
2026-05-13 13:35     ` Claudiu Beznea
2026-05-14  0:57   ` sashiko-bot [this message]
2026-05-12 12:12 ` [PATCH v5 11/17] dmaengine: sh: rz-dmac: Drop the update of channel->chctrl with CHCTRL_SETEN Claudiu Beznea
2026-05-12 21:55   ` Frank Li
2026-05-12 12:12 ` [PATCH v5 12/17] dmaengine: sh: rz-dmac: Add cyclic DMA support Claudiu Beznea
2026-05-12 22:00   ` Frank Li
2026-05-13 13:38     ` Claudiu Beznea
2026-05-14  1:43   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 13/17] dmaengine: sh: rz-dmac: Add runtime PM support Claudiu Beznea
2026-05-12 22:03   ` Frank Li
2026-05-13 13:39     ` Claudiu Beznea
2026-05-13 19:56       ` Frank Li
2026-05-14  9:20         ` Claudiu Beznea
2026-05-14  2:08   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 14/17] dmaengine: sh: rz-dmac: Add suspend to RAM support Claudiu Beznea
2026-05-14  3:04   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 15/17] ASoC: renesas: rz-ssi: Add pause support Claudiu Beznea
2026-05-14  3:54   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 16/17] ASoC: renesas: rz-ssi: Use generic PCM dmaengine APIs Claudiu Beznea
2026-05-14  4:52   ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 17/17] dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor Claudiu Beznea
2026-05-14  5:22   ` sashiko-bot

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