From: sashiko-bot@kernel.org
To: "Claudiu Beznea" <claudiu.beznea.uj@bp.renesas.com>
Cc: vkoul@kernel.org, Frank.Li@kernel.org, dmaengine@vger.kernel.org,
wsa+renesas@sang-engineering.com
Subject: Re: [PATCH v5 17/17] dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor
Date: Thu, 14 May 2026 05:22:49 +0000 [thread overview]
Message-ID: <20260514052250.9F7ADC2BCC6@smtp.kernel.org> (raw)
In-Reply-To: <20260512121219.216159-18-claudiu.beznea.uj@bp.renesas.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing bounds check on `sg_len` in `rz_dmac_prep_slave_sg()` leading to hardware descriptor ring overwrite and silent data corruption.
--
commit a98e7dbe1a1cc544a92a491414810a97272d12ae
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor
This commit modifies the RZ/G2L DMA driver to set the Link End (LE) bit
on the last descriptor of a transfer. This informs the DMA engine that
the transfer is finished, preventing it from loading invalid descriptors
and halting without raising an interrupt.
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
[ ... ]
> @@ -425,7 +426,7 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel)
> lmdesc->chext = 0;
> if (i == (sg_len - 1)) {
> lmdesc->chcfg = (channel->chcfg & ~CHCFG_DEM);
> - lmdesc->header = HEADER_LV;
> + lmdesc->header = HEADER_LV | HEADER_LE;
> } else {
> lmdesc->chcfg = channel->chcfg;
> lmdesc->header = HEADER_LV;
Does this code safely handle scatterlists that are larger than the hardware
descriptor ring?
If a DMA client submits a scatterlist with more than DMAC_NR_LMDESC (64)
segments, the initialization loop wraps around and overwrites the beginning
of the descriptor ring:
if (++lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC))
lmdesc = channel->lmdesc.base;
Because this update unconditionally applies the HEADER_LE bit to the final
segment (i == sg_len - 1), an oversized scatterlist would cause the last
overwritten descriptor to receive the HEADER_LE bit.
When the DMA engine starts, it executes the first few overwritten segments
and prematurely halts when it encounters the misplaced Link End bit, dropping
the rest of the segments without raising an error.
Should rz_dmac_prep_slave_sg() check for sg_len > DMAC_NR_LMDESC and return
NULL to avoid data corruption, similar to how rz_dmac_prep_dma_cyclic()
explicitly checks if periods is greater than DMAC_NR_LMDESC?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260512121219.216159-1-claudiu.beznea.uj@bp.renesas.com?part=17
prev parent reply other threads:[~2026-05-14 5:22 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 12:12 [PATCH v5 00/17] Renesas: dmaengine and ASoC fixes Claudiu Beznea
2026-05-12 12:12 ` [PATCH v5 01/17] dmaengine: sh: rz-dmac: Move interrupt request after everything is set up Claudiu Beznea
2026-05-12 20:28 ` Frank Li
2026-05-13 21:44 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 02/17] dmaengine: sh: rz-dmac: Fix incorrect NULL check on list_first_entry() Claudiu Beznea
2026-05-12 20:35 ` Frank Li
2026-05-13 13:31 ` Claudiu Beznea
2026-05-13 22:00 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 03/17] dmaengine: sh: rz-dmac: Use list_first_entry_or_null() Claudiu Beznea
2026-05-12 20:38 ` Frank Li
2026-05-13 22:18 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 04/17] dmaengine: sh: rz-dmac: Use rz_dmac_disable_hw() Claudiu Beznea
2026-05-12 20:42 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 05/17] dmaengine: sh: rz-dmac: Add helper to compute the lmdesc address Claudiu Beznea
2026-05-12 20:44 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 06/17] dmaengine: sh: rz-dmac: Save the start LM descriptor Claudiu Beznea
2026-05-12 20:48 ` Frank Li
2026-05-13 13:33 ` Claudiu Beznea
2026-05-13 23:52 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 07/17] dmaengine: sh: rz-dmac: Add helper to check if the channel is enabled Claudiu Beznea
2026-05-12 20:49 ` Frank Li
2026-05-13 23:59 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 08/17] dmaengine: sh: rz-dmac: Add helper to check if the channel is paused Claudiu Beznea
2026-05-12 20:57 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 09/17] dmaengine: sh: rz-dmac: Use virt-dma APIs for channel descriptor processing Claudiu Beznea
2026-05-12 21:38 ` Frank Li
2026-05-13 13:34 ` Claudiu Beznea
2026-05-14 0:42 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 10/17] dmaengine: sh: rz-dmac: Refactor pause/resume code Claudiu Beznea
2026-05-12 21:43 ` Frank Li
2026-05-13 13:35 ` Claudiu Beznea
2026-05-14 0:57 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 11/17] dmaengine: sh: rz-dmac: Drop the update of channel->chctrl with CHCTRL_SETEN Claudiu Beznea
2026-05-12 21:55 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 12/17] dmaengine: sh: rz-dmac: Add cyclic DMA support Claudiu Beznea
2026-05-12 22:00 ` Frank Li
2026-05-13 13:38 ` Claudiu Beznea
2026-05-14 1:43 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 13/17] dmaengine: sh: rz-dmac: Add runtime PM support Claudiu Beznea
2026-05-12 22:03 ` Frank Li
2026-05-13 13:39 ` Claudiu Beznea
2026-05-13 19:56 ` Frank Li
2026-05-14 9:20 ` Claudiu Beznea
2026-05-14 2:08 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 14/17] dmaengine: sh: rz-dmac: Add suspend to RAM support Claudiu Beznea
2026-05-14 3:04 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 15/17] ASoC: renesas: rz-ssi: Add pause support Claudiu Beznea
2026-05-14 3:54 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 16/17] ASoC: renesas: rz-ssi: Use generic PCM dmaengine APIs Claudiu Beznea
2026-05-14 4:52 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 17/17] dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor Claudiu Beznea
2026-05-14 5:22 ` sashiko-bot [this message]
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