DMA Engine development
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Koichiro Den" <den@valinux.co.jp>
Cc: vkoul@kernel.org, dmaengine@vger.kernel.org, Frank.Li@kernel.org
Subject: Re: [PATCH v6 10/14] dmaengine: dw-edma-pcie: Add register offset match flag
Date: Tue, 21 Jul 2026 06:45:02 +0000	[thread overview]
Message-ID: <20260721064502.E56821F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260721062815.4117887-11-den@valinux.co.jp>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] IRQ vectors allocated by `pci_alloc_irq_vectors()` are leaked on error paths and during device unbinding.
--

--- Patch [10]: [PATCH v6 10/14] dmaengine: dw-edma-pcie: Add register offset match flag ---
commit 96fe59ecf68ecec537def0ad5937dd1f7c596bd9
Author: Koichiro Den <den@valinux.co.jp>

dmaengine: dw-edma-pcie: Add register offset match flag

Add a match-data flag for devices whose DMA register block starts at an
offset inside the mapped BAR. Existing Synopsys EDDA and AMD (Xilinx)
MDB/CPM6 matches keep using the BAR mapping base directly.

> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index 99ddb6e6da348..4b2757c1eda28 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c

[ ... ]

> @@ -464,6 +465,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
>  	chip->reg_base = pcim_iomap_table(pdev)[dma_data->rg.bar];
>  	if (!chip->reg_base)
>  		return -ENOMEM;

[Severity: High]
This is a pre-existing issue, but does this error path leak IRQ vectors?

Looking at dw_edma_pcie_probe(), pci_alloc_irq_vectors() is called earlier
in the function to allocate IRQ resources. However, this direct return on
failure bypasses releasing them.

It looks like other error returns after IRQ allocation, as well as the
dw_edma_pcie_remove() function, might also be missing a call to
pci_free_irq_vectors().

Could we exhaust system IRQ capacity if these resources are leaked during
failed probe attempts or device unbinding?

> +	if (match->flags & DW_EDMA_PCIE_F_REG_OFFSET)
> +		chip->reg_base += dma_data->rg.off;
>  
>  	for (i = 0; i < chip->ll_wr_cnt && !dma_data->cfg_non_ll; i++) {
>  		struct dw_edma_region *ll_region = &chip->ll_region_wr[i];

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260721062815.4117887-1-den@valinux.co.jp?part=10

  reply	other threads:[~2026-07-21  6:45 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-21  6:28 [PATCH v6 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-07-21  6:28 ` [PATCH v6 01/14] dmaengine: dw-edma: Factor out HDMA interrupt setup helper Koichiro Den
2026-07-21  6:28 ` [PATCH v6 02/14] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-07-21  6:43   ` sashiko-bot
2026-07-21  6:28 ` [PATCH v6 03/14] dmaengine: dw-edma: Add core quiesce operations Koichiro Den
2026-07-21  6:28 ` [PATCH v6 04/14] dmaengine: dw-edma: Initialize IRQ data before requesting IRQs Koichiro Den
2026-07-21  6:45   ` sashiko-bot
2026-07-21  6:28 ` [PATCH v6 05/14] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-07-21  6:46   ` sashiko-bot
2026-07-21  6:28 ` [PATCH v6 06/14] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 07/14] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 08/14] dmaengine: dw-edma-pcie: Rename vsec_data to dma_data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 09/14] dmaengine: dw-edma-pcie: Add platform ops to match data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 10/14] dmaengine: dw-edma-pcie: Add register offset match flag Koichiro Den
2026-07-21  6:45   ` sashiko-bot [this message]
2026-07-21  6:28 ` [PATCH v6 11/14] dmaengine: dw-edma-pcie: Factor out descriptor block address lookup Koichiro Den
2026-07-21  6:28 ` [PATCH v6 12/14] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-07-21  6:28 ` [PATCH v6 13/14] dmaengine: dw-edma-pcie: Add chip flags to match data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 14/14] dmaengine: dw-edma: Program endpoint function numbers Koichiro Den
2026-07-21  6:51   ` sashiko-bot
2026-07-21 11:24 ` [PATCH v6 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Vinod Koul

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260721064502.E56821F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=Frank.Li@kernel.org \
    --cc=den@valinux.co.jp \
    --cc=dmaengine@vger.kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox