DMA Engine development
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Koichiro Den" <den@valinux.co.jp>
Cc: dmaengine@vger.kernel.org, vkoul@kernel.org, Frank.Li@kernel.org
Subject: Re: [PATCH v6 05/14] dmaengine: dw-edma: Add partial channel ownership mode
Date: Tue, 21 Jul 2026 06:46:52 +0000	[thread overview]
Message-ID: <20260721064652.CF39E1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260721062815.4117887-6-den@valinux.co.jp>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Teardown asymmetry / UAF risk in dw_edma_remove
--

--- Patch [5]: [PATCH v6 05/14] dmaengine: dw-edma: Add partial channel ownership mode ---
commit 4c8696aea18fd0130d8ca7adb9a53eadf014e468
Author: Koichiro Den <den@valinux.co.jp>

dmaengine: dw-edma: Add partial channel ownership mode

This commit adds a partial ownership flag for DesignWare eDMA instances
representing a subset of channels. It modifies initialization and teardown
to use a limited quiesce path instead of full core resets, preserving
controller-wide state owned by the peer.

> diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
> index ee9a8c32adf4c..c9df5bbe23925 100644
> --- a/drivers/dma/dw-edma/dw-edma-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-core.c

[ ... ]

> @@ -1213,14 +1268,16 @@ int dw_edma_remove(struct dw_edma_chip *chip)
>  	struct dw_edma_chan *chan, *_chan;
>  	struct device *dev = chip->dev;
>  	struct dw_edma *dw = chip->dw;
> -	int i;
> +	int i, err = 0;
>  
>  	/* Skip removal if no private data found */
>  	if (!dw)
>  		return -ENODEV;
>  
> -	/* Disable eDMA */
> -	dw_edma_core_off(dw);
> +	if (chip->flags & DW_EDMA_CHIP_PARTIAL)
> +		err = dw_edma_core_quiesce(dw);
> +	else
> +		dw_edma_core_off(dw);

[Severity: High]
This is a pre-existing issue, but does the teardown sequence in
dw_edma_remove() risk a use-after-free during device unbind?

Looking at dw_edma_remove() in drivers/dma/dw-edma/dw-edma-core.c, the core is
disabled here, IRQs are freed, and the workqueue is destroyed via
destroy_workqueue(dw->wq). Only after these steps are completed is the device
unregistered from the DMA subsystem via dma_async_device_unregister(&dw->dma).

Since the device is still exposed to the DMA engine subsystem during this
window, could a client request a channel or submit a new DMA transfer, causing
the driver to queue operations on the already destroyed workqueue or program
disabled hardware?

>  	/* Free irqs */
>  	for (i = (dw->nr_irqs - 1); i >= 0; i--)

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260721062815.4117887-1-den@valinux.co.jp?part=5

  reply	other threads:[~2026-07-21  6:46 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-21  6:28 [PATCH v6 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-07-21  6:28 ` [PATCH v6 01/14] dmaengine: dw-edma: Factor out HDMA interrupt setup helper Koichiro Den
2026-07-21  6:28 ` [PATCH v6 02/14] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-07-21  6:43   ` sashiko-bot
2026-07-21  6:28 ` [PATCH v6 03/14] dmaengine: dw-edma: Add core quiesce operations Koichiro Den
2026-07-21  6:28 ` [PATCH v6 04/14] dmaengine: dw-edma: Initialize IRQ data before requesting IRQs Koichiro Den
2026-07-21  6:45   ` sashiko-bot
2026-07-21  6:28 ` [PATCH v6 05/14] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-07-21  6:46   ` sashiko-bot [this message]
2026-07-21  6:28 ` [PATCH v6 06/14] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 07/14] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 08/14] dmaengine: dw-edma-pcie: Rename vsec_data to dma_data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 09/14] dmaengine: dw-edma-pcie: Add platform ops to match data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 10/14] dmaengine: dw-edma-pcie: Add register offset match flag Koichiro Den
2026-07-21  6:45   ` sashiko-bot
2026-07-21  6:28 ` [PATCH v6 11/14] dmaengine: dw-edma-pcie: Factor out descriptor block address lookup Koichiro Den
2026-07-21  6:28 ` [PATCH v6 12/14] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-07-21  6:28 ` [PATCH v6 13/14] dmaengine: dw-edma-pcie: Add chip flags to match data Koichiro Den
2026-07-21  6:28 ` [PATCH v6 14/14] dmaengine: dw-edma: Program endpoint function numbers Koichiro Den
2026-07-21  6:51   ` sashiko-bot
2026-07-21 11:24 ` [PATCH v6 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Vinod Koul

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260721064652.CF39E1F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=Frank.Li@kernel.org \
    --cc=den@valinux.co.jp \
    --cc=dmaengine@vger.kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox