From: sashiko-bot@kernel.org
To: "Koichiro Den" <den@valinux.co.jp>
Cc: vkoul@kernel.org, Frank.Li@kernel.org, dmaengine@vger.kernel.org
Subject: Re: [PATCH v6 14/14] dmaengine: dw-edma: Program endpoint function numbers
Date: Tue, 21 Jul 2026 06:51:06 +0000 [thread overview]
Message-ID: <20260721065107.19F381F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260721062815.4117887-15-den@valinux.co.jp>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Truncation of PCIe Requester ID using `PCI_FUNC()` breaks IOMMU isolation and DMA for ARI devices and SR-IOV Virtual Functions.
--
--- Patch [14]: [PATCH v6 14/14] dmaengine: dw-edma: Program endpoint function numbers ---
commit 12cd49191ea0c234c70a872c83095a085495199a
Author: Koichiro Den <den@valinux.co.jp>
dmaengine: dw-edma: Program endpoint function numbers
This patch configures the requester function number for eDMA/HDMA transfers
by recording it in the chip data and programming it per channel. It extracts
the function number using PCI_FUNC() during PCIe probe. Endpoint-local
instances keep it at 0, while host-side instances use the probing device's
function number.
[ ... ]
> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index 64f2a80072bce..9f237ba916dea 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
> @@ -473,6 +473,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
>
> chip->mf = dma_data->mf;
> chip->flags = match->chip_flags;
> + chip->func_no = PCI_FUNC(pdev->devfn);
[Severity: High]
Does PCI_FUNC() truncate the function number for Alternative Routing-ID
Interpretation (ARI) devices and SR-IOV Virtual Functions?
PCI_FUNC() masks the input to 3 bits, dropping the upper bits of the
function number. Since ARI or SR-IOV topologies can have function numbers
up to 255 (8 bits), could this cause the host IOMMU to attribute DMA traffic
from functions >= 8 to functions 0-7, breaking isolation?
> chip->nr_irqs = nr_irqs;
> chip->ops = match->plat_ops;
> chip->cfg_non_ll = dma_data->cfg_non_ll;
[ ... ]
> diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c
> index 8d20bb028b528..36ee72efcd317 100644
> --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c
> @@ -345,6 +345,9 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan)
> SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi);
> /* config MSI data */
> SET_CH_32(dw, chan->dir, chan->id, msi_msgdata, chan->msi.data);
> + /* Configure the requester function number used by outbound TLPs. */
> + SET_CH_32(dw, chan->dir, chan->id, func_num,
> + FIELD_PREP(HDMA_V0_FUNC_NUM_PF_MASK, chan->func_no));
[Severity: High]
HDMA_V0_FUNC_NUM_PF_MASK is an 8-bit mask, which implies the hardware expects
the full 8-bit devfn. Because chan->func_no was assigned using PCI_FUNC()
earlier, does this result in programming a truncated 3-bit value into this
8-bit hardware field, causing the hardware to emit TLPs with an incorrect
Requester ID?
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260721062815.4117887-1-den@valinux.co.jp?part=14
next prev parent reply other threads:[~2026-07-21 6:51 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 6:28 [PATCH v6 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-07-21 6:28 ` [PATCH v6 01/14] dmaengine: dw-edma: Factor out HDMA interrupt setup helper Koichiro Den
2026-07-21 6:28 ` [PATCH v6 02/14] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-07-21 6:43 ` sashiko-bot
2026-07-21 6:28 ` [PATCH v6 03/14] dmaengine: dw-edma: Add core quiesce operations Koichiro Den
2026-07-21 6:28 ` [PATCH v6 04/14] dmaengine: dw-edma: Initialize IRQ data before requesting IRQs Koichiro Den
2026-07-21 6:45 ` sashiko-bot
2026-07-21 6:28 ` [PATCH v6 05/14] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-07-21 6:46 ` sashiko-bot
2026-07-21 6:28 ` [PATCH v6 06/14] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data Koichiro Den
2026-07-21 6:28 ` [PATCH v6 07/14] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-07-21 6:28 ` [PATCH v6 08/14] dmaengine: dw-edma-pcie: Rename vsec_data to dma_data Koichiro Den
2026-07-21 6:28 ` [PATCH v6 09/14] dmaengine: dw-edma-pcie: Add platform ops to match data Koichiro Den
2026-07-21 6:28 ` [PATCH v6 10/14] dmaengine: dw-edma-pcie: Add register offset match flag Koichiro Den
2026-07-21 6:45 ` sashiko-bot
2026-07-21 6:28 ` [PATCH v6 11/14] dmaengine: dw-edma-pcie: Factor out descriptor block address lookup Koichiro Den
2026-07-21 6:28 ` [PATCH v6 12/14] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-07-21 6:28 ` [PATCH v6 13/14] dmaengine: dw-edma-pcie: Add chip flags to match data Koichiro Den
2026-07-21 6:28 ` [PATCH v6 14/14] dmaengine: dw-edma: Program endpoint function numbers Koichiro Den
2026-07-21 6:51 ` sashiko-bot [this message]
2026-07-21 11:24 ` [PATCH v6 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Vinod Koul
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