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From: sashiko-bot@kernel.org
To: "Jia Wang" <wangjia@ultrarisc.com>
Cc: vkoul@kernel.org, dmaengine@vger.kernel.org, Frank.Li@kernel.org,
	robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH 12/12] riscv: dts: ultrarisc: Add Milk-V Titan board device tree
Date: Tue, 25 Aug 2026 06:16:16 +0000	[thread overview]
Message-ID: <20260825061616.610111F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260824-ultrarisc-dts-v1-12-61ab7aebe9e5@ultrarisc.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The comment explaining the `phy-mode = "rgmii"` configuration contradicts how the Realtek RTL8211F PHY driver actually behaves.
- [Low] The Ethernet PHY node is named `phy@0` instead of the standard `ethernet-phy@0`.
--

--- Patch [12]: [PATCH 12/12] riscv: dts: ultrarisc: Add Milk-V Titan board device tree ---
commit 3f673472054f18222d34b30ffbabd903e6df950c
Author: Jia Wang <wangjia@ultrarisc.com>

riscv: dts: ultrarisc: Add Milk-V Titan board device tree

This commit adds the device tree for the Milk-V Titan, an ITX motherboard
based on the UltraRISC DP1000 SoC.

Link: https://milkv.io/docs/titan/overview

> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts
> new file mode 100644
> index 0000000000000..f1a0efee3d746
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts

[ ... ]

> +&ethernet {
> +	phy-handle = <&phy0>;
> +	/*
> +	 * RTL8211F: board timing uses PHY strap delays; keep plain "rgmii".
> +	 * Enabling PHY internal delays via "rgmii-id" breaks Ethernet traffic.
> +	 */
> +	phy-mode = "rgmii";

[Severity: Medium]
Does this comment accurately describe how the Realtek RTL8211F PHY driver
handles "rgmii"?

Looking at rtl8211f_config_rgmii_delay() in
drivers/net/phy/realtek/realtek_main.c, configuring an RTL8211F PHY with
phy-mode = "rgmii" causes the driver to explicitly zero out the internal
TX and RX delay registers, overriding and disabling any hardware strap delays.

If the board functions correctly with "rgmii", it actually requires the PHY
delays to be disabled. Could the comment be updated to prevent confusion
about the hardware configuration?

> +
> +	status = "okay";
> +
> +	mdio {
> +		compatible = "snps,dwmac-mdio";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		phy0: phy@0 {
> +			reg = <0>;

[Severity: Low]
Does this node name correctly follow the devicetree bindings for ethernet
PHYs?

The node name phy@0 does not match the regex pattern required by the Ethernet
PHY DT binding (Documentation/devicetree/bindings/net/ethernet-phy.yaml).
The standard name is ethernet-phy@0.

Because the name does not match the expected pattern, the schema validation
is bypassed for this node and its subnodes when running make dtbs_check.

> +
> +			leds {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com?part=12

      parent reply	other threads:[~2026-08-25  6:16 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  5:54 [PATCH 00/12] riscv: Add device tree support for UltraRISC DP1000 Jia Wang via B4 Relay
2026-08-24  5:54 ` [PATCH 01/12] dt-bindings: riscv: cpus: Fix yamllint style issues Jia Wang via B4 Relay
2026-08-24 16:35   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 02/12] dt-bindings: vendor-prefixes: Add shenrongda Jia Wang via B4 Relay
2026-08-24 17:03   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 03/12] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-08-24 17:02   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 04/12] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Jia Wang via B4 Relay
2026-08-24 17:04   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 05/12] dt-bindings: timer: Add UltraRISC DP1000 CLINT Jia Wang via B4 Relay
2026-08-24 17:05   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 06/12] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for UltraRISC DP1000 SoC Jia Wang via B4 Relay
2026-08-24 17:07   ` Conor Dooley
2026-08-24 17:15     ` Conor Dooley
2026-08-25  8:16       ` Jia Wang
2026-08-24  5:54 ` [PATCH 07/12] dt-bindings: i2c: dw: " Jia Wang via B4 Relay
2026-08-24 17:07   ` Conor Dooley
2026-08-24 17:14     ` Conor Dooley
2026-08-25  8:45       ` Jia Wang
2026-08-24  5:54 ` [PATCH 08/12] dt-bindings: net: snps,dwmac: " Jia Wang via B4 Relay
2026-08-24 17:09   ` Conor Dooley
2026-08-24 17:13     ` Conor Dooley
2026-08-25 10:12       ` Jia Wang
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 09/12] dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible Jia Wang via B4 Relay
2026-08-24 17:03   ` Conor Dooley
2026-08-24 17:11     ` Conor Dooley
2026-08-24  5:54 ` [PATCH 10/12] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree Jia Wang via B4 Relay
2026-08-24 13:02   ` Andrew Lunn
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 12/12] riscv: dts: ultrarisc: Add Milk-V Titan " Jia Wang via B4 Relay
2026-08-24 13:06   ` Andrew Lunn
2026-08-25  6:16   ` sashiko-bot [this message]

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