From: Frank Li <Frank.li@nxp.com>
To: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
Cc: Vinod Koul <vkoul@kernel.org>, Greg Ungerer <gerg@linux-m68k.org>,
imx@lists.linux.dev, dmaengine@vger.kernel.org,
linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/7] dma: mcf-edma: Fix interrupt handler for 64 DMA channels
Date: Mon, 24 Nov 2025 11:09:06 -0500 [thread overview]
Message-ID: <aSSDItseEjQ0VMh6@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20251124-dma-coldfire-v1-4-dc8f93185464@yoseli.org>
On Mon, Nov 24, 2025 at 01:50:25PM +0100, Jean-Michel Hautbois wrote:
> Fix the DMA completion interrupt handler to properly handle all 64
> channels on MCF54418 ColdFire processors.
>
> The previous code used BIT(ch) to test interrupt status bits, which
> causes undefined behavior on 32-bit architectures when ch >= 32 because
> unsigned long is 32 bits and the shift would exceed the type width.
>
> Replace with bitmap_from_u64() and for_each_set_bit() which correctly
> handle 64-bit values on 32-bit systems by using a proper bitmap
> representation.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---
> drivers/dma/mcf-edma-main.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> index 8a7c1787adb1f66f3b6729903635b072218afad1..dd64f50f2b0a70a4664b03c7d6a23e74c9bcd7ae 100644
> --- a/drivers/dma/mcf-edma-main.c
> +++ b/drivers/dma/mcf-edma-main.c
> @@ -18,7 +18,8 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> {
> struct fsl_edma_engine *mcf_edma = dev_id;
> struct edma_regs *regs = &mcf_edma->regs;
> - unsigned int ch;
> + unsigned long ch;
channel number max value is 63. unsigned int should be enough.
Frank
> + DECLARE_BITMAP(status_mask, 64);
> u64 intmap;
>
> intmap = ioread32(regs->inth);
> @@ -27,11 +28,11 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> if (!intmap)
> return IRQ_NONE;
>
> - for (ch = 0; ch < mcf_edma->n_chans; ch++) {
> - if (intmap & BIT(ch)) {
> - iowrite8(EDMA_MASK_CH(ch), regs->cint);
> - fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> - }
> + bitmap_from_u64(status_mask, intmap);
> +
> + for_each_set_bit(ch, status_mask, mcf_edma->n_chans) {
> + iowrite8(EDMA_MASK_CH(ch), regs->cint);
> + fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> }
>
> return IRQ_HANDLED;
>
> --
> 2.39.5
>
next prev parent reply other threads:[~2025-11-24 16:09 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 12:50 [PATCH 0/7] dma: fsl/mcf-edma: Bug fixes and enhancements for ColdFire support Jean-Michel Hautbois
2025-11-24 12:50 ` [PATCH 1/7] dma: fsl-edma: Add write barrier after TCD descriptor fill Jean-Michel Hautbois
2025-11-24 15:57 ` Frank Li
2025-11-25 8:18 ` Jean-Michel Hautbois
2025-11-24 12:50 ` [PATCH 2/7] dma: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA Jean-Michel Hautbois
2025-11-24 16:03 ` Frank Li
2025-11-24 12:50 ` [PATCH 3/7] dma: mcf-edma: Add per-channel IRQ naming for debugging Jean-Michel Hautbois
2025-11-24 13:05 ` Geert Uytterhoeven
2025-11-25 8:35 ` kernel test robot
2025-11-25 12:06 ` kernel test robot
2025-11-24 12:50 ` [PATCH 4/7] dma: mcf-edma: Fix interrupt handler for 64 DMA channels Jean-Michel Hautbois
2025-11-24 16:09 ` Frank Li [this message]
2025-11-25 8:02 ` Jean-Michel Hautbois
2025-11-25 16:14 ` Frank Li
2025-11-24 12:50 ` [PATCH 5/7] dma: fsl-edma: Move error handler out of header file Jean-Michel Hautbois
2025-11-24 16:10 ` Frank Li
2025-11-24 12:50 ` [PATCH 6/7] dma: mcf-edma: Fix error handler for all 64 DMA channels Jean-Michel Hautbois
2025-11-24 16:16 ` Frank Li
2025-11-24 12:50 ` [PATCH 7/7] dma: fsl-edma: Support source stride for interleaved DMA transfers Jean-Michel Hautbois
2025-11-24 16:29 ` Frank Li
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