From: Frank Li <Frank.li@oss.nxp.com>
To: Linus Walleij <linusw@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
dmaengine@vger.kernel.org, phone-devel@vger.kernel.org
Subject: Re: [PATCH v7 21/24] dmaengine: ste_dma40: Fix V4B event group mapping
Date: Wed, 30 Sep 2026 15:36:54 -0400 [thread overview]
Message-ID: <ar1k1jTz4EdBdBfE@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20260927-dma40-fixes-v7-21-89f595e8851d@kernel.org>
On Sun, Sep 27, 2026 at 11:03:34AM +0200, Linus Walleij wrote:
> DMA40 physical resources are connected in pairs to event groups. The
> mapping repeats after each complete set of groups.
>
> D40_GROUP_SIZE and D40_PHYS_TO_GROUP() encode the four-group V4A layout.
> On V4B, which has five groups, resources 8 and 9 are consequently offered
> both to event groups 0 and 4. The GCC clock bookkeeping also treats these
> resources as group 0 instead of group 4.
>
> Derive the physical-resource stride and reverse mapping from the
> variant-specific number of event groups. This preserves the V4A mapping
> and gives V4B a ten-resource stride: resources 8 and 9 belong only to
> group 4, while resources 10 and 11 repeat group 0.
>
> Fixes: 3cb645dc85a0 ("dmaengine: ste_dma40: support more than 128 event lines")
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/dma/ste_dma40.c | 47 ++++++++++++++++++++++++++++++++--------------
> drivers/dma/ste_dma40_ll.h | 2 --
> 2 files changed, 33 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 91dc143f9a80..a5471a9157cd 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -85,6 +85,7 @@ struct stedma40_platform_data {
> /* Number of event groups per hardware register layout */
> #define D40_EVENT_GROUPS_V4A 4
> #define D40_EVENT_GROUPS_V4B 5
> +#define D40_PHYS_PER_EVENT_GROUP 2
>
> /* Max number of logical channels per physical channel */
> #define D40_MAX_LOG_CHAN_PER_PHY 32
> @@ -2027,6 +2028,12 @@ static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
> return is_free;
> }
>
> +static int d40_phy_to_group(struct d40_base *base, int phy)
> +{
> + return (phy / D40_PHYS_PER_EVENT_GROUP) %
> + base->gen_dmac.num_event_groups;
> +}
> +
> static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
> {
> int dev_type = d40c->dma_cfg.dev_type;
> @@ -2037,11 +2044,14 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
> int j;
> int log_num;
> int num_phy_chans;
> + int phy_group_stride;
> bool is_src;
> bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
>
> phys = d40c->base->phy_res;
> num_phy_chans = d40c->base->num_phy_chans;
> + phy_group_stride = D40_PHYS_PER_EVENT_GROUP *
> + d40c->base->gen_dmac.num_event_groups;
>
> if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
> log_num = 2 * dev_type;
> @@ -2075,13 +2085,18 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
> }
> }
> } else
> - for (j = 0; j < d40c->base->num_phy_chans;
> - j += D40_GROUP_SIZE) {
> - int phy_num = j + event_group * 2;
> - if (phy_num + 1 >= num_phy_chans)
> + for (j = 0; j < num_phy_chans;
> + j += phy_group_stride) {
> + int phy_num = j + event_group *
> + D40_PHYS_PER_EVENT_GROUP;
> +
> + if (phy_num + D40_PHYS_PER_EVENT_GROUP >
> + num_phy_chans)
> break;
>
> - for (i = phy_num; i < phy_num + 2; i++) {
> + for (i = phy_num;
> + i < phy_num + D40_PHYS_PER_EVENT_GROUP;
> + i++) {
> if (d40_alloc_mask_set(&phys[i],
> is_src,
> 0,
> @@ -2100,9 +2115,10 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
> return -EINVAL;
>
> /* Find logical channel */
> - for (j = 0; j < d40c->base->num_phy_chans; j += D40_GROUP_SIZE) {
> - int phy_num = j + event_group * 2;
> - if (phy_num + 1 >= num_phy_chans)
> + for (j = 0; j < num_phy_chans; j += phy_group_stride) {
> + int phy_num = j + event_group * D40_PHYS_PER_EVENT_GROUP;
> +
> + if (phy_num + D40_PHYS_PER_EVENT_GROUP > num_phy_chans)
> break;
>
> if (d40c->dma_cfg.use_fixed_channel) {
> @@ -2129,14 +2145,17 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
> * channels.
> */
> if (is_src) {
> - for (i = phy_num; i < phy_num + 2; i++) {
> + for (i = phy_num;
> + i < phy_num + D40_PHYS_PER_EVENT_GROUP;
> + i++) {
> if (d40_alloc_mask_set(&phys[i], is_src,
> event_line, is_log,
> first_phy_user))
> goto found_log;
> }
> } else {
> - for (i = phy_num + 1; i >= phy_num; i--) {
> + for (i = phy_num + D40_PHYS_PER_EVENT_GROUP - 1;
> + i >= phy_num; i--) {
> if (d40_alloc_mask_set(&phys[i], is_src,
> event_line, is_log,
> first_phy_user))
> @@ -3307,9 +3326,9 @@ static int __init d40_phy_res_init(struct d40_base *base)
> base->phy_res[i].allocated_src = D40_ALLOC_PHY;
> base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
> base->phy_res[i].reserved = true;
> - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
> + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, i),
> D40_DREG_GCC_SRC);
> - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
> + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, i),
> D40_DREG_GCC_DST);
>
>
> @@ -3329,9 +3348,9 @@ static int __init d40_phy_res_init(struct d40_base *base)
> base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
> base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
> base->phy_res[chan].reserved = true;
> - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
> + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, chan),
> D40_DREG_GCC_SRC);
> - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
> + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, chan),
> D40_DREG_GCC_DST);
> num_phy_chans_avail--;
> }
> diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
> index 2e30e9a94a1e..55090cb31057 100644
> --- a/drivers/dma/ste_dma40_ll.h
> +++ b/drivers/dma/ste_dma40_ll.h
> @@ -16,8 +16,6 @@
>
> #define D40_TYPE_TO_GROUP(type) (type / 16)
> #define D40_TYPE_TO_EVENT(type) (type % 16)
> -#define D40_GROUP_SIZE 8
> -#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
>
> /* Most bits of the CFG register are the same in log as in phy mode */
> #define D40_SREG_CFG_MST_POS 15
>
> --
> 2.55.0
>
next prev parent reply other threads:[~2026-09-30 19:37 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-27 9:03 [PATCH v7 00/24] dmaengine: ste_dma40: Fix numerous accumulated bugs Linus Walleij
2026-09-27 9:03 ` [PATCH v7 01/24] dmaengine: ste_dma40: Fix physical cyclic capability Linus Walleij
2026-09-27 9:03 ` [PATCH v7 02/24] dmaengine: ste_dma40: Fix cyclic transfer residue Linus Walleij
2026-09-27 9:03 ` [PATCH v7 03/24] dmaengine: ste_dma40: Recover coalesced cyclic callbacks Linus Walleij
2026-09-28 16:48 ` Frank Li
2026-09-27 9:03 ` [PATCH v7 04/24] dmaengine: ste_dma40: Fix failed start cleanup Linus Walleij
2026-09-27 9:03 ` [PATCH v7 05/24] dmaengine: ste_dma40: Fix probe runtime PM disable Linus Walleij
2026-09-27 9:03 ` [PATCH v7 06/24] dmaengine: ste_dma40: Check runtime PM in IRQ Linus Walleij
2026-09-27 9:24 ` sashiko-bot
2026-09-27 17:48 ` Linus Walleij
2026-09-27 9:03 ` [PATCH v7 07/24] dmaengine: ste_dma40: Handle runtime PM resume errors Linus Walleij
2026-09-27 9:03 ` [PATCH v7 08/24] dmaengine: ste_dma40: Return IRQ_NONE when no interrupt is pending Linus Walleij
2026-09-27 9:03 ` [PATCH v7 09/24] dmaengine: ste_dma40: Init hardware before registration Linus Walleij
2026-09-28 16:49 ` Frank Li
2026-09-27 9:03 ` [PATCH v7 10/24] dmaengine: ste_dma40: Fix probe IRQ leak Linus Walleij
2026-09-28 16:50 ` Frank Li
2026-09-27 9:03 ` [PATCH v7 11/24] dmaengine: ste_dma40: Fix DMA registration unwind Linus Walleij
2026-09-28 16:57 ` Frank Li
2026-09-27 9:03 ` [PATCH v7 12/24] dmaengine: ste_dma40: Fix LCLA allocation order Linus Walleij
2026-09-27 9:03 ` [PATCH v7 13/24] dmaengine: ste_dma40: Fix probe LCLA free Linus Walleij
2026-09-27 9:03 ` [PATCH v7 14/24] dmaengine: ste_dma40: Put the LCPA SRAM node Linus Walleij
2026-09-27 9:03 ` [PATCH v7 15/24] dmaengine: ste_dma40: Fix memcpy channel parsing Linus Walleij
2026-09-27 9:03 ` [PATCH v7 16/24] dmaengine: ste_dma40: Validate disabled channel indexes Linus Walleij
2026-09-27 9:03 ` [PATCH v7 17/24] dmaengine: ste_dma40: Validate DMA specifier length Linus Walleij
2026-09-27 9:03 ` [PATCH v7 18/24] dmaengine: ste_dma40: Reject direction changes after allocation Linus Walleij
2026-09-27 9:03 ` [PATCH v7 19/24] dmaengine: ste_dma40: Fix logical channel bounds check Linus Walleij
2026-09-28 16:58 ` Frank Li
2026-09-27 9:03 ` [PATCH v7 20/24] dmaengine: ste_dma40: Fix event group bounds Linus Walleij
2026-09-28 17:00 ` Frank Li
2026-09-27 9:03 ` [PATCH v7 21/24] dmaengine: ste_dma40: Fix V4B event group mapping Linus Walleij
2026-09-30 19:36 ` Frank Li [this message]
2026-09-27 9:03 ` [PATCH v7 22/24] dmaengine: ste_dma40: Search all blocks for fixed logical channels Linus Walleij
2026-10-05 15:39 ` Vinod Koul
2026-10-05 22:26 ` Linus Walleij
2026-09-27 9:03 ` [PATCH v7 23/24] dmaengine: ste_dma40: Validate fixed physical channel indexes Linus Walleij
2026-09-27 9:03 ` [PATCH v7 24/24] dmaengine: ste_dma40: Validate memcpy configuration Linus Walleij
2026-10-05 15:43 ` [PATCH v7 00/24] dmaengine: ste_dma40: Fix numerous accumulated bugs Vinod Koul
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