* [PATCH 0/3] dmaengine: tegra210-adma: Fixes for v5.2
From: Jon Hunter @ 2019-05-16 15:53 UTC (permalink / raw)
To: Laxman Dewangan, Vinod Koul
Cc: dmaengine, linux-tegra, Sameer Pujar, Jon Hunter
Here are 3 fixes for the Tegra210 ADMA driver for v5.2.
Jon Hunter (3):
dmaengine: tegra210-adma: Fix crash during probe
dmaengine: tegra210-adma: Fix channel FIFO configuration
dmaengine: tegra210-adma: Fix spelling
drivers/dma/tegra210-adma.c | 57 ++++++++++++++++++++++++++++-----------------
1 file changed, 36 insertions(+), 21 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH] dmaengine: axi-dmac: Enable TLAST handling
From: Alexandru Ardelean @ 2019-05-16 9:44 UTC (permalink / raw)
To: dmaengine; +Cc: Michael Hennerich, Alexandru Ardelean
From: Michael Hennerich <michael.hennerich@analog.com>
The TLAST flag is used by the DMAC HDL controller to signal to the
controller that the following segment (to be submitted) is the last one (in
a series of segments).
A receiver DMA (typically another DMAC) can read this parameter (from the
transfer), and terminate the transfer earlier. A typical use-case for this,
is when the receiver expects a certain amount of segments, but for some
reason (e.g. an ADC capture which can have an unknown number of digital
samples) the number of actual segments is smaller. The receiver would read
this flag, and then the DMAC would finish.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/dma/dma-axi-dmac.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index f32fdf21edbd..8b6fc21bdb9e 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -71,6 +71,7 @@
#define AXI_DMAC_IRQ_EOT BIT(1)
#define AXI_DMAC_FLAG_CYCLIC BIT(0)
+#define AXI_DMAC_FLAG_LAST BIT(1)
/* The maximum ID allocated by the hardware is 31 */
#define AXI_DMAC_SG_UNUSED 32U
@@ -216,6 +217,7 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
desc->num_submitted = 0; /* Start again */
else
chan->next_desc = NULL;
+ flags |= AXI_DMAC_FLAG_LAST;
} else {
chan->next_desc = desc;
}
--
2.17.1
^ permalink raw reply related
* [PATCH] dmaengine: axi-dmac: Sanity check memory mapped interface support
From: Alexandru Ardelean @ 2019-05-16 8:31 UTC (permalink / raw)
To: dmaengine; +Cc: Lars-Peter Clausen, Alexandru Ardelean
From: Lars-Peter Clausen <lars@metafoo.de>
The AXI-DMAC supports different types of interface for the data source and
destination ports. Typically one of those ports is a memory-mapped
interface while the other is some kind of streaming interface.
The information about which kind of interface is used for each port is
encoded in the devicetree.
It is also possible in the driver to detect whether a port supports
memory-mapped transfers or not. For streaming interfaces the address
register is read-only and will always return 0. So in order to check if a
port supports memory-mapped transfers write a non-zero value to the
corresponding address register and check that the value read-back is still
non zero.
This allows to detect mismatches between the devicetree description and the
actual hardware configuration.
Unfortunately it is not possible to autodetect the interface types since
there is no method to distinguish between the different streaming ports. So
the best thing that can be done is to error out when a memory mapped port
is described in the devicetree but none is detected in the hardware.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/dma/dma-axi-dmac.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index f32fdf21edbd..5710179a401e 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -632,7 +632,7 @@ static int axi_dmac_parse_chan_dt(struct device_node *of_chan,
return 0;
}
-static void axi_dmac_detect_caps(struct axi_dmac *dmac)
+static int axi_dmac_detect_caps(struct axi_dmac *dmac)
{
struct axi_dmac_chan *chan = &dmac->chan;
@@ -648,6 +648,24 @@ static void axi_dmac_detect_caps(struct axi_dmac *dmac)
chan->max_length = axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH);
if (chan->max_length != UINT_MAX)
chan->max_length++;
+
+ axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, 0xffffffff);
+ if (axi_dmac_read(dmac, AXI_DMAC_REG_DEST_ADDRESS) == 0 &&
+ chan->dest_type == AXI_DMAC_BUS_TYPE_AXI_MM) {
+ dev_err(dmac->dma_dev.dev,
+ "Destination memory-mapped interface not supported.");
+ return -ENODEV;
+ }
+
+ axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, 0xffffffff);
+ if (axi_dmac_read(dmac, AXI_DMAC_REG_SRC_ADDRESS) == 0 &&
+ chan->src_type == AXI_DMAC_BUS_TYPE_AXI_MM) {
+ dev_err(dmac->dma_dev.dev,
+ "Source memory-mapped interface not supported.");
+ return -ENODEV;
+ }
+
+ return 0;
}
static int axi_dmac_probe(struct platform_device *pdev)
@@ -723,7 +741,9 @@ static int axi_dmac_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- axi_dmac_detect_caps(dmac);
+ ret = axi_dmac_detect_caps(dmac);
+ if (ret)
+ goto err_clk_disable;
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00);
--
2.17.1
^ permalink raw reply related
* [PATCH] dmaengine: axi-dmac: Add support for interleaved cyclic transfers
From: Alexandru Ardelean @ 2019-05-16 7:04 UTC (permalink / raw)
To: dmaengine; +Cc: Dragos Bogdan, Alexandru Ardelean
From: Dragos Bogdan <dragos.bogdan@analog.com>
The DMAC HDL core supports interleaved & cyclic transfers.
An example use-case for this mode is when the controller is used as a
video DMA.
This change sets the `cyclic` field to true, so that when the IRQ comes and
the `axi_dmac_transfer_done()` callback is called (from the interrupt
handler) the proper `vchan_cyclic_callback()` is called. This way the
DMAEngine framework will process data correctly for interleaved + cyclic
transfers.
This doesn't fix anything. It's an enhancement to the driver.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/dma/dma-axi-dmac.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index f32fdf21edbd..4d2cae0bebb5 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -562,6 +562,9 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(
desc->sg[0].y_len = 1;
}
+ if (flags & DMA_CYCLIC)
+ desc->cyclic = true;
+
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
}
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 4/4] serial: 8250-mtk: modify uart DMA rx
From: Nicolas Boichat @ 2019-05-15 13:48 UTC (permalink / raw)
To: Long Cheng
Cc: Vinod Koul, Randy Dunlap, Rob Herring, Mark Rutland, Ryder Lee,
Sean Wang, Matthias Brugger, Dan Williams, Greg Kroah-Hartman,
Jiri Slaby, Sean Wang, dmaengine, devicetree,
linux-arm Mailing List, moderated list:ARM/Mediatek SoC support,
lkml, linux-serial, srv_heupstream, Yingjoe Chen, YT Shen,
Zhenbao Liu
In-Reply-To: <1556336193-15198-5-git-send-email-long.cheng@mediatek.com>
On Sat, Apr 27, 2019 at 11:36 AM Long Cheng <long.cheng@mediatek.com> wrote:
>
> Modify uart rx and complete for DMA.
I don't know much about the DMA framework, but can you please explain
why you are making the changes in this CL? I see that you are dropping
dma_sync_single_for_device calls, for example, why?
>
> Signed-off-by: Long Cheng <long.cheng@mediatek.com>
> ---
> drivers/tty/serial/8250/8250_mtk.c | 53 ++++++++++++++++--------------------
> 1 file changed, 23 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c
> index c1fdbc0..04081a6 100644
> --- a/drivers/tty/serial/8250/8250_mtk.c
> +++ b/drivers/tty/serial/8250/8250_mtk.c
> @@ -30,7 +30,6 @@
> #define MTK_UART_DMA_EN_TX 0x2
> #define MTK_UART_DMA_EN_RX 0x5
>
> -#define MTK_UART_TX_SIZE UART_XMIT_SIZE
> #define MTK_UART_RX_SIZE 0x8000
> #define MTK_UART_TX_TRIGGER 1
> #define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE
> @@ -64,28 +63,30 @@ static void mtk8250_dma_rx_complete(void *param)
> struct mtk8250_data *data = up->port.private_data;
> struct tty_port *tty_port = &up->port.state->port;
> struct dma_tx_state state;
> + int copied, cnt, tmp;
> unsigned char *ptr;
> - int copied;
>
> - dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
> - dma->rx_size, DMA_FROM_DEVICE);
> + if (data->rx_status == DMA_RX_SHUTDOWN)
> + return;
>
> dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
> + cnt = dma->rx_size - state.residue;
> + tmp = cnt;
I ponder, maybe we should rename cnt to left? (like, how many bytes
are left to transfer, in total) Or maybe "total"
Then maybe rename tmp to cnt.
>
> - if (data->rx_status == DMA_RX_SHUTDOWN)
> - return;
> + if ((data->rx_pos + cnt) > dma->rx_size)
> + tmp = dma->rx_size - data->rx_pos;
Maybe replace this and the line above:
tmp = max_t(int, cnt, dma->rx_size - data->rx_pos);
>
> - if ((data->rx_pos + state.residue) <= dma->rx_size) {
> - ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);
> - copied = tty_insert_flip_string(tty_port, ptr, state.residue);
> - } else {
> - ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);
> - copied = tty_insert_flip_string(tty_port, ptr,
> - dma->rx_size - data->rx_pos);
> + ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);
> + copied = tty_insert_flip_string(tty_port, ptr, tmp);
> + data->rx_pos += tmp;
> +
> + if (cnt > tmp) {
> ptr = (unsigned char *)(dma->rx_buf);
> - copied += tty_insert_flip_string(tty_port, ptr,
> - data->rx_pos + state.residue - dma->rx_size);
> + tmp = cnt - tmp;
> + copied += tty_insert_flip_string(tty_port, ptr, tmp);
> + data->rx_pos = tmp;
> }
> +
> up->port.icount.rx += copied;
>
> tty_flip_buffer_push(tty_port);
> @@ -96,9 +97,7 @@ static void mtk8250_dma_rx_complete(void *param)
> static void mtk8250_rx_dma(struct uart_8250_port *up)
> {
> struct uart_8250_dma *dma = up->dma;
> - struct mtk8250_data *data = up->port.private_data;
> struct dma_async_tx_descriptor *desc;
> - struct dma_tx_state state;
>
> desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
> dma->rx_size, DMA_DEV_TO_MEM,
> @@ -113,12 +112,6 @@ static void mtk8250_rx_dma(struct uart_8250_port *up)
>
> dma->rx_cookie = dmaengine_submit(desc);
>
> - dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
> - data->rx_pos = state.residue;
> -
> - dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
> - dma->rx_size, DMA_FROM_DEVICE);
> -
> dma_async_issue_pending(dma->rxchan);
> }
>
> @@ -131,13 +124,13 @@ static void mtk8250_dma_enable(struct uart_8250_port *up)
> if (data->rx_status != DMA_RX_START)
> return;
>
> - dma->rxconf.direction = DMA_DEV_TO_MEM;
> - dma->rxconf.src_addr_width = dma->rx_size / 1024;
> - dma->rxconf.src_addr = dma->rx_addr;
> + dma->rxconf.direction = DMA_DEV_TO_MEM;
> + dma->rxconf.src_port_window_size = dma->rx_size;
> + dma->rxconf.src_addr = dma->rx_addr;
>
> - dma->txconf.direction = DMA_MEM_TO_DEV;
> - dma->txconf.dst_addr_width = MTK_UART_TX_SIZE / 1024;
> - dma->txconf.dst_addr = dma->tx_addr;
> + dma->txconf.direction = DMA_MEM_TO_DEV;
> + dma->txconf.dst_port_window_size = UART_XMIT_SIZE;
> + dma->txconf.dst_addr = dma->tx_addr;
>
> serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
> UART_FCR_CLEAR_XMIT);
> @@ -217,7 +210,7 @@ static void mtk8250_shutdown(struct uart_port *port)
> * Mediatek UARTs use an extra highspeed register (UART_MTK_HIGHS)
> *
> * We need to recalcualte the quot register, as the claculation depends
> - * on the vaule in the highspeed register.
> + * on the value in the highspeed register.
Since you're doing some cosmetic changes here, you might as well fix
recalcualte => recalculate and claculation => calculation on the line
above.
But technically, this should belong in another patch...
> *
> * Some baudrates are not supported by the chip, so we use the next
> * lower rate supported and update termios c_flag.
> --
> 1.7.9.5
>
^ permalink raw reply
* [PATCH] dmaengine: ti: edma: Enable support for polled (memcpy) completion
From: Peter Ujfalusi @ 2019-05-14 8:09 UTC (permalink / raw)
To: vkoul; +Cc: dan.j.williams, dmaengine, linux-arm-kernel, linux-omap
When a DMA client driver decides that it is not providing callback for
completion of a transfer (and/or does not set the DMA_PREP_INTERRUPT) but
it will poll the status of the transfer (in case of short memcpy for
example) we will not get interrupt for the completion of the transfer and
will not mark the transaction as done.
Check the event registers (ER and EER) and if the channel is inactive then
return wioth DMA_COMPLETE to let the client know that the transfer is
completed.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/ti/edma.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c
index ceabdea40ae0..7501445af069 100644
--- a/drivers/dma/ti/edma.c
+++ b/drivers/dma/ti/edma.c
@@ -1211,8 +1211,9 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
edesc->pset[0].param.opt |= ITCCHEN;
if (nslots == 1) {
- /* Enable transfer complete interrupt */
- edesc->pset[0].param.opt |= TCINTEN;
+ /* Enable transfer complete interrupt if requested */
+ if (tx_flags & DMA_PREP_INTERRUPT)
+ edesc->pset[0].param.opt |= TCINTEN;
} else {
/* Enable transfer complete chaining for the first slot */
edesc->pset[0].param.opt |= TCCHEN;
@@ -1239,7 +1240,9 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
}
edesc->pset[1].param.opt |= ITCCHEN;
- edesc->pset[1].param.opt |= TCINTEN;
+ /* Enable transfer complete interrupt if requested */
+ if (tx_flags & DMA_PREP_INTERRUPT)
+ edesc->pset[1].param.opt |= TCINTEN;
}
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
@@ -1801,6 +1804,20 @@ static enum dma_status edma_tx_status(struct dma_chan *chan,
unsigned long flags;
ret = dma_cookie_status(chan, cookie, txstate);
+
+ if (ret != DMA_COMPLETE && echan->edesc && !echan->edesc->cyclic) {
+ struct edma_cc *ecc = echan->ecc;
+ int channel = EDMA_CHAN_SLOT(echan->ch_num);
+ int j = (channel >> 5);
+ unsigned int mask = BIT(channel & 0x1f);
+ unsigned int sh_er = edma_shadow0_read_array(ecc, SH_ER, j);
+ unsigned int sh_eer = edma_shadow0_read_array(ecc, SH_EER, j);
+
+ /* The channel is no longer active */
+ if (!(sh_er & mask) && !(sh_eer & mask))
+ ret = DMA_COMPLETE;
+ }
+
if (ret == DMA_COMPLETE || !txstate)
return ret;
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* Re: [PATCH v3 08/14] dt-bindings: spi: imx: add new i.mx6ul compatible name
From: Rob Herring @ 2019-05-13 17:26 UTC (permalink / raw)
To: Robin Gong
Cc: robh@kernel.org, broonie@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
vkoul@kernel.org, dan.j.williams@intel.com,
catalin.marinas@arm.com, will.deacon@arm.com,
l.stach@pengutronix.de, dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557249513-4903-9-git-send-email-yibin.gong@nxp.com>
On Tue, 7 May 2019 09:16:25 +0000, Robin Gong wrote:
> ERR009165 fixed from i.mx6ul, add its compatible name.
>
> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
> ---
> Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] dmaengine: rcar-dmac: Update copyright information
From: Simon Horman @ 2019-05-13 12:20 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Geert Uytterhoeven, Niklas Söderlund,
dmaengine@vger.kernel.org, Linux-Renesas, HIROYUKI YOKOYAMA,
Vinod Koul
In-Reply-To: <OSBPR01MB31747DA6369AD1C240972FBBD80C0@OSBPR01MB3174.jpnprd01.prod.outlook.com>
On Fri, May 10, 2019 at 11:03:48AM +0000, Yoshihiro Shimoda wrote:
> Hi Simon-san,
>
> > From: Simon Horman, Sent: Thursday, May 9, 2019 9:55 PM
> >
> <snip>
> > Shimoda-san, can we go further and also:
> >
> > 1. Remove the r8a66597-udc driver, which also seems unused
> > 2. Remove (minimal) sudmac integration from usbhs ?
>
> I think so. I'll do both.
> About the 2, I'll do it when adding RZ/A2 support from Chris-san is applied.
Thanks Shimoda-san,
much appreciated.
^ permalink raw reply
* [PATCH v2] dmaengine: sudmac: remove unused driver
From: Simon Horman @ 2019-05-13 11:39 UTC (permalink / raw)
To: Vinod Koul
Cc: dmaengine, linux-renesas-soc, Magnus Damm, Yoshihiro Shimoda,
Sergei Shtylyov, Simon Horman
SUDMAC driver was introduced in v3.10 but was never integrated for use
by any platform. As it is unused remove it.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
v2
* Update changelog
* Add Shimoda-san's Ack
---
drivers/dma/sh/Kconfig | 6 -
drivers/dma/sh/Makefile | 1 -
drivers/dma/sh/sudmac.c | 414 ------------------------------------------------
include/linux/sudmac.h | 52 ------
4 files changed, 473 deletions(-)
delete mode 100644 drivers/dma/sh/sudmac.c
delete mode 100644 include/linux/sudmac.h
diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
index 4d6b02b3b1f1..54d5d0369d3c 100644
--- a/drivers/dma/sh/Kconfig
+++ b/drivers/dma/sh/Kconfig
@@ -47,9 +47,3 @@ config RENESAS_USB_DMAC
help
This driver supports the USB-DMA controller found in the Renesas
SoCs.
-
-config SUDMAC
- tristate "Renesas SUDMAC support"
- depends on SH_DMAE_BASE
- help
- Enable support for the Renesas SUDMAC controllers.
diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile
index 42110dd57a56..112fbd22bb3f 100644
--- a/drivers/dma/sh/Makefile
+++ b/drivers/dma/sh/Makefile
@@ -15,4 +15,3 @@ obj-$(CONFIG_SH_DMAE) += shdma.o
obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o
obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o
-obj-$(CONFIG_SUDMAC) += sudmac.o
diff --git a/drivers/dma/sh/sudmac.c b/drivers/dma/sh/sudmac.c
deleted file mode 100644
index 30cc3553cb8b..000000000000
--- a/drivers/dma/sh/sudmac.c
+++ /dev/null
@@ -1,414 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Renesas SUDMAC support
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- *
- * based on drivers/dma/sh/shdma.c:
- * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
- * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
- */
-
-#include <linux/dmaengine.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/sudmac.h>
-
-struct sudmac_chan {
- struct shdma_chan shdma_chan;
- void __iomem *base;
- char dev_id[16]; /* unique name per DMAC of channel */
-
- u32 offset; /* for CFG, BA, BBC, CA, CBC, DEN */
- u32 cfg;
- u32 dint_end_bit;
-};
-
-struct sudmac_device {
- struct shdma_dev shdma_dev;
- struct sudmac_pdata *pdata;
- void __iomem *chan_reg;
-};
-
-struct sudmac_regs {
- u32 base_addr;
- u32 base_byte_count;
-};
-
-struct sudmac_desc {
- struct sudmac_regs hw;
- struct shdma_desc shdma_desc;
-};
-
-#define to_chan(schan) container_of(schan, struct sudmac_chan, shdma_chan)
-#define to_desc(sdesc) container_of(sdesc, struct sudmac_desc, shdma_desc)
-#define to_sdev(sc) container_of(sc->shdma_chan.dma_chan.device, \
- struct sudmac_device, shdma_dev.dma_dev)
-
-/* SUDMAC register */
-#define SUDMAC_CH0CFG 0x00
-#define SUDMAC_CH0BA 0x10
-#define SUDMAC_CH0BBC 0x18
-#define SUDMAC_CH0CA 0x20
-#define SUDMAC_CH0CBC 0x28
-#define SUDMAC_CH0DEN 0x30
-#define SUDMAC_DSTSCLR 0x38
-#define SUDMAC_DBUFCTRL 0x3C
-#define SUDMAC_DINTCTRL 0x40
-#define SUDMAC_DINTSTS 0x44
-#define SUDMAC_DINTSTSCLR 0x48
-#define SUDMAC_CH0SHCTRL 0x50
-
-/* Definitions for the sudmac_channel.config */
-#define SUDMAC_SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
-#define SUDMAC_RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
-#define SUDMAC_LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
-
-/* Definitions for the sudmac_channel.dint_end_bit */
-#define SUDMAC_CH1ENDE 0x0002 /* b1: Ch1 DMA Transfer End Int Enable */
-#define SUDMAC_CH0ENDE 0x0001 /* b0: Ch0 DMA Transfer End Int Enable */
-
-#define SUDMAC_DRV_NAME "sudmac"
-
-static void sudmac_writel(struct sudmac_chan *sc, u32 data, u32 reg)
-{
- iowrite32(data, sc->base + reg);
-}
-
-static u32 sudmac_readl(struct sudmac_chan *sc, u32 reg)
-{
- return ioread32(sc->base + reg);
-}
-
-static bool sudmac_is_busy(struct sudmac_chan *sc)
-{
- u32 den = sudmac_readl(sc, SUDMAC_CH0DEN + sc->offset);
-
- if (den)
- return true; /* working */
-
- return false; /* waiting */
-}
-
-static void sudmac_set_reg(struct sudmac_chan *sc, struct sudmac_regs *hw,
- struct shdma_desc *sdesc)
-{
- sudmac_writel(sc, sc->cfg, SUDMAC_CH0CFG + sc->offset);
- sudmac_writel(sc, hw->base_addr, SUDMAC_CH0BA + sc->offset);
- sudmac_writel(sc, hw->base_byte_count, SUDMAC_CH0BBC + sc->offset);
-}
-
-static void sudmac_start(struct sudmac_chan *sc)
-{
- u32 dintctrl = sudmac_readl(sc, SUDMAC_DINTCTRL);
-
- sudmac_writel(sc, dintctrl | sc->dint_end_bit, SUDMAC_DINTCTRL);
- sudmac_writel(sc, 1, SUDMAC_CH0DEN + sc->offset);
-}
-
-static void sudmac_start_xfer(struct shdma_chan *schan,
- struct shdma_desc *sdesc)
-{
- struct sudmac_chan *sc = to_chan(schan);
- struct sudmac_desc *sd = to_desc(sdesc);
-
- sudmac_set_reg(sc, &sd->hw, sdesc);
- sudmac_start(sc);
-}
-
-static bool sudmac_channel_busy(struct shdma_chan *schan)
-{
- struct sudmac_chan *sc = to_chan(schan);
-
- return sudmac_is_busy(sc);
-}
-
-static void sudmac_setup_xfer(struct shdma_chan *schan, int slave_id)
-{
-}
-
-static const struct sudmac_slave_config *sudmac_find_slave(
- struct sudmac_chan *sc, int slave_id)
-{
- struct sudmac_device *sdev = to_sdev(sc);
- struct sudmac_pdata *pdata = sdev->pdata;
- const struct sudmac_slave_config *cfg;
- int i;
-
- for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
- if (cfg->slave_id == slave_id)
- return cfg;
-
- return NULL;
-}
-
-static int sudmac_set_slave(struct shdma_chan *schan, int slave_id,
- dma_addr_t slave_addr, bool try)
-{
- struct sudmac_chan *sc = to_chan(schan);
- const struct sudmac_slave_config *cfg = sudmac_find_slave(sc, slave_id);
-
- if (!cfg)
- return -ENODEV;
-
- return 0;
-}
-
-static inline void sudmac_dma_halt(struct sudmac_chan *sc)
-{
- u32 dintctrl = sudmac_readl(sc, SUDMAC_DINTCTRL);
-
- sudmac_writel(sc, 0, SUDMAC_CH0DEN + sc->offset);
- sudmac_writel(sc, dintctrl & ~sc->dint_end_bit, SUDMAC_DINTCTRL);
- sudmac_writel(sc, sc->dint_end_bit, SUDMAC_DINTSTSCLR);
-}
-
-static int sudmac_desc_setup(struct shdma_chan *schan,
- struct shdma_desc *sdesc,
- dma_addr_t src, dma_addr_t dst, size_t *len)
-{
- struct sudmac_chan *sc = to_chan(schan);
- struct sudmac_desc *sd = to_desc(sdesc);
-
- dev_dbg(sc->shdma_chan.dev, "%s: src=%pad, dst=%pad, len=%zu\n",
- __func__, &src, &dst, *len);
-
- if (*len > schan->max_xfer_len)
- *len = schan->max_xfer_len;
-
- if (dst)
- sd->hw.base_addr = dst;
- else if (src)
- sd->hw.base_addr = src;
- sd->hw.base_byte_count = *len;
-
- return 0;
-}
-
-static void sudmac_halt(struct shdma_chan *schan)
-{
- struct sudmac_chan *sc = to_chan(schan);
-
- sudmac_dma_halt(sc);
-}
-
-static bool sudmac_chan_irq(struct shdma_chan *schan, int irq)
-{
- struct sudmac_chan *sc = to_chan(schan);
- u32 dintsts = sudmac_readl(sc, SUDMAC_DINTSTS);
-
- if (!(dintsts & sc->dint_end_bit))
- return false;
-
- /* DMA stop */
- sudmac_dma_halt(sc);
-
- return true;
-}
-
-static size_t sudmac_get_partial(struct shdma_chan *schan,
- struct shdma_desc *sdesc)
-{
- struct sudmac_chan *sc = to_chan(schan);
- struct sudmac_desc *sd = to_desc(sdesc);
- u32 current_byte_count = sudmac_readl(sc, SUDMAC_CH0CBC + sc->offset);
-
- return sd->hw.base_byte_count - current_byte_count;
-}
-
-static bool sudmac_desc_completed(struct shdma_chan *schan,
- struct shdma_desc *sdesc)
-{
- struct sudmac_chan *sc = to_chan(schan);
- struct sudmac_desc *sd = to_desc(sdesc);
- u32 current_addr = sudmac_readl(sc, SUDMAC_CH0CA + sc->offset);
-
- return sd->hw.base_addr + sd->hw.base_byte_count == current_addr;
-}
-
-static int sudmac_chan_probe(struct sudmac_device *su_dev, int id, int irq,
- unsigned long flags)
-{
- struct shdma_dev *sdev = &su_dev->shdma_dev;
- struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
- struct sudmac_chan *sc;
- struct shdma_chan *schan;
- int err;
-
- sc = devm_kzalloc(&pdev->dev, sizeof(struct sudmac_chan), GFP_KERNEL);
- if (!sc)
- return -ENOMEM;
-
- schan = &sc->shdma_chan;
- schan->max_xfer_len = 64 * 1024 * 1024 - 1;
-
- shdma_chan_probe(sdev, schan, id);
-
- sc->base = su_dev->chan_reg;
-
- /* get platform_data */
- sc->offset = su_dev->pdata->channel->offset;
- if (su_dev->pdata->channel->config & SUDMAC_TX_BUFFER_MODE)
- sc->cfg |= SUDMAC_SENDBUFM;
- if (su_dev->pdata->channel->config & SUDMAC_RX_END_MODE)
- sc->cfg |= SUDMAC_RCVENDM;
- sc->cfg |= (su_dev->pdata->channel->wait << 4) & SUDMAC_LBA_WAIT;
-
- if (su_dev->pdata->channel->dint_end_bit & SUDMAC_DMA_BIT_CH0)
- sc->dint_end_bit |= SUDMAC_CH0ENDE;
- if (su_dev->pdata->channel->dint_end_bit & SUDMAC_DMA_BIT_CH1)
- sc->dint_end_bit |= SUDMAC_CH1ENDE;
-
- /* set up channel irq */
- if (pdev->id >= 0)
- snprintf(sc->dev_id, sizeof(sc->dev_id), "sudmac%d.%d",
- pdev->id, id);
- else
- snprintf(sc->dev_id, sizeof(sc->dev_id), "sudmac%d", id);
-
- err = shdma_request_irq(schan, irq, flags, sc->dev_id);
- if (err) {
- dev_err(sdev->dma_dev.dev,
- "DMA channel %d request_irq failed %d\n", id, err);
- goto err_no_irq;
- }
-
- return 0;
-
-err_no_irq:
- /* remove from dmaengine device node */
- shdma_chan_remove(schan);
- return err;
-}
-
-static void sudmac_chan_remove(struct sudmac_device *su_dev)
-{
- struct shdma_chan *schan;
- int i;
-
- shdma_for_each_chan(schan, &su_dev->shdma_dev, i) {
- BUG_ON(!schan);
-
- shdma_chan_remove(schan);
- }
-}
-
-static dma_addr_t sudmac_slave_addr(struct shdma_chan *schan)
-{
- /* SUDMAC doesn't need the address */
- return 0;
-}
-
-static struct shdma_desc *sudmac_embedded_desc(void *buf, int i)
-{
- return &((struct sudmac_desc *)buf)[i].shdma_desc;
-}
-
-static const struct shdma_ops sudmac_shdma_ops = {
- .desc_completed = sudmac_desc_completed,
- .halt_channel = sudmac_halt,
- .channel_busy = sudmac_channel_busy,
- .slave_addr = sudmac_slave_addr,
- .desc_setup = sudmac_desc_setup,
- .set_slave = sudmac_set_slave,
- .setup_xfer = sudmac_setup_xfer,
- .start_xfer = sudmac_start_xfer,
- .embedded_desc = sudmac_embedded_desc,
- .chan_irq = sudmac_chan_irq,
- .get_partial = sudmac_get_partial,
-};
-
-static int sudmac_probe(struct platform_device *pdev)
-{
- struct sudmac_pdata *pdata = dev_get_platdata(&pdev->dev);
- int err, i;
- struct sudmac_device *su_dev;
- struct dma_device *dma_dev;
- struct resource *chan, *irq_res;
-
- /* get platform data */
- if (!pdata)
- return -ENODEV;
-
- irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!irq_res)
- return -ENODEV;
-
- err = -ENOMEM;
- su_dev = devm_kzalloc(&pdev->dev, sizeof(struct sudmac_device),
- GFP_KERNEL);
- if (!su_dev)
- return err;
-
- dma_dev = &su_dev->shdma_dev.dma_dev;
-
- chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- su_dev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
- if (IS_ERR(su_dev->chan_reg))
- return PTR_ERR(su_dev->chan_reg);
-
- dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
-
- su_dev->shdma_dev.ops = &sudmac_shdma_ops;
- su_dev->shdma_dev.desc_size = sizeof(struct sudmac_desc);
- err = shdma_init(&pdev->dev, &su_dev->shdma_dev, pdata->channel_num);
- if (err < 0)
- return err;
-
- /* platform data */
- su_dev->pdata = dev_get_platdata(&pdev->dev);
-
- platform_set_drvdata(pdev, su_dev);
-
- /* Create DMA Channel */
- for (i = 0; i < pdata->channel_num; i++) {
- err = sudmac_chan_probe(su_dev, i, irq_res->start, IRQF_SHARED);
- if (err)
- goto chan_probe_err;
- }
-
- err = dma_async_device_register(&su_dev->shdma_dev.dma_dev);
- if (err < 0)
- goto chan_probe_err;
-
- return err;
-
-chan_probe_err:
- sudmac_chan_remove(su_dev);
-
- shdma_cleanup(&su_dev->shdma_dev);
-
- return err;
-}
-
-static int sudmac_remove(struct platform_device *pdev)
-{
- struct sudmac_device *su_dev = platform_get_drvdata(pdev);
- struct dma_device *dma_dev = &su_dev->shdma_dev.dma_dev;
-
- dma_async_device_unregister(dma_dev);
- sudmac_chan_remove(su_dev);
- shdma_cleanup(&su_dev->shdma_dev);
-
- return 0;
-}
-
-static struct platform_driver sudmac_driver = {
- .driver = {
- .name = SUDMAC_DRV_NAME,
- },
- .probe = sudmac_probe,
- .remove = sudmac_remove,
-};
-module_platform_driver(sudmac_driver);
-
-MODULE_AUTHOR("Yoshihiro Shimoda");
-MODULE_DESCRIPTION("Renesas SUDMAC driver");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:" SUDMAC_DRV_NAME);
diff --git a/include/linux/sudmac.h b/include/linux/sudmac.h
deleted file mode 100644
index 377b8a5788fa..000000000000
--- a/include/linux/sudmac.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Header for the SUDMAC driver
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- *
- * This is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- */
-#ifndef SUDMAC_H
-#define SUDMAC_H
-
-#include <linux/dmaengine.h>
-#include <linux/shdma-base.h>
-#include <linux/types.h>
-
-/* Used by slave DMA clients to request DMA to/from a specific peripheral */
-struct sudmac_slave {
- struct shdma_slave shdma_slave; /* Set by the platform */
-};
-
-/*
- * Supplied by platforms to specify, how a DMA channel has to be configured for
- * a certain peripheral
- */
-struct sudmac_slave_config {
- int slave_id;
-};
-
-struct sudmac_channel {
- unsigned long offset;
- unsigned long config;
- unsigned long wait; /* The configuable range is 0 to 3 */
- unsigned long dint_end_bit;
-};
-
-struct sudmac_pdata {
- const struct sudmac_slave_config *slave;
- int slave_num;
- const struct sudmac_channel *channel;
- int channel_num;
-};
-
-/* Definitions for the sudmac_channel.config */
-#define SUDMAC_TX_BUFFER_MODE BIT(0)
-#define SUDMAC_RX_END_MODE BIT(1)
-
-/* Definitions for the sudmac_channel.dint_end_bit */
-#define SUDMAC_DMA_BIT_CH0 BIT(0)
-#define SUDMAC_DMA_BIT_CH1 BIT(1)
-
-#endif
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v3 00/14] add ecspi ERR009165 for i.mx6/7 soc family
From: Lucas Stach @ 2019-05-13 9:31 UTC (permalink / raw)
To: Robin Gong, robh@kernel.org, broonie@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com,
mark.rutland@arm.com, u.kleine-koenig@pengutronix.de,
plyatov@gmail.com, vkoul@kernel.org, dan.j.williams@intel.com,
catalin.marinas@arm.com, will.deacon@arm.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, dl-linux-imx, kernel@pengutronix.de,
dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <1557249513-4903-1-git-send-email-yibin.gong@nxp.com>
Hi Robin,
Am Dienstag, den 07.05.2019, 09:15 +0000 schrieb Robin Gong:
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram script which works in XCH mode as PIO inside sdma instead
> of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
> exist on all legacy i.mx6/7 soc family before i.mx6ul.
> NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
> 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
> still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
> for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
> or not.
> The first two reverted patches should be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id is zero.
>
> PS:
> Please get sdma firmware from below linux-firmware and copy it to your
> local rootfs /lib/firmware/imx/sdma.
> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma
This series is unfit for merging, as long as it depends on a SDMA RAM
script that is known to break serial DMA. When can we expect to get a
firmware version with the broken serial script removed out into the
public?
Regards,
Lucas
> v2:
> 1. add commit log for reverted patches.
> 2. add comment for 'ecspi_fixed' in sdma driver.
> 3. add 'fsl,imx6sll-ecspi' compatible instead of 'fsl,imx6ul-ecspi'
> rather than remove.
> v3:
> 1. confirm with design team make sure ERR009165 fixed on i.mx6ul/i.mx6ull
> /i.mx6sll, not fixed on i.mx8m/8mm and other i.mx6/7 legacy chips.
> Correct dts related dts patch in v2.
> 2. clean eratta information in binding doc and new 'tx_glitch_fixed' flag
> in spi-imx driver to state ERR009165 fixed or not.
> 3. Enlarge burst size to fifo size for tx since tx_wml set to 0 in the
> errata workaroud, thus improve performance as possible.
>
> Robin Gong (14):
> Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"
> Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores"
> Revert "dmaengine: imx-sdma: refine to load context only once"
> dmaengine: imx-sdma: remove dupilicated sdma_load_context
> dmaengine: imx-sdma: add mcu_2_ecspi script
> spi: imx: fix ERR009165
> spi: imx: remove ERR009165 workaround on i.mx6ul
> dt-bindings: spi: imx: add new i.mx6ul compatible name
> dmaengine: imx-sdma: remove ERR009165 on i.mx6ul
> dt-bindings: dma: imx-sdma: add i.mx6ul/6sx compatible name
> dmaengine: imx-sdma: fix ecspi1 rx dma not work on i.mx8mm
> ARM: dts: imx6ul: add dma support on ecspi
> ARM: dts: imx6sll: correct sdma compatible
> arm64: defconfig: Enable SDMA on i.mx8mq/8mm
>
> .../devicetree/bindings/dma/fsl-imx-sdma.txt | 2 +
> .../devicetree/bindings/spi/fsl-imx-cspi.txt | 1 +
> arch/arm/boot/dts/imx6q.dtsi | 2 +-
> arch/arm/boot/dts/imx6qdl.dtsi | 8 +--
> arch/arm/boot/dts/imx6sll.dtsi | 2 +-
> arch/arm/boot/dts/imx6ul.dtsi | 8 +++
> arch/arm64/configs/defconfig | 3 +
> drivers/dma/imx-sdma.c | 78 ++++++++++++++++------
> drivers/spi/spi-imx.c | 61 ++++++++++++++---
> include/linux/platform_data/dma-imx-sdma.h | 1 +
> 10 files changed, 132 insertions(+), 34 deletions(-)
>
> --
> 2.7.4
>
^ permalink raw reply
* RE: [PATCH] dmaengine: sudmac: remove unused driver
From: Yoshihiro Shimoda @ 2019-05-13 7:57 UTC (permalink / raw)
To: Simon Horman, Vinod Koul
Cc: dmaengine@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Magnus Damm
In-Reply-To: <20190509125211.324-1-horms+renesas@verge.net.au>
Hi Simon-san,
> From: Simon Horman, Sent: Thursday, May 9, 2019 9:52 PM
>
> SUDMAC driver was introduced in v3.10 but was never integrated for use
> by any platform. As it unused remove it.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Thank you for the patch!
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Best regards,
Yoshihiro Shimoda
^ permalink raw reply
* Re: [PATCH v3 08/14] dt-bindings: spi: imx: add new i.mx6ul compatible name
From: Mark Brown @ 2019-05-12 9:17 UTC (permalink / raw)
To: Robin Gong
Cc: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
vkoul@kernel.org, dan.j.williams@intel.com,
catalin.marinas@arm.com, will.deacon@arm.com,
l.stach@pengutronix.de, dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557249513-4903-9-git-send-email-yibin.gong@nxp.com>
[-- Attachment #1: Type: text/plain, Size: 348 bytes --]
On Tue, May 07, 2019 at 09:16:25AM +0000, Robin Gong wrote:
> ERR009165 fixed from i.mx6ul, add its compatible name.
>
> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Mark Brown <broonie@kernel.org>
Please use subject lines matching the style for the subsystem. This
makes it easier for people to identify relevant patches.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v3 07/14] spi: imx: remove ERR009165 workaround on i.mx6ul
From: Mark Brown @ 2019-05-12 9:17 UTC (permalink / raw)
To: Robin Gong
Cc: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
vkoul@kernel.org, dan.j.williams@intel.com,
catalin.marinas@arm.com, will.deacon@arm.com,
l.stach@pengutronix.de, dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557249513-4903-8-git-send-email-yibin.gong@nxp.com>
[-- Attachment #1: Type: text/plain, Size: 277 bytes --]
On Tue, May 07, 2019 at 09:16:19AM +0000, Robin Gong wrote:
> ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and
> i.mx8m/8mm still need this errata. Please refer to nxp official
> errata document from https://www.nxp.com/ .
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v3 06/14] spi: imx: fix ERR009165
From: Mark Brown @ 2019-05-12 9:16 UTC (permalink / raw)
To: Robin Gong
Cc: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
vkoul@kernel.org, dan.j.williams@intel.com,
catalin.marinas@arm.com, will.deacon@arm.com,
l.stach@pengutronix.de, dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557249513-4903-7-git-send-email-yibin.gong@nxp.com>
[-- Attachment #1: Type: text/plain, Size: 229 bytes --]
On Tue, May 07, 2019 at 09:16:13AM +0000, Robin Gong wrote:
> Change to XCH mode even in dma mode, please refer to the below
> errata:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* RE: [PATCH] dmaengine: rcar-dmac: Update copyright information
From: Yoshihiro Shimoda @ 2019-05-10 11:03 UTC (permalink / raw)
To: Simon Horman
Cc: Geert Uytterhoeven, Niklas Söderlund,
dmaengine@vger.kernel.org, Linux-Renesas, HIROYUKI YOKOYAMA,
Vinod Koul
In-Reply-To: <20190509125528.d7eryp5iv45yn2mp@verge.net.au>
Hi Simon-san,
> From: Simon Horman, Sent: Thursday, May 9, 2019 9:55 PM
>
<snip>
> Shimoda-san, can we go further and also:
>
> 1. Remove the r8a66597-udc driver, which also seems unused
> 2. Remove (minimal) sudmac integration from usbhs ?
I think so. I'll do both.
About the 2, I'll do it when adding RZ/A2 support from Chris-san is applied.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply
* [PATCH v1 4/6] dmaengine: fsl-edma: add i.mx7ulp edma2 version support
From: Robin Gong @ 2019-05-10 10:14 UTC (permalink / raw)
To: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com, vkoul@kernel.org,
dan.j.williams@intel.com
Cc: dl-linux-imx, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557512248-8440-1-git-send-email-yibin.gong@nxp.com>
Add edma2 for i.mx7ulp by version v3, since v2 has already
been used by mcf-edma.
The big changes based on v1 are belows:
1. only one dmamux.
2. another clock dma_clk except dmamux clk.
3. 16 independent interrupts instead of only one interrupt for
all channels.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.c | 18 ++++++++++-
drivers/dma/fsl-edma-common.h | 3 ++
drivers/dma/fsl-edma.c | 69 ++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index bb24251..64e822e 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -90,6 +90,19 @@ static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
iowrite8(val8, addr + off);
}
+void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
+ u32 off, u32 slot, bool enable)
+{
+ u32 val;
+
+ if (enable)
+ val = EDMAMUX_CHCFG_ENBL << 24 | slot;
+ else
+ val = EDMAMUX_CHCFG_DIS;
+
+ iowrite32(val, addr + off * 4);
+}
+
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
unsigned int slot, bool enable)
{
@@ -102,7 +115,10 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
- mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
+ if (fsl_chan->edma->version == v3)
+ mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable);
+ else
+ mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
}
EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 21a9cfd..2b0cc8e 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -124,6 +124,7 @@ struct fsl_edma_chan {
dma_addr_t dma_dev_addr;
u32 dma_dev_size;
enum dma_data_direction dma_dir;
+ char chan_name[16];
};
struct fsl_edma_desc {
@@ -138,6 +139,7 @@ struct fsl_edma_desc {
enum edma_version {
v1, /* 32ch, Vybrid, mpc57x, etc */
v2, /* 64ch Coldfire */
+ v3, /* 32ch, i.mx7ulp */
};
struct fsl_edma_engine {
@@ -145,6 +147,7 @@ struct fsl_edma_engine {
void __iomem *membase;
void __iomem *muxbase[DMAMUX_NR];
struct clk *muxclk[DMAMUX_NR];
+ struct clk *dmaclk;
u32 dmamux_nr;
struct mutex fsl_edma_mutex;
u32 n_chans;
diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c
index 7b65ef4..1568070 100644
--- a/drivers/dma/fsl-edma.c
+++ b/drivers/dma/fsl-edma.c
@@ -165,6 +165,51 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma
return 0;
}
+static int
+fsl_edma2_irq_init(struct platform_device *pdev,
+ struct fsl_edma_engine *fsl_edma)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int i, ret, irq;
+ int count = 0;
+
+ count = of_irq_count(np);
+ dev_info(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
+ if (count <= 2) {
+ dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
+ return -EINVAL;
+ }
+ /*
+ * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
+ * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
+ * For now, just simply request irq without IRQF_SHARED flag, since 16
+ * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
+ */
+ for (i = 0; i < count; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ return -ENXIO;
+
+ sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
+
+ /* The last IRQ is for eDMA err */
+ if (i == count - 1)
+ ret = devm_request_irq(&pdev->dev, irq,
+ fsl_edma_err_handler,
+ 0, "eDMA2-ERR", fsl_edma);
+ else
+
+ ret = devm_request_irq(&pdev->dev, irq,
+ fsl_edma_tx_handler, 0,
+ fsl_edma->chans[i].chan_name,
+ fsl_edma);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static void fsl_edma_irq_exit(
struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
{
@@ -218,6 +263,23 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_edma_setup_regs(fsl_edma);
regs = &fsl_edma->regs;
+ if (of_device_is_compatible(np, "fsl,imx7ulp-edma")) {
+ fsl_edma->dmamux_nr = 1;
+ fsl_edma->version = v3;
+
+ fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
+ if (IS_ERR(fsl_edma->dmaclk)) {
+ dev_err(&pdev->dev, "Missing DMA block clock.\n");
+ return PTR_ERR(fsl_edma->dmaclk);
+ }
+
+ ret = clk_prepare_enable(fsl_edma->dmaclk);
+ if (ret) {
+ dev_err(&pdev->dev, "DMA clk block failed.\n");
+ return ret;
+ }
+ }
+
for (i = 0; i < fsl_edma->dmamux_nr; i++) {
char clkname[32];
@@ -264,7 +326,11 @@ static int fsl_edma_probe(struct platform_device *pdev)
}
edma_writel(fsl_edma, ~0, regs->intl);
- ret = fsl_edma_irq_init(pdev, fsl_edma);
+
+ if (fsl_edma->version == v3)
+ ret = fsl_edma2_irq_init(pdev, fsl_edma);
+ else
+ ret = fsl_edma_irq_init(pdev, fsl_edma);
if (ret)
return ret;
@@ -385,6 +451,7 @@ static const struct dev_pm_ops fsl_edma_pm_ops = {
static const struct of_device_id fsl_edma_dt_ids[] = {
{ .compatible = "fsl,vf610-edma", },
+ { .compatible = "fsl,imx7ulp-edma", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
--
2.7.4
^ permalink raw reply related
* [PATCH v1 6/6] ARM: dts: imx7ulp: add edma device node
From: Robin Gong @ 2019-05-10 10:14 UTC (permalink / raw)
To: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com, vkoul@kernel.org,
dan.j.williams@intel.com
Cc: dl-linux-imx, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557512248-8440-1-git-send-email-yibin.gong@nxp.com>
Add edma device node in dts.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm/boot/dts/imx7ulp.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index d6b7110..b4f7adf 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -100,6 +100,34 @@
reg = <0x40000000 0x800000>;
ranges;
+ edma1: dma-controller@40080000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x40080000 0x2000>,
+ <0x40210000 0x1000>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
+ <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
+ };
+
lpuart4: serial@402d0000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x402d0000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH v1 5/6] dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma
From: Robin Gong @ 2019-05-10 10:14 UTC (permalink / raw)
To: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com, vkoul@kernel.org,
dan.j.williams@intel.com
Cc: dl-linux-imx, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557512248-8440-1-git-send-email-yibin.gong@nxp.com>
More channel interrupts, one more clock, and only one
dmamux on i.mx7ulp-edma.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
Documentation/devicetree/bindings/dma/fsl-edma.txt | 44 +++++++++++++++++++---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt
index 97e213e..29dd3cc 100644
--- a/Documentation/devicetree/bindings/dma/fsl-edma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt
@@ -9,15 +9,16 @@ group, DMAMUX0 or DMAMUX1, but not both.
Required properties:
- compatible :
- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
+ - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
- reg : Specifies base physical address(s) and size of the eDMA registers.
The 1st region is eDMA control register's address and size.
The 2nd and the 3rd regions are programmable channel multiplexing
control register's address and size.
- interrupts : A list of interrupt-specifiers, one for each entry in
- interrupt-names.
-- interrupt-names : Should contain:
- "edma-tx" - the transmission interrupt
- "edma-err" - the error interrupt
+ interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
+ per transmission interrupt, total 16 channel interrupt and 1
+ error interrupt(located in the last), no interrupt-names list on
+ i.mx7ulp for clean on dts.
- #dma-cells : Must be <2>.
The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
Specific request source can only be multiplexed by specific channels
@@ -28,6 +29,7 @@ Required properties:
- clock-names : A list of channel group clock names. Should contain:
"dmamux0" - clock name of mux0 group
"dmamux1" - clock name of mux1 group
+ Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp.
- clocks : A list of phandle and clock-specifier pairs, one for each entry in
clock-names.
@@ -35,6 +37,10 @@ Optional properties:
- big-endian: If present registers and hardware scatter/gather descriptors
of the eDMA are implemented in big endian mode, otherwise in little
mode.
+- interrupt-names : Should contain the below on vf610 similar SoC but not used
+ on i.mx7ulp similar SoC:
+ "edma-tx" - the transmission interrupt
+ "edma-err" - the error interrupt
Examples:
@@ -52,8 +58,36 @@ edma0: dma-controller@40018000 {
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
-};
+}; /* vf610 */
+edma1: dma-controller@40080000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x40080000 0x2000>,
+ <0x40210000 0x1000>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ /* last is eDMA2-ERR interrupt */
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
+ <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
+}; /* i.mx7ulp */
* DMA clients
DMA client drivers that uses the DMA function must use the format described
--
2.7.4
^ permalink raw reply related
* [PATCH v1 3/6] dmaengine: fsl-edma-common: move dmamux register to another single function
From: Robin Gong @ 2019-05-10 10:14 UTC (permalink / raw)
To: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com, vkoul@kernel.org,
dan.j.williams@intel.com
Cc: dl-linux-imx, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557512248-8440-1-git-send-email-yibin.gong@nxp.com>
Prepare for edmav2 on i.mx7ulp whose dmamux register is 32bit. No function
impacted.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index c9a17fc..bb24251 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -77,6 +77,19 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
+static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
+ u32 off, u32 slot, bool enable)
+{
+ u8 val8;
+
+ if (enable)
+ val8 = EDMAMUX_CHCFG_ENBL | slot;
+ else
+ val8 = EDMAMUX_CHCFG_DIS;
+
+ iowrite8(val8, addr + off);
+}
+
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
unsigned int slot, bool enable)
{
@@ -89,10 +102,7 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
- if (enable)
- iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off);
- else
- iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off);
+ mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
}
EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
--
2.7.4
^ permalink raw reply related
* [PATCH v1 2/6] dmaengine: mcf-edma: update to 'dmamux_nr'
From: Robin Gong @ 2019-05-10 10:14 UTC (permalink / raw)
To: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com, vkoul@kernel.org,
dan.j.williams@intel.com
Cc: dl-linux-imx, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557512248-8440-1-git-send-email-yibin.gong@nxp.com>
Update to 'dmamux_nr' instead of static macro DMAMUX_NR since
new version edma only has one dmamux.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.c | 2 +-
drivers/dma/mcf-edma.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 680b2a0..c9a17fc 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -84,7 +84,7 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
void __iomem *muxaddr;
unsigned int chans_per_mux, ch_off;
- chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
+ chans_per_mux = fsl_chan->edma->n_chans / fsl_chan->edma->dmamux_nr;
ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
index 7de54b2f..4484190 100644
--- a/drivers/dma/mcf-edma.c
+++ b/drivers/dma/mcf-edma.c
@@ -189,6 +189,7 @@ static int mcf_edma_probe(struct platform_device *pdev)
/* Set up version for ColdFire edma */
mcf_edma->version = v2;
+ mcf_edma->dmamux_nr = DMAMUX_NR;
mcf_edma->big_endian = 1;
if (!mcf_edma->n_chans) {
--
2.7.4
^ permalink raw reply related
* [PATCH v1 1/6] dmaengine: fsl-edma: add dmamux_nr for next version
From: Robin Gong @ 2019-05-10 10:14 UTC (permalink / raw)
To: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com, vkoul@kernel.org,
dan.j.williams@intel.com
Cc: dl-linux-imx, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1557512248-8440-1-git-send-email-yibin.gong@nxp.com>
Next version of edma such as edmav2 on i.mx7ulp has only one dmamux.
Add dmamux_nr instead of static macro define 'DMAMUX_NR'. No any
function change here.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.h | 1 +
drivers/dma/fsl-edma.c | 11 ++++++-----
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index c53f76e..21a9cfd 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -145,6 +145,7 @@ struct fsl_edma_engine {
void __iomem *membase;
void __iomem *muxbase[DMAMUX_NR];
struct clk *muxclk[DMAMUX_NR];
+ u32 dmamux_nr;
struct mutex fsl_edma_mutex;
u32 n_chans;
int txirq;
diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c
index d641ef8..7b65ef4 100644
--- a/drivers/dma/fsl-edma.c
+++ b/drivers/dma/fsl-edma.c
@@ -96,7 +96,7 @@ static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
struct dma_chan *chan, *_chan;
struct fsl_edma_chan *fsl_chan;
- unsigned long chans_per_mux = fsl_edma->n_chans / DMAMUX_NR;
+ unsigned long chans_per_mux = fsl_edma->n_chans / fsl_edma->dmamux_nr;
if (dma_spec->args_count != 2)
return NULL;
@@ -206,6 +206,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
return -ENOMEM;
fsl_edma->version = v1;
+ fsl_edma->dmamux_nr = DMAMUX_NR;
fsl_edma->n_chans = chans;
mutex_init(&fsl_edma->fsl_edma_mutex);
@@ -217,7 +218,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_edma_setup_regs(fsl_edma);
regs = &fsl_edma->regs;
- for (i = 0; i < DMAMUX_NR; i++) {
+ for (i = 0; i < fsl_edma->dmamux_nr; i++) {
char clkname[32];
res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
@@ -295,7 +296,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
if (ret) {
dev_err(&pdev->dev,
"Can't register Freescale eDMA engine. (%d)\n", ret);
- fsl_disable_clocks(fsl_edma, DMAMUX_NR);
+ fsl_disable_clocks(fsl_edma, fsl_edma->dmamux_nr);
return ret;
}
@@ -304,7 +305,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
dev_err(&pdev->dev,
"Can't register Freescale eDMA of_dma. (%d)\n", ret);
dma_async_device_unregister(&fsl_edma->dma_dev);
- fsl_disable_clocks(fsl_edma, DMAMUX_NR);
+ fsl_disable_clocks(fsl_edma, fsl_edma->dmamux_nr);
return ret;
}
@@ -323,7 +324,7 @@ static int fsl_edma_remove(struct platform_device *pdev)
fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
of_dma_controller_free(np);
dma_async_device_unregister(&fsl_edma->dma_dev);
- fsl_disable_clocks(fsl_edma, DMAMUX_NR);
+ fsl_disable_clocks(fsl_edma, fsl_edma->dmamux_nr);
return 0;
}
--
2.7.4
^ permalink raw reply related
* [PATCH v1 0/6] add edma2 for i.mx7ulp
From: Robin Gong @ 2019-05-10 10:14 UTC (permalink / raw)
To: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, mark.rutland@arm.com, vkoul@kernel.org,
dan.j.williams@intel.com
Cc: dl-linux-imx, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
This patch set add new version of edma for i.mx7ulp, the main changes
are as belows:
1. only one dmamux.
2. another clock dma_clk except dmamux clk.
3. 16 independent interrupts instead of only one interrupt for
all channels.
For the first change, need modify fsl-edma-common.c and mcf-edma,
so create the first two patches to prepare without any function
impact.
For the third change, need request single irq for every channel with
the legacy handler. But actually 2 dma channels share one interrupt(16
channel interrupts, but 32 channels.),ch0/ch16,ch1/ch17... For now, just
simply request irq without IRQF_SHARED flag, since 16 channels are enough
on i.mx7ulp whose M4 domain own some peripherals.
Robin Gong (6):
dmaengine: fsl-edma: add dmamux_nr for next version
dmaengine: mcf-edma: update to 'dmamux_nr'
dmaengine: fsl-edma-common: move dmamux register to another single
function
dmaengine: fsl-edma: add i.mx7ulp edma2 version support
dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma
ARM: dts: imx7ulp: add edma device node
Documentation/devicetree/bindings/dma/fsl-edma.txt | 44 ++++++++++--
arch/arm/boot/dts/imx7ulp.dtsi | 28 ++++++++
drivers/dma/fsl-edma-common.c | 34 +++++++--
drivers/dma/fsl-edma-common.h | 4 ++
drivers/dma/fsl-edma.c | 80 ++++++++++++++++++++--
drivers/dma/mcf-edma.c | 1 +
6 files changed, 176 insertions(+), 15 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH] dmaengine: ioatdma: fix unprotected timer deletion
From: Dave Jiang @ 2019-05-09 23:37 UTC (permalink / raw)
To: vkoul; +Cc: dmaengine, dan.j.williams, fan.du
When ioat_free_chan_resources() gets called, ioat_stop() is called without
chan->cleanup_lock. ioat_stop modifies IOAT_RUN bit. It needs to be
protected by cleanup_lock. Also, in the __cleanup() path, if IOAT_RUN is
cleared, we should not touch the timer again. We observed that the timer
routine was run after timer was deleted.
Fixes: 3372de5813e ("dmaengine: ioatdma: removal of dma_v3.c and relevant ioat3
references")
Reported-by: Fan Du <fan.du@intel.com>
Tested-by: Fan Du <fan.du@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/dma/ioat/dma.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index f373a139e0c3..78598ba5c73b 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -138,11 +138,14 @@ void ioat_stop(struct ioatdma_chan *ioat_chan)
struct pci_dev *pdev = ioat_dma->pdev;
int chan_id = chan_num(ioat_chan);
struct msix_entry *msix;
+ unsigned long flags;
- /* 1/ stop irq from firing tasklets
- * 2/ stop the tasklet from re-arming irqs
- */
+ spin_lock_irqsave(&ioat_chan->cleanup_lock, flags);
clear_bit(IOAT_RUN, &ioat_chan->state);
+ spin_unlock_irqrestore(&ioat_chan->cleanup_lock, flags);
+
+ /* flush inflight timers */
+ del_timer_sync(&ioat_chan->timer);
/* flush inflight interrupts */
switch (ioat_dma->irq_mode) {
@@ -158,9 +161,6 @@ void ioat_stop(struct ioatdma_chan *ioat_chan)
break;
}
- /* flush inflight timers */
- del_timer_sync(&ioat_chan->timer);
-
/* flush inflight tasklet runs */
tasklet_kill(&ioat_chan->cleanup_task);
@@ -652,7 +652,9 @@ static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete)
if (active - i == 0) {
dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n",
__func__);
- mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
+
+ if (test_bit(IOAT_RUN, &ioat_chan->state))
+ mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
}
/* microsecond delay by sysfs variable per pending descriptor */
^ permalink raw reply related
* Re: [GIT PULL]: dmaengine updates for v5.2-rc1
From: pr-tracker-bot @ 2019-05-09 16:25 UTC (permalink / raw)
To: Vinod Koul; +Cc: Linus Torvalds, dma, LKML
In-Reply-To: <20190509074615.GB16052@vkoul-mobl>
The pull request you sent on Thu, 9 May 2019 13:16:15 +0530:
> git://git.infradead.org/users/vkoul/slave-dma.git tags/dmaengine-5.2-rc1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/055128ee008b00fba14e3638e7e84fc2cff8d77d
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.wiki.kernel.org/userdoc/prtracker
^ permalink raw reply
* Re: [PATCH] dmaengine: sudmac: remove unused driver
From: Sergei Shtylyov @ 2019-05-09 16:20 UTC (permalink / raw)
To: Simon Horman, Vinod Koul
Cc: dmaengine, linux-renesas-soc, Magnus Damm, Yoshihiro Shimoda
In-Reply-To: <20190509125211.324-1-horms+renesas@verge.net.au>
On 05/09/2019 03:52 PM, Simon Horman wrote:
> SUDMAC driver was introduced in v3.10 but was never integrated for use
> by any platform. As it unused remove it.
"It's unused" perhaps? :-)
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[...]
MBR, Sergei
^ permalink raw reply
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