* [PATCH] net/bnxt: enable Tx completion coalescing in hardware
@ 2026-09-21 2:57 Mohammad Shuab Siddique
2026-09-21 15:52 ` Stephen Hemminger
2026-09-29 0:23 ` [PATCH v2] " Mohammad Shuab Siddique
0 siblings, 2 replies; 3+ messages in thread
From: Mohammad Shuab Siddique @ 2026-09-21 2:57 UTC (permalink / raw)
To: dev; +Cc: kishore.padmanabha, Mohammad Shuab Siddique, Ajit Khaparde
From: Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com>
P7 devices support Tx completion coalescing in hardware: the driver
can program the Tx coalescing parameters during Tx ring allocation
instead of always disabling it. Use the wthresh config option
provided in ethdev to select the coalescing value for the Tx rings.
A value of 0 disables the feature. A value of 254 for wthresh is the
max allowable setting; the driver converts the provided value to the
nearest power of 2 for the hardware setting (1 rounds up to 2, which
maps to the same COAL_4 setting as an exact 4; 254 rounds up to 256).
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com>
---
drivers/net/bnxt/bnxt_hwrm.c | 51 ++++++++++++++++++++++++---
drivers/net/bnxt/bnxt_hwrm.h | 3 +-
drivers/net/bnxt/bnxt_mpc.c | 2 +-
drivers/net/bnxt/bnxt_ring.c | 12 +++----
drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 12 ++++++-
drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 13 +++++--
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 14 ++++++--
drivers/net/bnxt/bnxt_txq.c | 1 +
drivers/net/bnxt/bnxt_txr.c | 1 -
9 files changed, 91 insertions(+), 18 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 1615b36aae..71a9730b5e 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1113,7 +1113,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
int rc = 0;
struct hwrm_func_qcaps_input req = {.req_type = 0 };
struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
- uint32_t flags, flags_ext2, flags_ext3;
+ uint32_t flags, flags_ext, flags_ext2, flags_ext3;
uint16_t new_max_vfs;
HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
@@ -1126,6 +1126,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
flags = rte_le_to_cpu_32(resp->flags);
+ flags_ext = rte_le_to_cpu_32(resp->flags_ext);
flags_ext2 = rte_le_to_cpu_32(resp->flags_ext2);
flags_ext3 = rte_le_to_cpu_32(resp->flags_ext3);
@@ -1215,6 +1216,8 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
PMD_DRV_LOG_LINE(DEBUG, "VLAN acceleration for TX is enabled");
}
+ if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP)
+ bp->fw_cap |= BNXT_FW_CAP_TX_COAL_CMPL;
bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
if (bp->tunnel_disable_flag)
@@ -2171,11 +2174,52 @@ mpc_chnl_types[] = {HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE,
HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA,
HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE};
+static uint8_t bnxt_get_cmpl_coal(uint16_t wthresh)
+{
+ uint8_t coal;
+ uint16_t th;
+
+ th = rte_align32pow2(wthresh);
+ if (wthresh == 1)
+ th = 2;
+
+ switch (th) {
+ case 2:
+ /* FALLTHROUGH */
+ case 4:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4;
+ break;
+ case 8:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8;
+ break;
+ case 16:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16;
+ break;
+ case 32:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32;
+ break;
+ case 64:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64;
+ break;
+ case 128:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128;
+ break;
+ case 256:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256;
+ break;
+ case 0:
+ default:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF;
+ }
+ return coal;
+}
+
int bnxt_hwrm_ring_alloc(struct bnxt *bp,
struct bnxt_ring *ring,
uint32_t ring_type, uint32_t map_index,
uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
- uint16_t tx_cosq_id, uint16_t dpi)
+ uint16_t tx_cosq_id, uint16_t dpi,
+ uint16_t tx_coal_thresh)
{
int rc = 0;
uint32_t enables = 0;
@@ -2198,8 +2242,7 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp,
req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
if (bp->fw_cap & BNXT_FW_CAP_TX_COAL_CMPL)
- req.cmpl_coal_cnt =
- HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF;
+ req.cmpl_coal_cnt = bnxt_get_cmpl_coal(tx_coal_thresh);
if (tx_cosq_id != MPC_HW_COS_ID) {
req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
} else {
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index 3034803023..1dd6671046 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -221,7 +221,8 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp,
struct bnxt_ring *ring,
uint32_t ring_type, uint32_t map_index,
uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
- uint16_t tx_cosq_id, uint16_t dpi);
+ uint16_t tx_cosq_id, uint16_t dpi,
+ uint16_t tx_coal_thresh);
int bnxt_hwrm_ring_free(struct bnxt *bp,
struct bnxt_ring *ring, uint32_t ring_type,
uint16_t cp_ring_id);
diff --git a/drivers/net/bnxt/bnxt_mpc.c b/drivers/net/bnxt/bnxt_mpc.c
index d77f9dd308..a7138f0aca 100644
--- a/drivers/net/bnxt/bnxt_mpc.c
+++ b/drivers/net/bnxt/bnxt_mpc.c
@@ -502,7 +502,7 @@ static int bnxt_mpc_ring_alloc_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id)
map_index,
cpr->hw_stats_ctx_id,
cp_ring->fw_ring_id,
- MPC_HW_COS_ID, BNXT_PRIVILEGED_DPI);
+ MPC_HW_COS_ID, BNXT_PRIVILEGED_DPI, 0);
if (rc) {
PMD_DRV_LOG_LINE(ERR, "mpc ring %d tx ring alloc failed rc:%d!",
chnl_id, rc);
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index 064520aa62..d478c60a1e 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -434,7 +434,7 @@ int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
cpr->dpi = dpi;
rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, cp_ring_index,
- HWRM_NA_SIGNATURE, nq_ring_id, 0, dpi);
+ HWRM_NA_SIGNATURE, nq_ring_id, 0, dpi, 0);
if (rc)
return rc;
@@ -505,7 +505,7 @@ int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp)
nqr->dpi = dpi;
rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, ring_index,
- HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0, dpi);
+ HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0, dpi, 0);
if (rc) {
rte_free(ring);
rte_free(nqr);
@@ -555,7 +555,7 @@ static int bnxt_alloc_rx_ring(struct bnxt *bp, int queue_index)
rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type,
queue_index, cpr->hw_stats_ctx_id,
- cp_ring->fw_ring_id, 0, dpi);
+ cp_ring->fw_ring_id, 0, dpi, 0);
if (rc)
return rc;
@@ -595,7 +595,7 @@ static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index)
rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, map_idx,
hw_stats_ctx_id, cp_ring->fw_ring_id, 0,
- BNXT_PRIVILEGED_DPI);
+ BNXT_PRIVILEGED_DPI, 0);
if (rc)
return rc;
@@ -833,7 +833,7 @@ int bnxt_alloc_async_cp_ring(struct bnxt *bp)
rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, 0,
HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0,
- BNXT_PRIVILEGED_DPI);
+ BNXT_PRIVILEGED_DPI, 0);
if (rc)
return rc;
@@ -944,7 +944,7 @@ int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index)
HWRM_RING_ALLOC_INPUT_RING_TYPE_TX,
queue_index, cpr->hw_stats_ctx_id,
cp_ring->fw_ring_id,
- tx_cosq_id, txr->dpi);
+ tx_cosq_id, txr->dpi, txq->wthresh);
if (rc)
goto err_out;
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
index 7f07b0a3e1..2dfb7f0ae0 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
@@ -735,7 +735,9 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
uint32_t ring_mask = cp_ring_struct->ring_mask;
+ uint32_t tx_ring_mask;
+ tx_ring_mask = txq->tx_ring->tx_ring_struct->ring_mask;
do {
cons = RING_CMPL(ring_mask, raw_cons);
txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
@@ -749,7 +751,15 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
rte_atomic_fetch_add_explicit(&txq->tx_dma_err, 1,
rte_memory_order_relaxed);
- nb_tx_pkts += txcmp->opaque;
+ if (CMP_TYPE(txcmp) == CMPL_BASE_TYPE_TX_L2_COAL) {
+ struct tx_cmpl_coal *txcmp_c = (struct tx_cmpl_coal *)txcmp;
+
+ nb_tx_pkts = (rte_le_to_cpu_32(txcmp_c->sq_cons_idx) -
+ (txq->tx_ring->tx_raw_cons & tx_ring_mask)) &
+ tx_ring_mask;
+ } else {
+ nb_tx_pkts += txcmp->opaque;
+ }
raw_cons = NEXT_RAW_CMP(raw_cons);
} while (nb_tx_pkts < ring_mask);
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
index 03f39280e5..ffbcc92dc5 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
@@ -347,7 +347,9 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
uint32_t ring_mask = cp_ring_struct->ring_mask;
+ uint32_t tx_ring_mask;
+ tx_ring_mask = txq->tx_ring->tx_ring_struct->ring_mask;
do {
cons = RING_CMPL(ring_mask, raw_cons);
txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
@@ -355,12 +357,19 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
break;
- if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ if (CMP_TYPE(txcmp) == CMPL_BASE_TYPE_TX_L2_COAL) {
+ struct tx_cmpl_coal *txcmp_c = (struct tx_cmpl_coal *)txcmp;
+
+ nb_tx_pkts = (rte_le_to_cpu_32(txcmp_c->sq_cons_idx) -
+ (txq->tx_ring->tx_raw_cons & tx_ring_mask)) &
+ tx_ring_mask;
+ } else if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)) {
nb_tx_pkts += txcmp->opaque;
- else
+ } else {
RTE_LOG_DP_LINE(ERR, BNXT,
"Unhandled CMP type %02x",
CMP_TYPE(txcmp));
+ }
raw_cons = NEXT_RAW_CMP(raw_cons);
} while (nb_tx_pkts < ring_mask);
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
index a97ff6f5fe..9312d41ef8 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -569,6 +569,9 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
uint32_t ring_mask = cp_ring_struct->ring_mask;
+ uint32_t tx_ring_mask;
+
+ tx_ring_mask = txq->tx_ring->tx_ring_struct->ring_mask;
do {
cons = RING_CMPL(ring_mask, raw_cons);
@@ -583,12 +586,19 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
rte_atomic_fetch_add_explicit(&txq->tx_dma_err, 1,
rte_memory_order_relaxed);
- if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ if (CMP_TYPE(txcmp) == CMPL_BASE_TYPE_TX_L2_COAL) {
+ struct tx_cmpl_coal *txcmp_c = (struct tx_cmpl_coal *)txcmp;
+
+ nb_tx_pkts = (rte_le_to_cpu_32(txcmp_c->sq_cons_idx) -
+ (txq->tx_ring->tx_raw_cons & tx_ring_mask)) &
+ tx_ring_mask;
+ } else if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)) {
nb_tx_pkts += txcmp->opaque;
- else
+ } else {
RTE_LOG_DP_LINE(ERR, BNXT,
"Unhandled CMP type %02x",
CMP_TYPE(txcmp));
+ }
raw_cons = NEXT_RAW_CMP(raw_cons);
} while (nb_tx_pkts < ring_mask);
diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c
index 03407c556a..830298bd5e 100644
--- a/drivers/net/bnxt/bnxt_txq.c
+++ b/drivers/net/bnxt/bnxt_txq.c
@@ -175,6 +175,7 @@ int bnxt_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
/* For PTP packets, process the completion sooner */
if (bp->ptp_cfg != NULL)
txq->tx_free_thresh = RTE_BNXT_MIN_TX_BURST;
+ txq->wthresh = tx_conf->tx_thresh.wthresh;
txq->offloads = eth_dev->data->dev_conf.txmode.offloads |
tx_conf->offloads;
/* mbuf fast free not supported for the following. Reset the bit */
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index edd99dc84a..54daeef3e1 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -740,7 +740,6 @@ static void bnxt_tx_cmp(struct bnxt_tx_queue *txq, int nb_tx, bool tx_coal_cmp)
static bool bnxt_is_tx_cmpl_type(uint16_t type)
{
return (type == CMPL_BASE_TYPE_TX_L2_PKT_TS ||
- type == CMPL_BASE_TYPE_TX_L2_COAL ||
type == CMPL_BASE_TYPE_TX_L2);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] net/bnxt: enable Tx completion coalescing in hardware
2026-09-21 2:57 [PATCH] net/bnxt: enable Tx completion coalescing in hardware Mohammad Shuab Siddique
@ 2026-09-21 15:52 ` Stephen Hemminger
2026-09-29 0:23 ` [PATCH v2] " Mohammad Shuab Siddique
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Hemminger @ 2026-09-21 15:52 UTC (permalink / raw)
To: Mohammad Shuab Siddique; +Cc: dev, kishore.padmanabha, Ajit Khaparde
On Sun, 20 Sep 2026 20:57:55 -0600
Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com> wrote:
> From: Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com>
>
> P7 devices support Tx completion coalescing in hardware: the driver
> can program the Tx coalescing parameters during Tx ring allocation
> instead of always disabling it. Use the wthresh config option
> provided in ethdev to select the coalescing value for the Tx rings.
>
> A value of 0 disables the feature. A value of 254 for wthresh is the
> max allowable setting; the driver converts the provided value to the
> nearest power of 2 for the hardware setting (1 rounds up to 2, which
> maps to the same COAL_4 setting as an exact 4; 254 rounds up to 256).
>
> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> Signed-off-by: Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com>
> ---
[PATCH] net/bnxt: enable Tx completion coalescing in hardware
Error: does not apply to main without fuzz (see summary).
Warning: this adds user-visible behaviour keyed off
tx_thresh.wthresh. It needs a doc/guides/nics/bnxt.rst entry and a
release note.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2] net/bnxt: enable Tx completion coalescing in hardware
2026-09-21 2:57 [PATCH] net/bnxt: enable Tx completion coalescing in hardware Mohammad Shuab Siddique
2026-09-21 15:52 ` Stephen Hemminger
@ 2026-09-29 0:23 ` Mohammad Shuab Siddique
1 sibling, 0 replies; 3+ messages in thread
From: Mohammad Shuab Siddique @ 2026-09-29 0:23 UTC (permalink / raw)
To: dev; +Cc: kishore.padmanabha, Mohammad Shuab Siddique, Ajit Khaparde
From: Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com>
P7 devices support Tx completion coalescing in hardware: the driver
can program the Tx coalescing parameters during Tx ring allocation
instead of always disabling it. Use the wthresh config option
provided in ethdev to select the coalescing value for the Tx rings.
A value of 0 disables the feature. A value of 254 for wthresh is the
max allowable setting; the driver converts the provided value to the
nearest power of 2 for the hardware setting (1 rounds up to 2, which
maps to the same COAL_4 setting as an exact 4; 254 rounds up to 256).
bnxt_hwrm_ring_alloc() previously programmed cmpl_coal_cnt as
COAL_OFF unconditionally. Add a bnxt_get_cmpl_coal() helper and
thread a new tx_coal_thresh parameter through bnxt_hwrm_ring_alloc()
and its callers, wiring txq->wthresh (assigned from
tx_conf->tx_thresh.wthresh) through to the Tx ring's alloc call.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com>
---
v2:
* Rebased onto current main -- Stephen Hemminger noted v1 did not
apply cleanly.
* Added a "Tx Completion Coalescing" section to
doc/guides/nics/bnxt.rst and a release notes entry, both requested
by Stephen Hemminger.
doc/guides/nics/bnxt.rst | 10 +++++
doc/guides/rel_notes/release_26_11.rst | 2 +
drivers/net/bnxt/bnxt_hwrm.c | 51 ++++++++++++++++++++++++--
drivers/net/bnxt/bnxt_hwrm.h | 3 +-
drivers/net/bnxt/bnxt_mpc.c | 2 +-
drivers/net/bnxt/bnxt_ring.c | 12 +++---
drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 12 +++++-
drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 13 ++++++-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 14 ++++++-
drivers/net/bnxt/bnxt_txq.c | 1 +
drivers/net/bnxt/bnxt_txr.c | 1 -
11 files changed, 103 insertions(+), 18 deletions(-)
diff --git a/doc/guides/nics/bnxt.rst b/doc/guides/nics/bnxt.rst
index 48b950876c..8c36cec102 100644
--- a/doc/guides/nics/bnxt.rst
+++ b/doc/guides/nics/bnxt.rst
@@ -342,6 +342,16 @@ The BNXT PMD supports hardware-based CRC offload:
Note that the CRC offload is always turned on.
+Tx Completion Coalescing
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+On P7 devices, the BNXT PMD programs the hardware to coalesce Tx completions
+instead of generating one completion per descriptor. The coalescing count is
+derived from the ``wthresh`` field of ``struct rte_eth_txconf.tx_thresh``
+passed to ``rte_eth_tx_queue_setup()``, rounded up to the nearest power of
+two supported by the hardware (up to 256). A ``wthresh`` of 0 disables Tx
+completion coalescing.
+
Checksum Offload
^^^^^^^^^^^^^^^^
diff --git a/doc/guides/rel_notes/release_26_11.rst b/doc/guides/rel_notes/release_26_11.rst
index 87941f57dd..ab1192960c 100644
--- a/doc/guides/rel_notes/release_26_11.rst
+++ b/doc/guides/rel_notes/release_26_11.rst
@@ -81,6 +81,8 @@ New Features
is also folded into the standard ``oerrors`` counter.
* Raised the maximum Tx and Rx ring descriptor counts from 4096/8192 to
16384 each.
+ * Enabled hardware Tx completion coalescing on P7 devices, controlled
+ by the existing ``wthresh`` Tx queue configuration field.
* **Updated Intel iavf driver.**
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 1615b36aae..71a9730b5e 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1113,7 +1113,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
int rc = 0;
struct hwrm_func_qcaps_input req = {.req_type = 0 };
struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
- uint32_t flags, flags_ext2, flags_ext3;
+ uint32_t flags, flags_ext, flags_ext2, flags_ext3;
uint16_t new_max_vfs;
HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
@@ -1126,6 +1126,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
flags = rte_le_to_cpu_32(resp->flags);
+ flags_ext = rte_le_to_cpu_32(resp->flags_ext);
flags_ext2 = rte_le_to_cpu_32(resp->flags_ext2);
flags_ext3 = rte_le_to_cpu_32(resp->flags_ext3);
@@ -1215,6 +1216,8 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
PMD_DRV_LOG_LINE(DEBUG, "VLAN acceleration for TX is enabled");
}
+ if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP)
+ bp->fw_cap |= BNXT_FW_CAP_TX_COAL_CMPL;
bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
if (bp->tunnel_disable_flag)
@@ -2171,11 +2174,52 @@ mpc_chnl_types[] = {HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE,
HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA,
HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE};
+static uint8_t bnxt_get_cmpl_coal(uint16_t wthresh)
+{
+ uint8_t coal;
+ uint16_t th;
+
+ th = rte_align32pow2(wthresh);
+ if (wthresh == 1)
+ th = 2;
+
+ switch (th) {
+ case 2:
+ /* FALLTHROUGH */
+ case 4:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4;
+ break;
+ case 8:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8;
+ break;
+ case 16:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16;
+ break;
+ case 32:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32;
+ break;
+ case 64:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64;
+ break;
+ case 128:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128;
+ break;
+ case 256:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256;
+ break;
+ case 0:
+ default:
+ coal = HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF;
+ }
+ return coal;
+}
+
int bnxt_hwrm_ring_alloc(struct bnxt *bp,
struct bnxt_ring *ring,
uint32_t ring_type, uint32_t map_index,
uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
- uint16_t tx_cosq_id, uint16_t dpi)
+ uint16_t tx_cosq_id, uint16_t dpi,
+ uint16_t tx_coal_thresh)
{
int rc = 0;
uint32_t enables = 0;
@@ -2198,8 +2242,7 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp,
req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
if (bp->fw_cap & BNXT_FW_CAP_TX_COAL_CMPL)
- req.cmpl_coal_cnt =
- HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF;
+ req.cmpl_coal_cnt = bnxt_get_cmpl_coal(tx_coal_thresh);
if (tx_cosq_id != MPC_HW_COS_ID) {
req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
} else {
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index 3034803023..1dd6671046 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -221,7 +221,8 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp,
struct bnxt_ring *ring,
uint32_t ring_type, uint32_t map_index,
uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
- uint16_t tx_cosq_id, uint16_t dpi);
+ uint16_t tx_cosq_id, uint16_t dpi,
+ uint16_t tx_coal_thresh);
int bnxt_hwrm_ring_free(struct bnxt *bp,
struct bnxt_ring *ring, uint32_t ring_type,
uint16_t cp_ring_id);
diff --git a/drivers/net/bnxt/bnxt_mpc.c b/drivers/net/bnxt/bnxt_mpc.c
index 1398321ca7..5560d3da00 100644
--- a/drivers/net/bnxt/bnxt_mpc.c
+++ b/drivers/net/bnxt/bnxt_mpc.c
@@ -504,7 +504,7 @@ static int bnxt_mpc_ring_alloc_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id)
map_index,
cpr->hw_stats_ctx_id,
cp_ring->fw_ring_id,
- MPC_HW_COS_ID, BNXT_PRIVILEGED_DPI);
+ MPC_HW_COS_ID, BNXT_PRIVILEGED_DPI, 0);
if (rc) {
PMD_DRV_LOG_LINE(ERR, "mpc ring %d tx ring alloc failed rc:%d!",
chnl_id, rc);
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index 064520aa62..d478c60a1e 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -434,7 +434,7 @@ int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
cpr->dpi = dpi;
rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, cp_ring_index,
- HWRM_NA_SIGNATURE, nq_ring_id, 0, dpi);
+ HWRM_NA_SIGNATURE, nq_ring_id, 0, dpi, 0);
if (rc)
return rc;
@@ -505,7 +505,7 @@ int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp)
nqr->dpi = dpi;
rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, ring_index,
- HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0, dpi);
+ HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0, dpi, 0);
if (rc) {
rte_free(ring);
rte_free(nqr);
@@ -555,7 +555,7 @@ static int bnxt_alloc_rx_ring(struct bnxt *bp, int queue_index)
rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type,
queue_index, cpr->hw_stats_ctx_id,
- cp_ring->fw_ring_id, 0, dpi);
+ cp_ring->fw_ring_id, 0, dpi, 0);
if (rc)
return rc;
@@ -595,7 +595,7 @@ static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index)
rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, map_idx,
hw_stats_ctx_id, cp_ring->fw_ring_id, 0,
- BNXT_PRIVILEGED_DPI);
+ BNXT_PRIVILEGED_DPI, 0);
if (rc)
return rc;
@@ -833,7 +833,7 @@ int bnxt_alloc_async_cp_ring(struct bnxt *bp)
rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, 0,
HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0,
- BNXT_PRIVILEGED_DPI);
+ BNXT_PRIVILEGED_DPI, 0);
if (rc)
return rc;
@@ -944,7 +944,7 @@ int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index)
HWRM_RING_ALLOC_INPUT_RING_TYPE_TX,
queue_index, cpr->hw_stats_ctx_id,
cp_ring->fw_ring_id,
- tx_cosq_id, txr->dpi);
+ tx_cosq_id, txr->dpi, txq->wthresh);
if (rc)
goto err_out;
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
index 80074a56c4..1236d3c2fe 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
@@ -735,7 +735,9 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
uint32_t ring_mask = cp_ring_struct->ring_mask;
+ uint32_t tx_ring_mask;
+ tx_ring_mask = txq->tx_ring->tx_ring_struct->ring_mask;
do {
cons = RING_CMPL(ring_mask, raw_cons);
txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
@@ -751,7 +753,15 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
rte_memory_order_relaxed) + 1,
rte_memory_order_relaxed);
- nb_tx_pkts += txcmp->opaque;
+ if (CMP_TYPE(txcmp) == CMPL_BASE_TYPE_TX_L2_COAL) {
+ struct tx_cmpl_coal *txcmp_c = (struct tx_cmpl_coal *)txcmp;
+
+ nb_tx_pkts = (rte_le_to_cpu_32(txcmp_c->sq_cons_idx) -
+ (txq->tx_ring->tx_raw_cons & tx_ring_mask)) &
+ tx_ring_mask;
+ } else {
+ nb_tx_pkts += txcmp->opaque;
+ }
raw_cons = NEXT_RAW_CMP(raw_cons);
} while (nb_tx_pkts < ring_mask);
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
index aa2c5e26e6..7aa153bc4e 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
@@ -347,7 +347,9 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
uint32_t ring_mask = cp_ring_struct->ring_mask;
+ uint32_t tx_ring_mask;
+ tx_ring_mask = txq->tx_ring->tx_ring_struct->ring_mask;
do {
cons = RING_CMPL(ring_mask, raw_cons);
txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
@@ -363,12 +365,19 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
rte_memory_order_relaxed) + 1,
rte_memory_order_relaxed);
- if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ if (CMP_TYPE(txcmp) == CMPL_BASE_TYPE_TX_L2_COAL) {
+ struct tx_cmpl_coal *txcmp_c = (struct tx_cmpl_coal *)txcmp;
+
+ nb_tx_pkts = (rte_le_to_cpu_32(txcmp_c->sq_cons_idx) -
+ (txq->tx_ring->tx_raw_cons & tx_ring_mask)) &
+ tx_ring_mask;
+ } else if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)) {
nb_tx_pkts += txcmp->opaque;
- else
+ } else {
RTE_LOG_DP_LINE(ERR, BNXT,
"Unhandled CMP type %02x",
CMP_TYPE(txcmp));
+ }
raw_cons = NEXT_RAW_CMP(raw_cons);
} while (nb_tx_pkts < ring_mask);
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
index 5ac1809ad7..8dfb16a26d 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -569,6 +569,9 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
uint32_t ring_mask = cp_ring_struct->ring_mask;
+ uint32_t tx_ring_mask;
+
+ tx_ring_mask = txq->tx_ring->tx_ring_struct->ring_mask;
do {
cons = RING_CMPL(ring_mask, raw_cons);
@@ -585,12 +588,19 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
rte_memory_order_relaxed) + 1,
rte_memory_order_relaxed);
- if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ if (CMP_TYPE(txcmp) == CMPL_BASE_TYPE_TX_L2_COAL) {
+ struct tx_cmpl_coal *txcmp_c = (struct tx_cmpl_coal *)txcmp;
+
+ nb_tx_pkts = (rte_le_to_cpu_32(txcmp_c->sq_cons_idx) -
+ (txq->tx_ring->tx_raw_cons & tx_ring_mask)) &
+ tx_ring_mask;
+ } else if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)) {
nb_tx_pkts += txcmp->opaque;
- else
+ } else {
RTE_LOG_DP_LINE(ERR, BNXT,
"Unhandled CMP type %02x",
CMP_TYPE(txcmp));
+ }
raw_cons = NEXT_RAW_CMP(raw_cons);
} while (nb_tx_pkts < ring_mask);
diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c
index 03407c556a..830298bd5e 100644
--- a/drivers/net/bnxt/bnxt_txq.c
+++ b/drivers/net/bnxt/bnxt_txq.c
@@ -175,6 +175,7 @@ int bnxt_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
/* For PTP packets, process the completion sooner */
if (bp->ptp_cfg != NULL)
txq->tx_free_thresh = RTE_BNXT_MIN_TX_BURST;
+ txq->wthresh = tx_conf->tx_thresh.wthresh;
txq->offloads = eth_dev->data->dev_conf.txmode.offloads |
tx_conf->offloads;
/* mbuf fast free not supported for the following. Reset the bit */
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 64ff42b38e..fd0ac8fd19 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -740,7 +740,6 @@ static void bnxt_tx_cmp(struct bnxt_tx_queue *txq, int nb_tx, bool tx_coal_cmp)
static bool bnxt_is_tx_cmpl_type(uint16_t type)
{
return (type == CMPL_BASE_TYPE_TX_L2_PKT_TS ||
- type == CMPL_BASE_TYPE_TX_L2_COAL ||
type == CMPL_BASE_TYPE_TX_L2);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-09-29 0:20 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2026-09-21 2:57 [PATCH] net/bnxt: enable Tx completion coalescing in hardware Mohammad Shuab Siddique
2026-09-21 15:52 ` Stephen Hemminger
2026-09-29 0:23 ` [PATCH v2] " Mohammad Shuab Siddique
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