From: Nawal Kishor <nkishor@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>,
Nawal Kishor <nkishor@marvell.com>
Cc: <jerinj@marvell.com>, <asekhar@marvell.com>
Subject: [PATCH 2/2] common/cnxk: fix DPC double counting for legacy pools
Date: Fri, 30 Oct 2026 14:46:52 +0530 [thread overview]
Message-ID: <20261030091700.1237155-2-nkishor@marvell.com> (raw)
In-Reply-To: <20261030091700.1237155-1-nkishor@marvell.com>
For legacy (non-halo) pools, DPC was enabled on both the pool and the
aura contexts, so each operation was counted twice.
Enable and disable DPC only on the aura context.
Fixes: 28d65f12ac77 ("common/cnxk: add NPA diagnostic counter")
Signed-off-by: Nawal Kishor <nkishor@marvell.com>
---
drivers/common/cnxk/roc_npa.c | 70 +++++------------------------------
1 file changed, 10 insertions(+), 60 deletions(-)
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index ebeebf1205..484fe47465 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -1952,13 +1952,13 @@ roc_npa_pool_dpc_enable(uint64_t aura_handle, uint8_t counter_id, uint32_t flags
req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
req->op = NPA_AQ_INSTOP_WRITE;
if (!(flags & ROC_NPA_HALO_F)) {
- /* Enable DPC in Pool */
- req->ctype = NPA_AQ_CTYPE_POOL;
- req->pool.op_dpc_ena = 1;
- req->pool.op_dpc_set = counter_id;
- req->pool_mask.op_dpc_ena = 1;
- req->pool_mask.op_dpc_set = 0;
- req->pool_mask.op_dpc_set = ~req->pool_mask.op_dpc_set;
+ /* Enable DPC in Aura */
+ req->ctype = NPA_AQ_CTYPE_AURA;
+ req->aura.op_dpc_ena = 1;
+ req->aura.op_dpc_set = counter_id;
+ req->aura_mask.op_dpc_ena = 1;
+ req->aura_mask.op_dpc_set = 0;
+ req->aura_mask.op_dpc_set = ~req->aura_mask.op_dpc_set;
} else {
/* Enable DPC in Halo */
req->ctype = NPA_AQ_CTYPE_HALO;
@@ -1979,36 +1979,7 @@ roc_npa_pool_dpc_enable(uint64_t aura_handle, uint8_t counter_id, uint32_t flags
if (rsp->hdr.rc != 0)
goto exit;
- if (!(flags & ROC_NPA_HALO_F)) {
- req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox);
- if (req == NULL)
- goto disable;
-
- /* Enable DPC in Aura */
- req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
- req->op = NPA_AQ_INSTOP_WRITE;
- req->ctype = NPA_AQ_CTYPE_AURA;
- req->aura.op_dpc_ena = 1;
- req->aura.op_dpc_set = counter_id;
- req->aura_mask.op_dpc_ena = 1;
- req->aura_mask.op_dpc_set = 0;
- req->aura_mask.op_dpc_set = ~req->aura_mask.op_dpc_set;
-
- rc = mbox_process(mbox);
- if (rc < 0)
- goto disable;
-
- off = mbox->rx_start +
- PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
- rsp = (struct npa_cn20k_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
- if (rsp->hdr.rc != 0)
- goto disable;
- }
rc = 0;
- goto exit;
-
-disable:
- roc_npa_pool_dpc_disable(aura_handle, flags);
exit:
mbox_put(mbox);
return rc;
@@ -2038,9 +2009,9 @@ roc_npa_pool_dpc_disable(uint64_t aura_handle, uint32_t flags)
req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
req->op = NPA_AQ_INSTOP_WRITE;
if (!(flags & ROC_NPA_HALO_F)) {
- req->ctype = NPA_AQ_CTYPE_POOL;
- req->pool.op_dpc_ena = 0;
- req->pool_mask.op_dpc_ena = 1;
+ req->ctype = NPA_AQ_CTYPE_AURA;
+ req->aura.op_dpc_ena = 0;
+ req->aura_mask.op_dpc_ena = 1;
} else {
req->ctype = NPA_AQ_CTYPE_HALO;
req->halo.op_dpc_ena = 0;
@@ -2057,28 +2028,7 @@ roc_npa_pool_dpc_disable(uint64_t aura_handle, uint32_t flags)
if (rsp->hdr.rc != 0)
goto exit;
- if (!(flags & ROC_NPA_HALO_F)) {
- req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox);
- if (req == NULL)
- goto exit;
-
- req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
- req->op = NPA_AQ_INSTOP_WRITE;
- req->ctype = NPA_AQ_CTYPE_AURA;
- req->aura.op_dpc_ena = 0;
- req->aura_mask.op_dpc_ena = 1;
- rc = mbox_process(mbox);
- if (rc < 0)
- goto exit;
-
- off = mbox->rx_start + PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
- rsp = (struct npa_cn20k_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
- if (rsp->hdr.rc != 0)
- goto exit;
- }
-
rc = 0;
-
exit:
mbox_put(mbox);
return rc;
--
2.48.1
prev parent reply other threads:[~2026-10-30 9:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-30 9:16 [PATCH 1/2] common/cnxk: fix DPC alloc config width Nawal Kishor
2026-10-30 9:16 ` Nawal Kishor [this message]
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