[PATCH 1/2] common/cnxk: fix DPC alloc config width

[PATCH 1/2] common/cnxk: fix DPC alloc config width

[Nawal Kishor]

The dpc_conf field of the NPA DPC alloc mailbox request is a 64-bit
value, but it was declared as 16 bits in struct npa_cn20k_dpc_alloc_req
and in roc_npa_dpc_alloc(). The upper bits of the configuration were
truncated before reaching the AF.

Widen both to 64 bits.

Fixes: 28d65f12ac77 ("common/cnxk: add NPA diagnostic counter")

Signed-off-by: Nawal Kishor <nkishor@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 2 +-
 drivers/common/cnxk/roc_npa.c  | 2 +-
 drivers/common/cnxk/roc_npa.h  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 279a9cc99b..e21596c82e 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1466,7 +1466,7 @@ struct npa_cn20k_aq_enq_rsp {
 
 struct npa_cn20k_dpc_alloc_req {
 	struct mbox_msghdr hdr;
-	uint16_t __io dpc_conf;
+	uint64_t __io dpc_conf;
 };
 
 struct npa_cn20k_dpc_alloc_rsp {
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 425bbc782b..ebeebf1205 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -1850,7 +1850,7 @@ roc_npa_dev_unlock(void)
 }
 
 int
-roc_npa_dpc_alloc(uint8_t *counter_id, uint16_t conf)
+roc_npa_dpc_alloc(uint8_t *counter_id, uint64_t conf)
 {
 	struct npa_cn20k_dpc_alloc_req *req;
 	struct npa_cn20k_dpc_alloc_rsp *rsp;
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index db610cbd2c..df68e13ec6 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -893,7 +893,7 @@ int __roc_api roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit,
 
 void __roc_api roc_npa_dev_lock(void);
 void __roc_api roc_npa_dev_unlock(void);
-int __roc_api roc_npa_dpc_alloc(uint8_t *counter_id, uint16_t conf);
+int __roc_api roc_npa_dpc_alloc(uint8_t *counter_id, uint64_t conf);
 int __roc_api roc_npa_dpc_free(uint8_t counter_id);
 int __roc_api roc_npa_pool_dpc_enable(uint64_t aura_handle, uint8_t counter_id, uint32_t flags);
 int __roc_api roc_npa_pool_dpc_disable(uint64_t aura_handle, uint32_t flags);
-- 
2.48.1

[PATCH 2/2] common/cnxk: fix DPC double counting for legacy pools

[Nawal Kishor]

For legacy (non-halo) pools, DPC was enabled on both the pool and the
aura contexts, so each operation was counted twice.

Enable and disable DPC only on the aura context.

Fixes: 28d65f12ac77 ("common/cnxk: add NPA diagnostic counter")

Signed-off-by: Nawal Kishor <nkishor@marvell.com>
---
 drivers/common/cnxk/roc_npa.c | 70 +++++------------------------------
 1 file changed, 10 insertions(+), 60 deletions(-)

diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index ebeebf1205..484fe47465 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -1952,13 +1952,13 @@ roc_npa_pool_dpc_enable(uint64_t aura_handle, uint8_t counter_id, uint32_t flags
 	req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
 	req->op = NPA_AQ_INSTOP_WRITE;
 	if (!(flags & ROC_NPA_HALO_F)) {
-		/* Enable DPC in Pool */
-		req->ctype = NPA_AQ_CTYPE_POOL;
-		req->pool.op_dpc_ena = 1;
-		req->pool.op_dpc_set = counter_id;
-		req->pool_mask.op_dpc_ena = 1;
-		req->pool_mask.op_dpc_set = 0;
-		req->pool_mask.op_dpc_set = ~req->pool_mask.op_dpc_set;
+		/* Enable DPC in Aura */
+		req->ctype = NPA_AQ_CTYPE_AURA;
+		req->aura.op_dpc_ena = 1;
+		req->aura.op_dpc_set = counter_id;
+		req->aura_mask.op_dpc_ena = 1;
+		req->aura_mask.op_dpc_set = 0;
+		req->aura_mask.op_dpc_set = ~req->aura_mask.op_dpc_set;
 	} else {
 		/* Enable DPC in Halo */
 		req->ctype = NPA_AQ_CTYPE_HALO;
@@ -1979,36 +1979,7 @@ roc_npa_pool_dpc_enable(uint64_t aura_handle, uint8_t counter_id, uint32_t flags
 	if (rsp->hdr.rc != 0)
 		goto exit;
 
-	if (!(flags & ROC_NPA_HALO_F)) {
-		req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox);
-		if (req == NULL)
-			goto disable;
-
-		/* Enable DPC in Aura */
-		req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
-		req->op = NPA_AQ_INSTOP_WRITE;
-		req->ctype = NPA_AQ_CTYPE_AURA;
-		req->aura.op_dpc_ena = 1;
-		req->aura.op_dpc_set = counter_id;
-		req->aura_mask.op_dpc_ena = 1;
-		req->aura_mask.op_dpc_set = 0;
-		req->aura_mask.op_dpc_set = ~req->aura_mask.op_dpc_set;
-
-		rc = mbox_process(mbox);
-		if (rc < 0)
-			goto disable;
-
-		off = mbox->rx_start +
-		      PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
-		rsp = (struct npa_cn20k_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
-		if (rsp->hdr.rc != 0)
-			goto disable;
-	}
 	rc = 0;
-	goto exit;
-
-disable:
-	roc_npa_pool_dpc_disable(aura_handle, flags);
 exit:
 	mbox_put(mbox);
 	return rc;
@@ -2038,9 +2009,9 @@ roc_npa_pool_dpc_disable(uint64_t aura_handle, uint32_t flags)
 	req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
 	req->op = NPA_AQ_INSTOP_WRITE;
 	if (!(flags & ROC_NPA_HALO_F)) {
-		req->ctype = NPA_AQ_CTYPE_POOL;
-		req->pool.op_dpc_ena = 0;
-		req->pool_mask.op_dpc_ena = 1;
+		req->ctype = NPA_AQ_CTYPE_AURA;
+		req->aura.op_dpc_ena = 0;
+		req->aura_mask.op_dpc_ena = 1;
 	} else {
 		req->ctype = NPA_AQ_CTYPE_HALO;
 		req->halo.op_dpc_ena = 0;
@@ -2057,28 +2028,7 @@ roc_npa_pool_dpc_disable(uint64_t aura_handle, uint32_t flags)
 	if (rsp->hdr.rc != 0)
 		goto exit;
 
-	if (!(flags & ROC_NPA_HALO_F)) {
-		req = mbox_alloc_msg_npa_cn20k_aq_enq(mbox);
-		if (req == NULL)
-			goto exit;
-
-		req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
-		req->op = NPA_AQ_INSTOP_WRITE;
-		req->ctype = NPA_AQ_CTYPE_AURA;
-		req->aura.op_dpc_ena = 0;
-		req->aura_mask.op_dpc_ena = 1;
-		rc = mbox_process(mbox);
-		if (rc < 0)
-			goto exit;
-
-		off = mbox->rx_start + PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
-		rsp = (struct npa_cn20k_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
-		if (rsp->hdr.rc != 0)
-			goto exit;
-	}
-
 	rc = 0;
-
 exit:
 	mbox_put(mbox);
 	return rc;
-- 
2.48.1