* [PATCH v5 01/22] drm: Create Color Management DRM properties
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 02/22] drm: Create Color Management query properties Shashank Sharma
` (20 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
Color Management is an extension to DRM framework. It allows
abstraction of hardware color correction and enhancement capabilities
by virtue of DRM properties.
There are two major types of color correction supported by DRM
color manager:
- CTM: color transformation matrix, properties where a correction
matrix is used for color correction.
- Palette correction: Where direct LUT values are sent to be applied
on a color palette.
This patch initializes color management framework by:
1. Introducing new pointers in DRM mode_config structure to
carry CTM and Palette color correction properties.
2. Creating these DRM properties in DRM standard properties creation
sequence.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/drm_crtc.c | 19 +++++++++++++++++++
include/drm/drm_crtc.h | 5 +++++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index e7c8422..3644342 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1472,6 +1472,25 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
return -ENOMEM;
dev->mode_config.prop_mode_id = prop;
+ /* Color Management properties */
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_BLOB, "PALETTE_AFTER_CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.cm_palette_after_ctm_property = prop;
+
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_BLOB, "PALETTE_BEFORE_CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.cm_palette_before_ctm_property = prop;
+
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_BLOB, "CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.cm_ctm_property = prop;
+
return 0;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 33ddedd..5ddc1a2 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1148,6 +1148,11 @@ struct drm_mode_config {
struct drm_property *suggested_x_property;
struct drm_property *suggested_y_property;
+ /* Color Management Properties */
+ struct drm_property *cm_palette_before_ctm_property;
+ struct drm_property *cm_palette_after_ctm_property;
+ struct drm_property *cm_ctm_property;
+
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
--
1.9.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 02/22] drm: Create Color Management query properties
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 01/22] drm: Create Color Management DRM properties Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 03/22] drm: Add color correction blobs in CRTC state Shashank Sharma
` (19 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
DRM color management is written to extract the color correction
capabilities of various platforms, and every platform can showcase
its capabilities using the query properties.
Different hardwares can have different no of coefficients for palette
correction. Also the correction can be applied after/before color
transformation (CTM) unit in the display pipeline.
This patch adds two new read-only properties,
- cm_coeff_before_ctm_property: A platform driver should use this
property to show supported no_of_coefficients for palette correction,
which gets applied before ctm correction.
- cm_coeff_after_ctm_property: A platform driver should use this property
to show supported no_of_coefficients for palette correction, which gets
applied after ctm correction.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
---
drivers/gpu/drm/drm_crtc.c | 13 +++++++++++++
include/drm/drm_crtc.h | 4 ++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3644342..ad13630 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1491,6 +1491,19 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
return -ENOMEM;
dev->mode_config.cm_ctm_property = prop;
+ /* DRM properties to query color capabilities */
+ prop = drm_property_create(dev, DRM_MODE_PROP_IMMUTABLE,
+ "COEFFICIENTS_BEFORE_CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.cm_coeff_before_ctm_property = prop;
+
+ prop = drm_property_create(dev, DRM_MODE_PROP_IMMUTABLE,
+ "COEFFICIENTS_AFTER_CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.cm_coeff_after_ctm_property = prop;
+
return 0;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5ddc1a2..1a56596 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1153,6 +1153,10 @@ struct drm_mode_config {
struct drm_property *cm_palette_after_ctm_property;
struct drm_property *cm_ctm_property;
+ /* Color management capabilities query */
+ struct drm_property *cm_coeff_before_ctm_property;
+ struct drm_property *cm_coeff_after_ctm_property;
+
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 03/22] drm: Add color correction blobs in CRTC state
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 01/22] drm: Create Color Management DRM properties Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 02/22] drm: Create Color Management query properties Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 04/22] drm: Add set property support for color manager Shashank Sharma
` (18 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/drm_atomic_helper.c | 12 ++++++++++++
include/drm/drm_crtc.h | 5 +++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 87a2a44..d73ca9b9 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2193,6 +2193,12 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
if (state->mode_blob)
drm_property_reference_blob(state->mode_blob);
+ if (state->ctm_blob)
+ drm_property_reference_blob(state->ctm_blob);
+ if (state->palette_after_ctm_blob)
+ drm_property_reference_blob(state->palette_after_ctm_blob);
+ if (state->palette_before_ctm_blob)
+ drm_property_reference_blob(state->palette_before_ctm_blob);
state->mode_changed = false;
state->active_changed = false;
state->planes_changed = false;
@@ -2238,6 +2244,12 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
{
if (state->mode_blob)
drm_property_unreference_blob(state->mode_blob);
+ if (state->ctm_blob)
+ drm_property_unreference_blob(state->ctm_blob);
+ if (state->palette_after_ctm_blob)
+ drm_property_unreference_blob(state->palette_after_ctm_blob);
+ if (state->palette_before_ctm_blob)
+ drm_property_unreference_blob(state->palette_before_ctm_blob);
}
EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 1a56596..d416e20 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -304,6 +304,11 @@ struct drm_crtc_state {
/* blob property to expose current mode to atomic userspace */
struct drm_property_blob *mode_blob;
+ /* blob properties to hold the color properties' blobs */
+ struct drm_property_blob *palette_before_ctm_blob;
+ struct drm_property_blob *palette_after_ctm_blob;
+ struct drm_property_blob *ctm_blob;
+
struct drm_pending_vblank_event *event;
struct drm_atomic_state *state;
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 04/22] drm: Add set property support for color manager
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (2 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 03/22] drm: Add color correction blobs in CRTC state Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 05/22] drm: Add get " Shashank Sharma
` (17 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
As per DRM color manager design, if a userspace wants to set a correction
blob, it prepares it and sends the blob_id to kernel via set_property
call. DRM framework takes this blob_id, gets the blob, and saves it
in the CRTC state, so that, during the atomic_commit, the color correction
values from the blob can referred and applied on display controller
registers.
This patch adds this set_property support for color correction blobs
in drm framework.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/drm_atomic.c | 53 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 7bb3845..12a34e9 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -390,6 +390,38 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);
/**
+ * drm_atomic_crtc_set_blob - find and set a blob
+ * @state_blob: reference pointer to the color blob in the crtc_state
+ * @blob_id: blob_id coming from set_property() call
+ *
+ * Set a color correction blob (originating from a set blob property) on the
+ * desired CRTC state. This function will take reference of the blob property
+ * in the CRTC state, finds the blob based on blob_id (which comes from
+ * set_property call) and set the blob at the proper place.
+ *
+ * RETURNS:
+ * Zero on success, error code on failure.
+ */
+static int drm_atomic_crtc_set_blob(struct drm_device *dev,
+ struct drm_property_blob **state_blob, uint32_t blob_id)
+{
+ struct drm_property_blob *blob;
+
+ blob = drm_property_lookup_blob(dev, blob_id);
+ if (!blob) {
+ DRM_DEBUG_KMS("Invalid Blob ID\n");
+ return -EINVAL;
+ }
+
+ if (*state_blob)
+ drm_property_unreference_blob(*state_blob);
+
+ /* Attach the blob to be committed in state */
+ *state_blob = blob;
+ return 0;
+}
+
+/**
* drm_atomic_crtc_set_property - set property on CRTC
* @crtc: the drm CRTC to set a property on
* @state: the state object to update with the new property value
@@ -422,8 +454,25 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
if (mode)
drm_property_unreference_blob(mode);
return ret;
- }
- else if (crtc->funcs->atomic_set_property)
+ } else if (property == config->cm_palette_after_ctm_property) {
+ ret = drm_atomic_crtc_set_blob(dev,
+ &state->palette_after_ctm_blob, val);
+ if (ret)
+ DRM_ERROR("Failed to load blob palette_after_ctm\n");
+ return ret;
+ } else if (property == config->cm_palette_before_ctm_property) {
+ ret = drm_atomic_crtc_set_blob(dev,
+ &state->palette_before_ctm_blob, val);
+ if (ret)
+ DRM_ERROR("Failed to load blob palette_before_ctm\n");
+ return ret;
+ } else if (property == config->cm_ctm_property) {
+ ret = drm_atomic_crtc_set_blob(dev,
+ &state->ctm_blob, val);
+ if (ret)
+ DRM_ERROR("Failed to load blob ctm\n");
+ return ret;
+ } else if (crtc->funcs->atomic_set_property)
return crtc->funcs->atomic_set_property(crtc, state, property, val);
else
return -EINVAL;
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 05/22] drm: Add get property support for color manager
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (3 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 04/22] drm: Add set property support for color manager Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 06/22] drm: Add drm structures for palette color property Shashank Sharma
` (16 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
As per the DRM get_property implementation for a blob, framework
is supposed to return the blob_id to the caller. All the color
management blobs are saved in CRTC state during the set call.
This patch adds get_property support for color management
properties, by referring to the existing blob for the property
and passing its blob_id.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
---
drivers/gpu/drm/drm_atomic.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 12a34e9..b49aaeb 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -499,6 +499,14 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = state->active;
else if (property == config->prop_mode_id)
*val = (state->mode_blob) ? state->mode_blob->base.id : 0;
+ else if (property == config->cm_palette_after_ctm_property)
+ *val = (state->palette_after_ctm_blob) ?
+ state->palette_after_ctm_blob->base.id : 0;
+ else if (property == config->cm_palette_before_ctm_property)
+ *val = (state->palette_before_ctm_blob) ?
+ state->palette_before_ctm_blob->base.id : 0;
+ else if (property == config->cm_ctm_property)
+ *val = (state->ctm_blob) ? state->ctm_blob->base.id : 0;
else if (crtc->funcs->atomic_get_property)
return crtc->funcs->atomic_get_property(crtc, state, property, val);
else
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 06/22] drm: Add drm structures for palette color property
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (4 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 05/22] drm: Add get " Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 07/22] drm: Add structure to set/get a CTM " Shashank Sharma
` (15 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
include/uapi/drm/drm.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 3801584..681d5af 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -829,6 +829,32 @@ struct drm_event_vblank {
__u32 reserved;
};
+struct drm_r32g32b32 {
+ /*
+ * Data is in U8.24 fixed point format.
+ * All platforms support values within [0, 1.0] range,
+ * for Red, Green and Blue colors.
+ */
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+
+struct drm_palette {
+ /*
+ * This has to be a supported value during get call.
+ * Feature will be disabled if this is 0 while set
+ */
+ __u32 num_samples;
+ /*
+ * Starting of palette LUT in R32G32B32 format.
+ * Each of RGB value is in U8.24 fixed point format.
+ * Actual number of samples will depend upon num_samples
+ */
+ struct drm_r32g32b32 lut[0];
+};
+
/* typedef area */
#ifndef __KERNEL__
typedef struct drm_clip_rect drm_clip_rect_t;
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 07/22] drm: Add structure to set/get a CTM color property
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (5 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 06/22] drm: Add drm structures for palette color property Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 08/22] drm/i915: Add set property interface for CRTC Shashank Sharma
` (14 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
Color Manager framework defines a DRM property for color
space transformation and Gamut mapping. This property is called
CTM (Color Transformation Matrix).
This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents to
configure CTM coefficients for color correction.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
include/uapi/drm/drm.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 681d5af..f347c69 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -855,6 +855,16 @@ struct drm_palette {
struct drm_r32g32b32 lut[0];
};
+struct drm_ctm {
+ /*
+ * Each value is in S31.32 format.
+ * This is 3x3 matrix in row major format.
+ * Integer part will be clipped to nearest
+ * max/min boundary as supported by the HW platform.
+ */
+ __s64 ctm_coeff[9];
+};
+
/* typedef area */
#ifndef __KERNEL__
typedef struct drm_clip_rect drm_clip_rect_t;
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 08/22] drm/i915: Add set property interface for CRTC
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (6 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 07/22] drm: Add structure to set/get a CTM " Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 09/22] drm/i915: Create color management files Shashank Sharma
` (13 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
This patch adds set property interface for intel CRTC. This
interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cddb0c6..d01a524 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13275,6 +13275,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.page_flip = intel_crtc_page_flip,
.atomic_duplicate_state = intel_crtc_duplicate_state,
.atomic_destroy_state = intel_crtc_destroy_state,
+ .set_property = drm_atomic_helper_crtc_set_property,
};
static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
--
1.9.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 09/22] drm/i915: Create color management files
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (7 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 08/22] drm/i915: Add set property interface for CRTC Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 10/22] drm/i915: Register color correction capabilities Shashank Sharma
` (12 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
This patch create new files intel_color_manager.c which
will contain the core color correction code for I915 driver
and its header intel_color_manager.h
The per color property patches coming up in this patch series
will fill the appropriate functions in this file.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_color_manager.c | 33 ++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 50 ++++++++++++++++++++++++++++++
3 files changed, 85 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_color_manager.c
create mode 100644 drivers/gpu/drm/i915/intel_color_manager.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44d290a..56caf9e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -64,7 +64,8 @@ i915-y += intel_audio.o \
intel_overlay.o \
intel_psr.o \
intel_sideband.o \
- intel_sprite.o
+ intel_sprite.o \
+ intel_color_manager.o
i915-$(CONFIG_ACPI) += intel_acpi.o intel_opregion.o
i915-$(CONFIG_DRM_FBDEV_EMULATION) += intel_fbdev.o
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
new file mode 100644
index 0000000..7357d99
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Shashank Sharma <shashank.sharma@intel.com>
+ * Kausal Malladi <Kausal.Malladi@intel.com>
+ */
+
+#include "intel_color_manager.h"
+
+void intel_attach_color_properties_to_crtc(struct drm_device *dev,
+ struct drm_mode_object *mode_obj)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
new file mode 100644
index 0000000..eec52a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Shashank Sharma <shashank.sharma@intel.com>
+ * Kausal Malladi <Kausal.Malladi@intel.com>
+ */
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include "i915_drv.h"
+
+/* Color management bit utilities */
+#define GET_BIT_MASK(n) ((1 << n) - 1)
+
+/* Read bits of a word from bit no. 'start'(lsb) till 'n' bits */
+#define GET_BITS(x, start, nbits) ((x >> start) & GET_BIT_MASK(nbits))
+
+/* Round off by adding 1 to the immediate lower bit */
+#define GET_BITS_ROUNDOFF(x, start, nbits) \
+ ((GET_BITS(x, start, (nbits + 1)) + 1) >> 1)
+
+/* Clear bits of a word from bit no. 'start' till nbits */
+#define CLEAR_BITS(x, start, nbits) ( \
+ x &= ~((GET_BIT_MASK(nbits) << start)))
+
+/* Write bit_pattern of no_bits bits in a target word */
+#define SET_BITS(target, bit_pattern, start_bit, no_bits) \
+ do { \
+ CLEAR_BITS(target, start_bit, no_bits); \
+ target |= (bit_pattern << start_bit); \
+ } while (0)
--
1.9.1
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 10/22] drm/i915: Register color correction capabilities
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (8 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 09/22] drm/i915: Create color management files Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 11/22] drm/i915: CHV: Load gamma color correction values Shashank Sharma
` (11 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
From DRM color management:
============================
DRM color manager supports these color properties:
1. "ctm": Color transformation matrix property, where a
color transformation matrix of 9 correction values gets
applied as correction.
2. "palette_before_ctm": for corrections which get applied
beore color transformation matrix correction.
3. "palette_after_ctm": for corrections which get applied
after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting
various different no. of correction coefficients. So DRM color manager
support few properties using which a user space can query the platform's
capability, and prepare color correction accordingly.
These query properties are:
1. cm_coeff_after_ctm_property
2. cm_coeff_before_ctm_property
(CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers:
======================================
1. Gamma correction property as "palette_after_ctm" property
2. Degamma correction capability as "palette_bafore_ctm" property
capability as "palette_after_ctm" DRM color property hook.
3. CSC as "ctm" property.
So finally, This patch does the following:
1. Add a function which loads the platform's color correction
capabilities in the cm_crtc_palette_capabilities_property structure.
2. Attaches the cm_crtc_palette_capabilities_property to every CRTC
getting initiaized.
3. Adds two new parameters "num_samples_after_ctm" and
"num_samples_before_ctm" in intel_device_info as gamma and
degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++-
2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf14096..6044e5c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -785,6 +785,8 @@ struct intel_device_info {
u8 num_sprites[I915_MAX_PIPES];
u8 gen;
u8 ring_mask; /* Rings supported by the HW */
+ u16 num_samples_after_ctm;
+ u16 num_samples_before_ctm;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 7357d99..e466748 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -28,6 +28,37 @@
#include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
- struct drm_mode_object *mode_obj)
+ struct drm_crtc *crtc)
{
+ struct drm_mode_config *config = &dev->mode_config;
+ struct drm_mode_object *mode_obj = &crtc->base;
+
+ /*
+ * Register:
+ * =========
+ * Gamma correction as palette_after_ctm property
+ * Degamma correction as palette_before_ctm property
+ *
+ * Load:
+ * =====
+ * no. of coefficients supported on this platform for gamma
+ * and degamma with the query properties. A user
+ * space agent should read these query property, and prepare
+ * the color correction values accordingly. Its expected from the
+ * driver to load the right number of coefficients during the init
+ * phase.
+ */
+ if (config->cm_coeff_after_ctm_property) {
+ drm_object_attach_property(mode_obj,
+ config->cm_coeff_after_ctm_property,
+ INTEL_INFO(dev)->num_samples_after_ctm);
+ DRM_DEBUG_DRIVER("Gamma query property initialized\n");
+ }
+
+ if (config->cm_coeff_before_ctm_property) {
+ drm_object_attach_property(mode_obj,
+ config->cm_coeff_before_ctm_property,
+ INTEL_INFO(dev)->num_samples_before_ctm);
+ DRM_DEBUG_DRIVER("Degamma query property initialized\n");
+ }
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 11/22] drm/i915: CHV: Load gamma color correction values
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (9 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 10/22] drm/i915: Register color correction capabilities Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 12/22] drm/i915: CHV: Load degamma " Shashank Sharma
` (10 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_after_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coefficitents for best gamma color correction
modes possible in CHV, in device info structure, which is:
Gamma(10 bit, CGM HW unit): 257 coeff
These values will be loaded in cm_crtc_palette_capabilities_property
during the CRTC init section, by color manager's attach function.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/intel_color_manager.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 760e0ce..7780de4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -34,6 +34,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
+#include "intel_color_manager.h"
#include <linux/console.h>
#include <linux/module.h>
@@ -349,6 +350,7 @@ static const struct intel_device_info intel_cherryview_info = {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .num_samples_after_ctm = CHV_10BIT_GAMMA_MAX_VALS,
.is_valleyview = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index eec52a7..a378fe1 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -48,3 +48,6 @@
CLEAR_BITS(target, start_bit, no_bits); \
target |= (bit_pattern << start_bit); \
} while (0)
+
+/* CHV */
+#define CHV_10BIT_GAMMA_MAX_VALS 257
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 12/22] drm/i915: CHV: Load degamma color correction values
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (10 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 11/22] drm/i915: CHV: Load gamma color correction values Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 13/22] drm/i915: CHV: Pipe level Gamma correction Shashank Sharma
` (9 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_before_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coefficitents for degamma color correction
modes possible in CHV, in device info structure, which is:
CGM Degamma(10 bit, CGM HW unit): 65 coeff
These values will be loaded in cm_crtc_palette_capabilities_property
during the CRTC init section, by color manager's attach function.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@l.com>
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/intel_color_manager.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7780de4..6adf002 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -351,6 +351,7 @@ static const struct intel_device_info intel_cherryview_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = CHV_10BIT_GAMMA_MAX_VALS,
+ .num_samples_before_ctm = CHV_DEGAMMA_MAX_VALS,
.is_valleyview = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index a378fe1..14a1309 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -51,3 +51,4 @@
/* CHV */
#define CHV_10BIT_GAMMA_MAX_VALS 257
+#define CHV_DEGAMMA_MAX_VALS 65
--
1.9.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 13/22] drm/i915: CHV: Pipe level Gamma correction
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (11 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 12/22] drm/i915: CHV: Load degamma " Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 14/22] drm/i915: CHV: Pipe level degamma correction Shashank Sharma
` (8 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Adds Gamma correction macros
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++
drivers/gpu/drm/i915/intel_color_manager.c | 96 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 13 ++++
3 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88b3da2..8e0a1b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8148,4 +8148,16 @@ enum skl_disp_power_wells {
#define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/
#define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/
+/* Color Management */
+#define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00)
+#define PIPEB_CGM_CONTROL (VLV_DISPLAY_BASE + 0x69A00)
+#define PIPEC_CGM_CONTROL (VLV_DISPLAY_BASE + 0x6BA00)
+#define PIPEA_CGM_GAMMA (VLV_DISPLAY_BASE + 0x67000)
+#define PIPEB_CGM_GAMMA (VLV_DISPLAY_BASE + 0x69000)
+#define PIPEC_CGM_GAMMA (VLV_DISPLAY_BASE + 0x6B000)
+#define _PIPE_CGM_CONTROL(pipe) \
+ (_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL))
+#define _PIPE_GAMMA_BASE(pipe) \
+ (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index e466748..498e048 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,94 @@
#include "intel_color_manager.h"
+static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
+ struct drm_crtc *crtc)
+{
+ enum pipe pipe;
+ u16 red_fract, green_fract, blue_fract;
+ u32 red, green, blue, num_samples;
+ u32 word = 0;
+ u32 count, cgm_gamma_reg, cgm_control_reg;
+ u64 length;
+ struct drm_r32g32b32 *correction_values;
+ struct drm_palette *gamma_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc_state *state = crtc->state;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ gamma_data = (struct drm_palette *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+ num_samples = gamma_data->num_samples;
+ length = num_samples * sizeof(struct drm_r32g32b32);
+
+ switch (num_samples) {
+ case GAMMA_DISABLE_VALS:
+
+ /* Disable Gamma functionality on Pipe - CGM Block */
+ cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));
+ cgm_control_reg &= ~CGM_GAMMA_EN;
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);
+ state->palette_after_ctm_blob = NULL;
+ DRM_DEBUG_DRIVER("Gamma disabled on Pipe %c\n",
+ pipe_name(pipe));
+ return 0;
+
+ case CHV_8BIT_GAMMA_MAX_VALS:
+ case CHV_10BIT_GAMMA_MAX_VALS:
+
+ count = 0;
+ cgm_gamma_reg = _PIPE_GAMMA_BASE(pipe);
+ correction_values = gamma_data->lut;
+
+ while (count < num_samples) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ if (blue > CHV_MAX_GAMMA)
+ blue = CHV_MAX_GAMMA;
+
+ if (green > CHV_MAX_GAMMA)
+ green = CHV_MAX_GAMMA;
+
+ if (red > CHV_MAX_GAMMA)
+ red = CHV_MAX_GAMMA;
+
+ /* get MSB 10 bits from fraction part (14:23) */
+ blue_fract = GET_BITS(blue, 14, 10);
+ green_fract = GET_BITS(green, 14, 10);
+ red_fract = GET_BITS(red, 14, 10);
+
+ /* Green (25:16) and Blue (9:0) to be written */
+ SET_BITS(word, green_fract, 16, 10);
+ SET_BITS(word, blue_fract, 0, 10);
+ I915_WRITE(cgm_gamma_reg, word);
+ cgm_gamma_reg += 4;
+
+ /* Red (9:0) to be written */
+ word = red_fract;
+ I915_WRITE(cgm_gamma_reg, word);
+
+ cgm_gamma_reg += 4;
+ count++;
+ }
+
+ /* Enable (CGM) Gamma on Pipe */
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe),
+ I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_GAMMA_EN);
+ DRM_DEBUG_DRIVER("CGM Gamma enabled on Pipe %c\n",
+ pipe_name(pipe));
+ return 0;
+
+ default:
+ DRM_ERROR("Invalid number of samples (%u) for Gamma LUT\n",
+ num_samples);
+ return -EINVAL;
+ }
+}
+
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_crtc *crtc)
{
@@ -61,4 +149,12 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev,
INTEL_INFO(dev)->num_samples_before_ctm);
DRM_DEBUG_DRIVER("Degamma query property initialized\n");
}
+
+ /* Gamma correction */
+ if (config->cm_palette_after_ctm_property) {
+ drm_object_attach_property(mode_obj,
+ config->cm_palette_after_ctm_property, 0);
+ DRM_DEBUG_DRIVER("gamma property attached to CRTC\n");
+ }
+
}
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 14a1309..de706d9 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -52,3 +52,16 @@
/* CHV */
#define CHV_10BIT_GAMMA_MAX_VALS 257
#define CHV_DEGAMMA_MAX_VALS 65
+
+/* No of coeff for disabling gamma is 0 */
+#define GAMMA_DISABLE_VALS 0
+
+/* Gamma on CHV */
+#define CHV_10BIT_GAMMA_MAX_VALS 257
+#define CHV_8BIT_GAMMA_MAX_VALS 256
+#define CHV_10BIT_GAMMA_MSB_SHIFT 6
+#define CHV_GAMMA_SHIFT_GREEN 16
+#define CHV_MAX_GAMMA ((1 << 24) - 1)
+
+/* CHV CGM Block */
+#define CGM_GAMMA_EN (1 << 2)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 14/22] drm/i915: CHV: Pipe level degamma correction
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (12 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 13/22] drm/i915: CHV: Pipe level Gamma correction Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 15/22] drm/i915: CHV: Pipe level CSC correction Shashank Sharma
` (7 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
CHV/BSW supports Degamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
CHV/BSW platform
2. Add DeGamma correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_color_manager.c | 91 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 5 ++
3 files changed, 102 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8e0a1b1..cbb5fc9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8160,4 +8160,10 @@ enum skl_disp_power_wells {
#define _PIPE_GAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
+#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
+#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000)
+#define _PIPE_DEGAMMA_BASE(pipe) \
+ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 498e048..73c0762 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,91 @@
#include "intel_color_manager.h"
+static int chv_set_degamma(struct drm_device *dev,
+ struct drm_property_blob *blob, struct drm_crtc *crtc)
+{
+ u16 red_fract, green_fract, blue_fract;
+ u32 red, green, blue;
+ u32 num_samples;
+ u32 word = 0;
+ u32 count, cgm_control_reg, cgm_degamma_reg;
+ u64 length;
+ enum pipe pipe;
+ struct drm_palette *degamma_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_r32g32b32 *correction_values = NULL;
+ struct drm_crtc_state *state = crtc->state;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ degamma_data = (struct drm_palette *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+ num_samples = degamma_data->num_samples;
+ length = num_samples * sizeof(struct drm_r32g32b32);
+
+ if (num_samples == GAMMA_DISABLE_VALS) {
+ /* Disable DeGamma functionality on Pipe - CGM Block */
+ cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));
+ cgm_control_reg &= ~CGM_DEGAMMA_EN;
+ state->palette_before_ctm_blob = NULL;
+
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);
+ DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n",
+ pipe_name(pipe));
+ return 0;
+ } else if (num_samples == CHV_DEGAMMA_MAX_VALS) {
+ cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe);
+
+ count = 0;
+ correction_values = (struct drm_r32g32b32 *)°amma_data->lut;
+ while (count < CHV_DEGAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ if (blue > CHV_MAX_GAMMA)
+ blue = CHV_MAX_GAMMA;
+
+ if (green > CHV_MAX_GAMMA)
+ green = CHV_MAX_GAMMA;
+
+ if (red > CHV_MAX_GAMMA)
+ red = CHV_MAX_GAMMA;
+
+ blue_fract = GET_BITS(blue, 8, 14);
+ green_fract = GET_BITS(green, 8, 14);
+ red_fract = GET_BITS(red, 8, 14);
+
+ /* Green (29:16) and Blue (13:0) in DWORD1 */
+ SET_BITS(word, green_fract, 16, 14);
+ SET_BITS(word, green_fract, 0, 14);
+ I915_WRITE(cgm_degamma_reg, word);
+ cgm_degamma_reg += 4;
+
+ /* Red (13:0) to be written to DWORD2 */
+ word = red_fract;
+ I915_WRITE(cgm_degamma_reg, word);
+ cgm_degamma_reg += 4;
+ count++;
+ }
+
+ DRM_DEBUG_DRIVER("DeGamma LUT loaded for Pipe %c\n",
+ pipe_name(pipe));
+
+ /* Enable DeGamma on Pipe */
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe),
+ I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_DEGAMMA_EN);
+
+ DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",
+ pipe_name(pipe));
+ return 0;
+ } else {
+ DRM_ERROR("Invalid number of samples for DeGamma LUT\n");
+ return -EINVAL;
+ }
+}
+
static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)
{
@@ -157,4 +242,10 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev,
DRM_DEBUG_DRIVER("gamma property attached to CRTC\n");
}
+ /* Degamma correction */
+ if (config->cm_palette_before_ctm_property) {
+ drm_object_attach_property(mode_obj,
+ config->cm_palette_before_ctm_property, 0);
+ DRM_DEBUG_DRIVER("degamma property attached to CRTC\n");
+ }
}
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index de706d9..77a2119 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -63,5 +63,10 @@
#define CHV_GAMMA_SHIFT_GREEN 16
#define CHV_MAX_GAMMA ((1 << 24) - 1)
+/* Degamma on CHV */
+#define CHV_DEGAMMA_MSB_SHIFT 2
+#define CHV_DEGAMMA_GREEN_SHIFT 16
+
/* CHV CGM Block */
#define CGM_GAMMA_EN (1 << 2)
+#define CGM_DEGAMMA_EN (1 << 0)
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 15/22] drm/i915: CHV: Pipe level CSC correction
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (13 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 14/22] drm/i915: CHV: Pipe level degamma correction Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 16/22] drm/i915: Commit color correction to CRTC Shashank Sharma
` (6 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC correction macros
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
Signed-off-by: Kumar, Kiran S <kiran.s.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++
drivers/gpu/drm/i915/intel_color_manager.c | 99 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 19 ++++++
3 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbb5fc9..c395b63 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8166,4 +8166,12 @@ enum skl_disp_power_wells {
#define _PIPE_DEGAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900)
+#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900)
+#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900)
+#define _PIPE_CSC_BASE(pipe) \
+ (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
+
+
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 73c0762..6b17b20 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,98 @@
#include "intel_color_manager.h"
+static s32 chv_prepare_csc_coeff(s64 csc_value)
+{
+ s32 csc_int_value;
+ u32 csc_fract_value;
+ s32 csc_s3_12_format;
+
+ if (csc_value >= 0) {
+ csc_value += CHV_CSC_FRACT_ROUNDOFF;
+ if (csc_value > CHV_CSC_COEFF_MAX)
+ csc_value = CHV_CSC_COEFF_MAX;
+ } else {
+ csc_value = -csc_value;
+ csc_value += CHV_CSC_FRACT_ROUNDOFF;
+ if (csc_value > CHV_CSC_COEFF_MAX + 1)
+ csc_value = CHV_CSC_COEFF_MAX + 1;
+ csc_value = -csc_value;
+ }
+
+ csc_int_value = csc_value >> CHV_CSC_COEFF_SHIFT;
+ csc_int_value <<= CHV_CSC_COEFF_INT_SHIFT;
+ if (csc_value < 0)
+ csc_int_value |= CSC_COEFF_SIGN;
+
+ csc_fract_value = csc_value;
+ csc_fract_value >>= CHV_CSC_COEFF_FRACT_SHIFT;
+ csc_s3_12_format = csc_int_value | csc_fract_value;
+
+ return csc_s3_12_format;
+}
+
+static int chv_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
+ struct drm_crtc *crtc)
+{
+ struct drm_ctm *csc_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 reg;
+ enum pipe pipe;
+ s32 word = 0, temp;
+ int count = 0;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ if (blob->length != sizeof(struct drm_ctm)) {
+ DRM_ERROR("Invalid length of data received\n");
+ return -EINVAL;
+ }
+
+ csc_data = (struct drm_ctm *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+
+ /* Disable CSC functionality */
+ reg = _PIPE_CGM_CONTROL(pipe);
+ I915_WRITE(reg, I915_READ(reg) & (~CGM_CSC_EN));
+
+ DRM_DEBUG_DRIVER("Disabled CSC Functionality on Pipe %c\n",
+ pipe_name(pipe));
+
+ reg = _PIPE_CSC_BASE(pipe);
+
+ /*
+ * First 8 of 9 CSC correction values go in pair, to first
+ * 4 CSC register (bit 0:15 and 16:31)
+ */
+ while (count < CSC_MAX_VALS - 1) {
+ temp = chv_prepare_csc_coeff(
+ csc_data->ctm_coeff[count]);
+ SET_BITS(word, GET_BITS(temp, 16, 16), 0, 16);
+ count++;
+
+ temp = chv_prepare_csc_coeff(
+ csc_data->ctm_coeff[count]);
+ SET_BITS(word, GET_BITS(temp, 16, 16), 16, 16);
+ count++;
+
+ I915_WRITE(reg, word);
+ reg += 4;
+ }
+
+ /* 9th coeff goes to 5th register, bit 0:16 */
+ temp = chv_prepare_csc_coeff(
+ csc_data->ctm_coeff[count]);
+ SET_BITS(word, GET_BITS(temp, 16, 16), 0, 16);
+ I915_WRITE(reg, word);
+
+ /* Enable CSC functionality */
+ reg = _PIPE_CGM_CONTROL(pipe);
+ I915_WRITE(reg, I915_READ(reg) | CGM_CSC_EN);
+ DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe));
+ return 0;
+}
+
static int chv_set_degamma(struct drm_device *dev,
struct drm_property_blob *blob, struct drm_crtc *crtc)
{
@@ -248,4 +340,11 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev,
config->cm_palette_before_ctm_property, 0);
DRM_DEBUG_DRIVER("degamma property attached to CRTC\n");
}
+
+ /* CSC */
+ if (config->cm_ctm_property) {
+ drm_object_attach_property(mode_obj,
+ config->cm_ctm_property, 0);
+ DRM_DEBUG_DRIVER("CSC property attached to CRTC\n");
+ }
}
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 77a2119..7b96512 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -63,10 +63,29 @@
#define CHV_GAMMA_SHIFT_GREEN 16
#define CHV_MAX_GAMMA ((1 << 24) - 1)
+/*
+ * CSC on CHV
+ * Fractional part is 32 bit, and we need only 12 MSBs for programming
+ * into registers. ROUNDOFF is required to minimize loss of precision.
+ */
+#define CHV_CSC_FRACT_ROUNDOFF (1 << 19)
+/*
+ * CSC values are 64-bit values. For CHV, the maximum CSC value that
+ * user can program is 7.99999..., which can be represented in fixed point
+ * S31.32 format like this, with all fractional bits as 1
+ */
+#define CHV_CSC_COEFF_MAX 0x00000007FFFFFFFF
+#define CHV_CSC_COEFF_SHIFT 32
+#define CHV_CSC_COEFF_INT_SHIFT 28
+#define CSC_COEFF_SIGN (1 << 31)
+#define CHV_CSC_COEFF_FRACT_SHIFT 4
+#define CSC_MAX_VALS 9
+
/* Degamma on CHV */
#define CHV_DEGAMMA_MSB_SHIFT 2
#define CHV_DEGAMMA_GREEN_SHIFT 16
/* CHV CGM Block */
#define CGM_GAMMA_EN (1 << 2)
+#define CGM_CSC_EN (1 << 1)
#define CGM_DEGAMMA_EN (1 << 0)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 16/22] drm/i915: Commit color correction to CRTC
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (14 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 15/22] drm/i915: CHV: Pipe level CSC correction Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 17/22] drm/i915: Attach color properties " Shashank Sharma
` (5 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
The color correction blob values are loaded during set_property
calls. This patch adds a function to find the blob and apply the
correction values to the display registers, during the atomic
commit call.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/intel_color_manager.c | 44 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_drv.h | 3 ++
3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 6b17b20..fe95762 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -292,6 +292,50 @@ static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
}
}
+void intel_color_manager_crtc_commit(struct drm_device *dev,
+ struct drm_crtc_state *crtc_state)
+{
+ struct drm_property_blob *blob;
+ struct drm_crtc *crtc = crtc_state->crtc;
+ int ret = -EINVAL;
+
+ blob = crtc_state->palette_after_ctm_blob;
+ if (blob) {
+ /* Gamma correction is platform specific */
+ if (IS_CHERRYVIEW(dev))
+ ret = chv_set_gamma(dev, blob, crtc);
+
+ if (ret)
+ DRM_ERROR("set Gamma correction failed\n");
+ else
+ DRM_DEBUG_DRIVER("Gamma correction success\n");
+ }
+
+ blob = crtc_state->palette_before_ctm_blob;
+ if (blob) {
+ /* Degamma correction */
+ if (IS_CHERRYVIEW(dev))
+ ret = chv_set_degamma(dev, blob, crtc);
+
+ if (ret)
+ DRM_ERROR("set degamma correction failed\n");
+ else
+ DRM_DEBUG_DRIVER("degamma correction success\n");
+ }
+
+ blob = crtc_state->ctm_blob;
+ if (blob) {
+ /* CSC correction */
+ if (IS_CHERRYVIEW(dev))
+ ret = chv_set_csc(dev, blob, crtc);
+
+ if (ret)
+ DRM_ERROR("set CSC correction failed\n");
+ else
+ DRM_DEBUG_DRIVER("CSC correction success\n");
+ }
+}
+
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d01a524..8c7f8d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13564,6 +13564,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
intel_update_pipe_config(intel_crtc, old_intel_state);
else if (INTEL_INFO(dev)->gen >= 9)
skl_detach_scalers(intel_crtc);
+
+ intel_color_manager_crtc_commit(dev, crtc->state);
}
static void intel_finish_crtc_commit(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 91b6b40..3e79bb4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1474,4 +1474,7 @@ void intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state);
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
+/* intel_color_manager.c */
+void intel_color_manager_crtc_commit(struct drm_device *dev,
+ struct drm_crtc_state *crtc_state);
#endif /* __INTEL_DRV_H__ */
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 17/22] drm/i915: Attach color properties to CRTC
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (15 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 16/22] drm/i915: Commit color correction to CRTC Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 18/22] drm/i915: BDW: Load gamma correction values Shashank Sharma
` (4 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
Function intel_attach_color_properties_to_crtc attaches a
color property to its CRTC object. This patch calls this
function from crtc initialization sequence.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8c7f8d3..cc284bcd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13895,6 +13895,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
intel_crtc->cursor_size = ~0;
intel_crtc->wm.cxsr_allowed = true;
+ intel_attach_color_properties_to_crtc(dev, &intel_crtc->base);
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3e79bb4..ebe776c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1477,4 +1477,6 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
/* intel_color_manager.c */
void intel_color_manager_crtc_commit(struct drm_device *dev,
struct drm_crtc_state *crtc_state);
+void intel_attach_color_properties_to_crtc(struct drm_device *dev,
+ struct drm_crtc *crtc);
#endif /* __INTEL_DRV_H__ */
--
1.9.1
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 18/22] drm/i915: BDW: Load gamma correction values
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (16 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 17/22] drm/i915: Attach color properties " Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 19/22] drm/i915: BDW: Pipe level Gamma correction Shashank Sharma
` (3 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
I915 color manager registers pipe gamma correction as palette
correction after CTM property.
For BDW and higher platforms, split gamma correction is the best
gamma correction. This patch adds the no of coefficients(512) for
split gamma correction as "num_samples_after_ctm" parameter in device
info structures, for all of those.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
drivers/gpu/drm/i915/intel_color_manager.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6adf002..8beac5c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -302,6 +302,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -314,6 +315,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
.gen = 8, .is_mobile = 1, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -326,6 +328,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -338,6 +341,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = {
.gen = 8, .is_mobile = 1, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -363,6 +367,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -376,6 +381,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.gen = 9, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -389,6 +395,7 @@ static const struct intel_device_info intel_broxton_info = {
.gen = 9,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.num_pipes = 3,
.has_ddi = 1,
.has_fpga_dbg = 1,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 7b96512..271246a 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -89,3 +89,6 @@
#define CGM_GAMMA_EN (1 << 2)
#define CGM_CSC_EN (1 << 1)
#define CGM_DEGAMMA_EN (1 << 0)
+
+/* Gamma on BDW */
+#define BDW_SPLITGAMMA_MAX_VALS 512
--
1.9.1
_______________________________________________
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 19/22] drm/i915: BDW: Pipe level Gamma correction
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (17 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 18/22] drm/i915: BDW: Load gamma correction values Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 20/22] drm/i915: BDW: Load degamma correction values Shashank Sharma
` (2 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. Split mode
4. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values
for BDW/SKL/BXT platforms
2. Adds Gamma correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/i915_reg.h | 25 ++-
drivers/gpu/drm/i915/intel_color_manager.c | 285 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 6 +
3 files changed, 314 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c395b63..13e268a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5685,11 +5685,15 @@ enum skl_disp_power_wells {
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
-#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
+#define _LGC_PALETTE_C 0x4b000
+#define LGC_PALETTE(pipe, i) (_PIPE3(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B, \
+ _LGC_PALETTE_C) + (i) * 4)
#define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80
-#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
+#define _GAMMA_MODE_C 0x4b480
+#define GAMMA_MODE(pipe) \
+ _PIPE3(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B, _GAMMA_MODE_C)
#define GAMMA_MODE_MODE_MASK (3 << 0)
#define GAMMA_MODE_MODE_8BIT (0 << 0)
#define GAMMA_MODE_MODE_10BIT (1 << 0)
@@ -8172,6 +8176,23 @@ enum skl_disp_power_wells {
#define _PIPE_CSC_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
+/* BDW gamma correction */
+#define PAL_PREC_INDEX_A 0x4A400
+#define PAL_PREC_INDEX_B 0x4AC00
+#define PAL_PREC_INDEX_C 0x4B400
+#define PAL_PREC_DATA_A 0x4A404
+#define PAL_PREC_DATA_B 0x4AC04
+#define PAL_PREC_DATA_C 0x4B404
+#define PAL_PREC_GCMAX_A 0x4A410
+#define PAL_PREC_GCMAX_B 0x4AC10
+#define PAL_PREC_GCMAX_C 0x4B410
+
+#define _PREC_PAL_INDEX(pipe) \
+ (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B, PAL_PREC_INDEX_C))
+#define _PREC_PAL_DATA(pipe) \
+ (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B, PAL_PREC_DATA_C))
+#define _PREC_PAL_GCMAX(pipe) \
+ (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index fe95762..cf85bc3 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,289 @@
#include "intel_color_manager.h"
+static void bdw_write_8bit_gamma_legacy(struct drm_device *dev,
+ struct drm_r32g32b32 *correction_values, u32 palette)
+{
+ u16 blue_fract, green_fract, red_fract;
+ u32 blue, green, red;
+ u32 count = 0;
+ u32 word = 0;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ while (count < BDW_8BIT_GAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ /*
+ * Maximum possible gamma correction value supported
+ * for BDW is 0xFFFFFFFF, so clamp the values accordingly
+ */
+ if (blue >= BDW_MAX_GAMMA)
+ blue = BDW_MAX_GAMMA;
+ if (green >= BDW_MAX_GAMMA)
+ green = BDW_MAX_GAMMA;
+ if (red >= BDW_MAX_GAMMA)
+ red = BDW_MAX_GAMMA;
+
+ blue_fract = GET_BITS(blue, 16, 8);
+ green_fract = GET_BITS(green, 16, 8);
+ red_fract = GET_BITS(red, 16, 8);
+
+ /* Blue (7:0) Green (15:8) and Red (23:16) */
+ SET_BITS(word, blue_fract, 0, 8);
+ SET_BITS(word, green_fract, 8, 8);
+ SET_BITS(word, blue_fract, 16, 8);
+ I915_WRITE(palette, word);
+ palette += 4;
+ count++;
+ }
+}
+
+static void bdw_write_10bit_gamma_precision(struct drm_device *dev,
+ struct drm_r32g32b32 *correction_values, u32 pal_prec_data,
+ u32 no_of_coeff)
+{
+ u16 blue_fract, green_fract, red_fract;
+ u32 word = 0;
+ u32 count = 0;
+ u32 blue, green, red;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ while (count < no_of_coeff) {
+
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ /*
+ * Maximum possible gamma correction value supported
+ * for BDW is 0xFFFFFFFF, so clamp the values accordingly
+ */
+ if (blue >= BDW_MAX_GAMMA)
+ blue = BDW_MAX_GAMMA;
+ if (green >= BDW_MAX_GAMMA)
+ green = BDW_MAX_GAMMA;
+ if (red >= BDW_MAX_GAMMA)
+ red = BDW_MAX_GAMMA;
+
+ /*
+ * Gamma correction values are sent in 8.24 format
+ * with 8 int and 24 fraction bits. BDW 10 bit gamma
+ * unit expects correction registers to be programmed in
+ * 0.10 format, with 0 int and 16 fraction bits. So take
+ * MSB 10 bit values(bits 23-14) from the fraction part and
+ * prepare the correction registers.
+ */
+ blue_fract = GET_BITS(blue, 14, 10);
+ green_fract = GET_BITS(green, 14, 10);
+ red_fract = GET_BITS(red, 14, 10);
+
+ /* Arrange: Red (29:20) Green (19:10) and Blue (9:0) */
+ SET_BITS(word, red_fract, 20, 10);
+ SET_BITS(word, green_fract, 10, 10);
+ SET_BITS(word, blue_fract, 0, 10);
+ I915_WRITE(pal_prec_data, word);
+ count++;
+ }
+ DRM_DEBUG_DRIVER("Gamma correction programmed\n");
+}
+
+static void bdw_write_12bit_gamma_precision(struct drm_device *dev,
+ struct drm_r32g32b32 *correction_values, u32 pal_prec_data,
+ enum pipe pipe)
+{
+ uint16_t blue_fract, green_fract, red_fract;
+ uint32_t gcmax;
+ uint32_t word = 0;
+ uint32_t count = 0;
+ uint32_t gcmax_reg;
+ u32 blue, green, red;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* Program first 512 values in precision palette */
+ while (count < BDW_12BIT_GAMMA_MAX_VALS - 1) {
+
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ /*
+ * Maximum possible gamma correction value supported
+ * for BDW is 0xFFFFFFFF, so clamp the values accordingly
+ */
+ if (blue >= BDW_MAX_GAMMA)
+ blue = BDW_MAX_GAMMA;
+ if (green >= BDW_MAX_GAMMA)
+ green = BDW_MAX_GAMMA;
+ if (red >= BDW_MAX_GAMMA)
+ red = BDW_MAX_GAMMA;
+
+ /*
+ * Framework's general gamma format is 8.24 (8 int 16 fraction)
+ * BDW Platform's supported gamma format is 16 bit correction
+ * values in 0.16 format. So extract higher 16 fraction bits
+ * from 8.24 gamma correction values.
+ */
+ red_fract = GET_BITS(red, 8, 16);
+ green_fract = GET_BITS(green, 8, 16);
+ blue_fract = GET_BITS(blue, 8, 16);
+
+ /*
+ * From the bspec:
+ * For 12 bit gamma correction, program precision palette
+ * with 16 bits per color in a 0.16 format with 0 integer and
+ * 16 fractional bits (upper 10 bits in odd indexes, lower 6
+ * bits in even indexes)
+ */
+
+ /* Even index: Lower 6 bits from correction should go as MSB */
+ SET_BITS(word, GET_BITS(red_fract, 0, 6), 24, 6);
+ SET_BITS(word, GET_BITS(green_fract, 0, 6), 14, 6);
+ SET_BITS(word, GET_BITS(blue_fract, 0, 6), 4, 6);
+ I915_WRITE(pal_prec_data, word);
+
+ word = 0x0;
+ /* Odd index: Upper 10 bits of correction should go as MSB */
+ SET_BITS(word, GET_BITS(red_fract, 6, 10), 20, 10);
+ SET_BITS(word, GET_BITS(green_fract, 6, 10), 10, 10);
+ SET_BITS(word, GET_BITS(blue_fract, 6, 10), 0, 10);
+
+ I915_WRITE(pal_prec_data, word);
+ count++;
+ }
+
+ /* Now program the 513th value in GCMAX regs */
+ word = 0;
+ gcmax_reg = _PREC_PAL_GCMAX(pipe);
+ gcmax = min_t(u32, GET_BITS(correction_values[count].r32, 8, 17),
+ BDW_MAX_GAMMA);
+ SET_BITS(word, gcmax, 0, 17);
+ I915_WRITE(gcmax_reg, word);
+ gcmax_reg += 4;
+
+ word = 0;
+ gcmax = min_t(u32, GET_BITS(correction_values[count].g32, 8, 17),
+ BDW_MAX_GAMMA);
+ SET_BITS(word, gcmax, 0, 17);
+ I915_WRITE(gcmax_reg, word);
+ gcmax_reg += 4;
+
+ word = 0;
+ gcmax = min_t(u32, GET_BITS(correction_values[count].b32, 8, 17),
+ BDW_MAX_GAMMA);
+ SET_BITS(word, gcmax, 0, 17);
+ I915_WRITE(gcmax_reg, word);
+}
+
+/* Apply unity gamma for gamma reset */
+static void bdw_reset_gamma(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ u16 count = 0;
+ u32 val;
+ u32 pal_prec_data = LGC_PALETTE(pipe, 0);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /* Reset the palette for unit gamma */
+ while (count < BDW_8BIT_GAMMA_MAX_VALS) {
+ /* Red (23:16) Green (15:8) and Blue (7:0) */
+ val = (count << 16) | (count << 8) | count;
+ I915_WRITE(pal_prec_data, val);
+ pal_prec_data += 4;
+ count++;
+ }
+}
+
+static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
+ struct drm_crtc *crtc)
+{
+ enum pipe pipe;
+ int num_samples;
+ u32 mode, pal_prec_index, pal_prec_data, index;
+ u32 word = 0;
+ struct drm_palette *gamma_data;
+ struct drm_crtc_state *state = crtc->state;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_r32g32b32 *correction_values = NULL;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ gamma_data = (struct drm_palette *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+ num_samples = gamma_data->num_samples;
+
+ pal_prec_index = _PREC_PAL_INDEX(pipe);
+ pal_prec_data = _PREC_PAL_DATA(pipe);
+
+ correction_values = (struct drm_r32g32b32 *)&gamma_data->lut;
+ index = I915_READ(pal_prec_index);
+
+ switch (num_samples) {
+ case GAMMA_DISABLE_VALS:
+
+ /* Disable Gamma functionality on Pipe */
+ DRM_DEBUG_DRIVER("Disabling gamma on Pipe %c\n",
+ pipe_name(pipe));
+ mode = I915_READ(GAMMA_MODE(pipe));
+ if ((mode & GAMMA_MODE_MODE_MASK) == GAMMA_MODE_MODE_12BIT)
+ bdw_reset_gamma(dev_priv, pipe);
+ state->palette_after_ctm_blob = NULL;
+ word = GAMMA_MODE_MODE_8BIT;
+ break;
+
+ case BDW_8BIT_GAMMA_MAX_VALS:
+
+ /* Legacy palette */
+ bdw_write_8bit_gamma_legacy(dev, correction_values,
+ LGC_PALETTE(pipe, 0));
+ word = GAMMA_MODE_MODE_8BIT;
+ break;
+
+ case BDW_SPLITGAMMA_MAX_VALS:
+
+ index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE;
+ I915_WRITE(pal_prec_index, index);
+ bdw_write_10bit_gamma_precision(dev, correction_values,
+ pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);
+ word = GAMMA_MODE_MODE_SPLIT;
+ break;
+
+ case BDW_12BIT_GAMMA_MAX_VALS:
+
+ index |= BDW_INDEX_AUTO_INCREMENT;
+ index &= ~BDW_INDEX_SPLIT_MODE;
+ I915_WRITE(pal_prec_index, index);
+ bdw_write_12bit_gamma_precision(dev, correction_values,
+ pal_prec_data, pipe);
+ word = GAMMA_MODE_MODE_12BIT;
+ break;
+
+ case BDW_10BIT_GAMMA_MAX_VALS:
+ index |= BDW_INDEX_AUTO_INCREMENT;
+ index &= ~BDW_INDEX_SPLIT_MODE;
+ I915_WRITE(pal_prec_index, index);
+ bdw_write_10bit_gamma_precision(dev, correction_values,
+ pal_prec_data, BDW_10BIT_GAMMA_MAX_VALS);
+ word = GAMMA_MODE_MODE_10BIT;
+ break;
+
+ default:
+ DRM_ERROR("Invalid number of samples\n");
+ return -EINVAL;
+ }
+
+ /* Set gamma mode on pipe control reg */
+ mode = I915_READ(GAMMA_MODE(pipe));
+ mode &= ~GAMMA_MODE_MODE_MASK;
+ I915_WRITE(GAMMA_MODE(pipe), mode | word);
+ DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n",
+ pipe_name(pipe));
+ return 0;
+}
+
static s32 chv_prepare_csc_coeff(s64 csc_value)
{
s32 csc_int_value;
@@ -304,6 +587,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
/* Gamma correction is platform specific */
if (IS_CHERRYVIEW(dev))
ret = chv_set_gamma(dev, blob, crtc);
+ else if (IS_BROADWELL(dev) || IS_GEN9(dev))
+ ret = bdw_set_gamma(dev, blob, crtc);
if (ret)
DRM_ERROR("set Gamma correction failed\n");
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 271246a..6c7cb08 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -92,3 +92,9 @@
/* Gamma on BDW */
#define BDW_SPLITGAMMA_MAX_VALS 512
+#define BDW_8BIT_GAMMA_MAX_VALS 256
+#define BDW_10BIT_GAMMA_MAX_VALS 1024
+#define BDW_12BIT_GAMMA_MAX_VALS 513
+#define BDW_MAX_GAMMA ((1 << 24) - 1)
+#define BDW_INDEX_AUTO_INCREMENT (1 << 15)
+#define BDW_INDEX_SPLIT_MODE (1 << 31)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 20/22] drm/i915: BDW: Load degamma correction values
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (18 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 19/22] drm/i915: BDW: Pipe level Gamma correction Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 21/22] drm/i915: BDW: Pipe level degamma correction Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 22/22] drm/i915: BDW: Pipe level CSC correction Shashank Sharma
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.
This patch adds the no of coefficients(512) for degamma correction
as "num_samples_before_ctm" parameter in device info structures,
for BDW and higher platforms.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
drivers/gpu/drm/i915/intel_color_manager.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8beac5c..1c68e91 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -303,6 +303,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+ .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -316,6 +317,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+ .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -329,6 +331,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+ .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -342,6 +345,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+ .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -368,6 +372,7 @@ static const struct intel_device_info intel_skylake_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+ .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -382,6 +387,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+ .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -396,6 +402,7 @@ static const struct intel_device_info intel_broxton_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+ .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.num_pipes = 3,
.has_ddi = 1,
.has_fpga_dbg = 1,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 6c7cb08..e0c486e 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -98,3 +98,6 @@
#define BDW_MAX_GAMMA ((1 << 24) - 1)
#define BDW_INDEX_AUTO_INCREMENT (1 << 15)
#define BDW_INDEX_SPLIT_MODE (1 << 31)
+
+/* Degamma on BDW */
+#define BDW_DEGAMMA_MAX_VALS 512
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 21/22] drm/i915: BDW: Pipe level degamma correction
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (19 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 20/22] drm/i915: BDW: Load degamma correction values Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
2015-10-13 12:39 ` [PATCH v5 22/22] drm/i915: BDW: Pipe level CSC correction Shashank Sharma
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, avinash.reddy.palleti, indranil.mukherjee,
kausalmalladi, kiran.s.kumar, daniel.vetter, =gary.k.smith
BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied before Color Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
BDW/SKL/BXT platform
2. Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
---
drivers/gpu/drm/i915/intel_color_manager.c | 58 ++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index cf85bc3..42fd2f5 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -310,6 +310,62 @@ static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
return 0;
}
+static int bdw_set_degamma(struct drm_device *dev,
+ struct drm_property_blob *blob, struct drm_crtc *crtc)
+{
+ enum pipe pipe;
+ int num_samples;
+ u32 index, mode;
+ u32 pal_prec_index, pal_prec_data;
+ struct drm_palette *degamma_data;
+ struct drm_crtc_state *state = crtc->state;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_r32g32b32 *correction_values = NULL;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ degamma_data = (struct drm_palette *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+ num_samples = degamma_data->num_samples;
+
+ if (num_samples == GAMMA_DISABLE_VALS) {
+ /* Disable degamma on Pipe */
+ mode = I915_READ(GAMMA_MODE(pipe)) & ~GAMMA_MODE_MODE_MASK;
+ I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_8BIT);
+
+ state->palette_before_ctm_blob = NULL;
+ DRM_DEBUG_DRIVER("Disabling degamma on Pipe %c\n",
+ pipe_name(pipe));
+ return 0;
+ }
+
+ if (num_samples != BDW_SPLITGAMMA_MAX_VALS) {
+ DRM_ERROR("Invalid number of samples\n");
+ return -EINVAL;
+ }
+
+ pal_prec_index = _PREC_PAL_INDEX(pipe);
+ pal_prec_data = _PREC_PAL_DATA(pipe);
+ correction_values = degamma_data->lut;
+
+ index = I915_READ(pal_prec_index);
+ index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE;
+ I915_WRITE(pal_prec_index, index);
+
+ bdw_write_10bit_gamma_precision(dev, correction_values,
+ pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);
+
+ /* Enable degamma on Pipe */
+ mode = I915_READ(GAMMA_MODE(pipe));
+ mode &= ~GAMMA_MODE_MODE_MASK;
+ I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT);
+ DRM_DEBUG_DRIVER("degamma correction enabled on Pipe %c\n",
+ pipe_name(pipe));
+
+ return 0;
+}
+
static s32 chv_prepare_csc_coeff(s64 csc_value)
{
s32 csc_int_value;
@@ -601,6 +657,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
/* Degamma correction */
if (IS_CHERRYVIEW(dev))
ret = chv_set_degamma(dev, blob, crtc);
+ else if (IS_BROADWELL(dev) || IS_GEN9(dev))
+ ret = bdw_set_degamma(dev, blob, crtc);
if (ret)
DRM_ERROR("set degamma correction failed\n");
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 22/22] drm/i915: BDW: Pipe level CSC correction
2015-10-13 12:39 [PATCH v5 00/22] Color Management for DRM Shashank Sharma
` (20 preceding siblings ...)
2015-10-13 12:39 ` [PATCH v5 21/22] drm/i915: BDW: Pipe level degamma correction Shashank Sharma
@ 2015-10-13 12:39 ` Shashank Sharma
21 siblings, 0 replies; 23+ messages in thread
From: Shashank Sharma @ 2015-10-13 12:39 UTC (permalink / raw)
To: dri-devel, intel-gfx, emil.l.velikov, matthew.d.roper,
robert.bradford, jim.bish
Cc: annie.j.matheson, kausalmalladi, daniel.vetter, =gary.k.smith
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
BDW/SKL/BXT platform
2. Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
Signed-off-by: Kumar, Kiran S <kiran.s.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++
drivers/gpu/drm/i915/intel_color_manager.c | 113 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 8 ++
3 files changed, 128 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13e268a..fa1703d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8195,4 +8195,11 @@ enum skl_disp_power_wells {
(_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */
+#define CSC_COEFF_A 0x49010
+#define CSC_COEFF_B 0x49110
+#define CSC_COEFF_C 0x49210
+#define _PIPE_CSC_COEFF(pipe) \
+ (_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 42fd2f5..8fe0c0b 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -366,6 +366,117 @@ static int bdw_set_degamma(struct drm_device *dev,
return 0;
}
+static uint32_t bdw_prepare_csc_coeff(int64_t coeff)
+{
+ uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;
+ int32_t mantissa;
+ uint64_t abs_coeff;
+
+ coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);
+ coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);
+
+ abs_coeff = abs(coeff);
+ if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {
+ /* abs_coeff < 0.125 */
+ exponent_bits = 3;
+ ls_bit_pos = 19;
+ } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&
+ abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {
+ /* abs_coeff >= 0.125 && val < 0.25 */
+ exponent_bits = 2;
+ ls_bit_pos = 20;
+ } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)
+ && abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {
+ /* abs_coeff >= 0.25 && val < 0.5 */
+ exponent_bits = 1;
+ ls_bit_pos = 21;
+ } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)
+ && abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {
+ /* abs_coeff >= 0.5 && val < 1.0 */
+ exponent_bits = 0;
+ ls_bit_pos = 22;
+ } else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&
+ abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {
+ /* abs_coeff >= 1.0 && val < 2.0 */
+ exponent_bits = 7;
+ ls_bit_pos = 23;
+ } else {
+ /* abs_coeff >= 2.0 && val < 4.0 */
+ exponent_bits = 6;
+ ls_bit_pos = 24;
+ }
+
+ mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos, CSC_MAX_VALS);
+ if (coeff < 0)
+ sign_bit = 1;
+
+ reg_val = 0;
+ SET_BITS(reg_val, exponent_bits, 12, 3);
+ SET_BITS(reg_val, mantissa, 3, 9);
+ SET_BITS(reg_val, sign_bit, 15, 1);
+ return reg_val;
+}
+
+static int bdw_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
+ struct drm_crtc *crtc)
+{
+ enum pipe pipe;
+ enum plane plane;
+ int temp, word;
+ int count = 0;
+ u32 reg, plane_ctl, mode;
+ struct drm_ctm *csc_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ if (blob->length != sizeof(struct drm_ctm)) {
+ DRM_ERROR("Invalid length of data received\n");
+ return -EINVAL;
+ }
+
+ csc_data = (struct drm_ctm *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+ plane = to_intel_crtc(crtc)->plane;
+
+ plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
+ plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
+ I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
+ reg = _PIPE_CSC_COEFF(pipe);
+
+ /*
+ * BDW CSC correction coefficients are written like this:
+ * first two values go in a pair, into first register(0:15 and 16:31)
+ * third one alone goes into second register (16:31). Same
+ * pattern repeats for 3 times = 3 * 3 = 9 values.
+ */
+ while (count < CSC_MAX_VALS) {
+ word = 0;
+ temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]);
+ SET_BITS(word, temp, 16, 16);
+
+ temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]);
+ SET_BITS(word, temp, 0, 16);
+
+ I915_WRITE(reg, word);
+ reg += 4;
+
+ word = 0;
+ temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]);
+ SET_BITS(word, temp, 16, 16);
+ I915_WRITE(reg, word);
+ reg += 4;
+ }
+
+ /* Enable CSC functionality */
+ mode = I915_READ(PIPE_CSC_MODE(pipe));
+ mode |= CSC_POSITION_BEFORE_GAMMA;
+ I915_WRITE(PIPE_CSC_MODE(pipe), mode);
+ DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe));
+ return 0;
+}
+
static s32 chv_prepare_csc_coeff(s64 csc_value)
{
s32 csc_int_value;
@@ -671,6 +782,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
/* CSC correction */
if (IS_CHERRYVIEW(dev))
ret = chv_set_csc(dev, blob, crtc);
+ else if (IS_BROADWELL(dev) || IS_GEN9(dev))
+ ret = bdw_set_csc(dev, blob, crtc);
if (ret)
DRM_ERROR("set CSC correction failed\n");
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index e0c486e..6c20cf0 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -90,6 +90,14 @@
#define CGM_CSC_EN (1 << 1)
#define CGM_DEGAMMA_EN (1 << 0)
+/* BDW CSC */
+/* 1.0000000 in S31.32 format */
+#define BDW_CSC_COEFF_UNITY_VAL 0x100000000
+/* 3.9921875 in S31.32 format */
+#define BDW_CSC_COEFF_MAX_VAL 0x3FE000000
+/*-4.000000 in S31.32 format */
+#define BDW_CSC_COEFF_MIN_VAL 0xFFFFFFFC00000000
+
/* Gamma on BDW */
#define BDW_SPLITGAMMA_MAX_VALS 512
#define BDW_8BIT_GAMMA_MAX_VALS 256
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread