From: Philipp Zabel <p.zabel@pengutronix.de>
To: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Cc: cphealy@gmail.com, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 4/6] drm/bridge: tc358767: fix timing calculations
Date: Tue, 01 Aug 2017 15:12:28 +0200 [thread overview]
Message-ID: <1501593148.3159.44.camel@pengutronix.de> (raw)
In-Reply-To: <20170727124736.3854-5-andrey.gusakov@cogentembedded.com>
On Thu, 2017-07-27 at 15:47 +0300, Andrey Gusakov wrote:
> Fields in HTIM01 and HTIM02 regs should be even.
> Recomended thresh_dly value is max_tu_symbol.
What about the VSDELAY change? This should be mentioned in the commit
message.
> Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
> ---
> drivers/gpu/drm/bridge/tc358767.c | 34 ++++++++++++++++++++--------------
> 1 file changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 4aee6178d889..c657a00af508 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -659,6 +659,14 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
> int lower_margin = mode->vsync_start - mode->vdisplay;
> int vsync_len = mode->vsync_end - mode->vsync_start;
>
> + /*
> + * Recommended maximum number of symbols transferred in a transfer unit:
> + * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
> + * (output active video bandwidth in bytes))
> + * Must be less than tu_size.
> + */
> + max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
> +
> dev_dbg(tc->dev, "set mode %dx%d\n",
> mode->hdisplay, mode->vdisplay);
> dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
> @@ -668,13 +676,18 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
> dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
>
>
> - /* LCD Ctl Frame Size */
> - tc_write(VPCTRL0, (0x40 << 20) /* VSDELAY */ |
> + /*
> + * LCD Ctl Frame Size
> + * datasheet is not clear of vsdelay in case of DPI
> + * assume we do not need any delay when DPI is a source of
> + * sync signals
> + */
> + tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
VSDELAY is documented as the delay in pixel clocks between the time a
VSYNC/HSYNC Start DSI packet is received and the time HSYNC/VSYNC is
asserted in the DP output.
I assume that this field is just ignored in DPI mode.
> OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
> - tc_write(HTIM01, (left_margin << 16) | /* H back porch */
> - (hsync_len << 0)); /* Hsync */
> - tc_write(HTIM02, (right_margin << 16) | /* H front porch */
> - (mode->hdisplay << 0)); /* width */
> + tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
> + (ALIGN(hsync_len, 2) << 0)); /* Hsync */
> + tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */
> + (ALIGN(mode->hdisplay, 2) << 0)); /* width */
> tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
> (vsync_len << 0)); /* Vsync */
> tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
> @@ -693,7 +706,7 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
> /* DP Main Stream Attributes */
> vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
> tc_write(DP0_VIDSYNCDELAY,
> - (0x003e << 16) | /* thresh_dly */
> + (max_tu_symbol << 16) | /* thresh_dly */
> (vid_sync_dly << 0));
>
> tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
> @@ -709,13 +722,6 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
> tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
> DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
>
> - /*
> - * Recommended maximum number of symbols transferred in a transfer unit:
> - * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
> - * (output active video bandwidth in bytes))
> - * Must be less than tu_size.
> - */
> - max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
> tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
> BPC_8);
>
Otherwise,
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
regards
Philipp
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next prev parent reply other threads:[~2017-08-01 13:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-27 12:47 [PATCH 0/6] drm/bridge: tc358767: fixes and improvements Andrey Gusakov
2017-07-27 12:47 ` [PATCH 1/6] drm/bridge: tc358767: do no fail on hi-res displays Andrey Gusakov
2017-08-01 13:11 ` Philipp Zabel
2017-07-27 12:47 ` [PATCH 2/6] drm/bridge: tc358767: filter out too high modes Andrey Gusakov
2017-08-01 13:11 ` Philipp Zabel
2017-08-02 17:34 ` Andrey Gusakov
2017-07-27 12:47 ` [PATCH 3/6] drm/bridge: tc358767: fix DP0_MISC register set Andrey Gusakov
2017-08-01 13:11 ` Philipp Zabel
2017-07-27 12:47 ` [PATCH 4/6] drm/bridge: tc358767: fix timing calculations Andrey Gusakov
2017-08-01 13:12 ` Philipp Zabel [this message]
2017-07-27 12:47 ` [PATCH 5/6] drm/bridge: tc358767: fix AUXDATAn registers access Andrey Gusakov
2017-08-01 13:12 ` Philipp Zabel
2017-07-27 12:47 ` [PATCH 6/6] drm/bridge: tc358767: fix 1-lane behavior Andrey Gusakov
2017-08-01 13:13 ` Philipp Zabel
2017-08-01 5:06 ` [PATCH 0/6] drm/bridge: tc358767: fixes and improvements Archit Taneja
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