From: Philipp Zabel <p.zabel@pengutronix.de>
To: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Cc: cphealy@gmail.com, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 5/6] drm/bridge: tc358767: fix AUXDATAn registers access
Date: Tue, 01 Aug 2017 15:12:39 +0200 [thread overview]
Message-ID: <1501593159.3159.45.camel@pengutronix.de> (raw)
In-Reply-To: <20170727124736.3854-6-andrey.gusakov@cogentembedded.com>
On Thu, 2017-07-27 at 15:47 +0300, Andrey Gusakov wrote:
> First four bytes should go to DP0_AUXWDATA0. Due to bug if
> len > 4 first four bytes was writen to DP0_AUXWDATA1 and all
> data get shifted by 4 bytes. Fix it.
>
> Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
> ---
> drivers/gpu/drm/bridge/tc358767.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index c657a00af508..84b0b0fff854 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -318,7 +318,7 @@ static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
> tmp = (tmp << 8) | buf[i];
> i++;
> if (((i % 4) == 0) || (i == size)) {
> - tc_write(DP0_AUXWDATA(i >> 2), tmp);
> + tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
> tmp = 0;
> }
> }
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
regards
Philipp
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next prev parent reply other threads:[~2017-08-01 13:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-27 12:47 [PATCH 0/6] drm/bridge: tc358767: fixes and improvements Andrey Gusakov
2017-07-27 12:47 ` [PATCH 1/6] drm/bridge: tc358767: do no fail on hi-res displays Andrey Gusakov
2017-08-01 13:11 ` Philipp Zabel
2017-07-27 12:47 ` [PATCH 2/6] drm/bridge: tc358767: filter out too high modes Andrey Gusakov
2017-08-01 13:11 ` Philipp Zabel
2017-08-02 17:34 ` Andrey Gusakov
2017-07-27 12:47 ` [PATCH 3/6] drm/bridge: tc358767: fix DP0_MISC register set Andrey Gusakov
2017-08-01 13:11 ` Philipp Zabel
2017-07-27 12:47 ` [PATCH 4/6] drm/bridge: tc358767: fix timing calculations Andrey Gusakov
2017-08-01 13:12 ` Philipp Zabel
2017-07-27 12:47 ` [PATCH 5/6] drm/bridge: tc358767: fix AUXDATAn registers access Andrey Gusakov
2017-08-01 13:12 ` Philipp Zabel [this message]
2017-07-27 12:47 ` [PATCH 6/6] drm/bridge: tc358767: fix 1-lane behavior Andrey Gusakov
2017-08-01 13:13 ` Philipp Zabel
2017-08-01 5:06 ` [PATCH 0/6] drm/bridge: tc358767: fixes and improvements Archit Taneja
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