From: Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [v2 0/7] drm/msm/a6xx: System Cache Support
Date: Fri, 5 Oct 2018 18:38:28 +0530 [thread overview]
Message-ID: <1538744915-25490-1-git-send-email-smasetty@codeaurora.org> (raw)
Some hardware variants contain a system level cache or the last level
cache(llc). This cache is typically a large block which is shared by multiple
clients on the SOC. GPU uses the system cache to cache both the GPU data
buffers(like textures) as well the SMMU pagetables. This helps with
improved render performance as well as lower power consumption by reducing
the bus traffic to the system memory.
The system cache architecture allows the cache to be split into slices which
then be used by multiple SOC clients. This patch series is an effort to enable
and use two of those slices perallocated for the GPU, one for the GPU data
buffers and another for the GPU SMMU hardware pagetables.
v2: Fixed code review comments from previous round. The first version was posted
a few months ago, so this is a refresh of the previous series. Update code to
conform to the newer version of the core llcc driver. Minor tweaks and
adjustments here and there.
Testing: Nothing breaks, but need to profile DDR traffic to see the impact the
cache blocks are really making.
Please review...
Jordan Crouse (1):
soc: qcom: llcc-slice: Add error checks for API functions
Sharat Masetty (5):
drm/msm: rearrange the gpu_rmw() function
drm/msm/adreno: Add registers in the GPU CX domain
arm64:dts:sdm845: Add register range for gpu CX
drm/msm: Pass mmu features to generic layers
drm/msm/a6xx: Add support for using system cache(LLC)
Vivek Gautam (1):
iommu/arm-smmu: Add support to use Last level cache
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 +-
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 159 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 8 ++
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.c | 6 +-
drivers/gpu/drm/msm/msm_gpu.h | 6 +-
drivers/gpu/drm/msm/msm_iommu.c | 13 +++
drivers/gpu/drm/msm/msm_mmu.h | 14 +++
drivers/iommu/arm-smmu.c | 14 +++
drivers/iommu/io-pgtable-arm.c | 24 ++++-
drivers/iommu/io-pgtable.h | 4 +
drivers/soc/qcom/llcc-slice.c | 15 ++-
include/linux/iommu.h | 4 +
20 files changed, 276 insertions(+), 20 deletions(-)
--
1.9.1
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next reply other threads:[~2018-10-05 13:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-05 13:08 Sharat Masetty [this message]
[not found] ` <1538744915-25490-1-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-10-05 13:08 ` [v2 1/7] soc: qcom: llcc-slice: Add error checks for API functions Sharat Masetty
[not found] ` <1538744915-25490-2-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-11-14 18:00 ` Andy Gross
2018-10-05 13:08 ` [v2 5/7] arm64:dts:sdm845: Add register range for gpu CX Sharat Masetty
2018-10-05 13:08 ` [v2 6/7] drm/msm: Pass mmu features to generic layers Sharat Masetty
2018-10-05 13:08 ` [v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC) Sharat Masetty
2018-10-05 15:07 ` Jordan Crouse
[not found] ` <20181005150745.GJ31641-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org>
2018-10-08 13:59 ` Sharat Masetty
[not found] ` <4dd1439a-990e-6a34-0290-7adc4837ca7f-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-10-08 14:18 ` Jordan Crouse
2018-10-05 13:08 ` [v2 2/7] iommu/arm-smmu: Add support to use Last level cache Sharat Masetty
2018-10-05 13:08 ` [v2 3/7] drm/msm: rearrange the gpu_rmw() function Sharat Masetty
2018-10-05 13:08 ` [v2 4/7] drm/msm/adreno: Add registers in the GPU CX domain Sharat Masetty
[not found] ` <1538744915-25490-5-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-10-05 15:01 ` Jordan Crouse
[not found] ` <20181005150157.GI31641-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org>
2018-10-08 13:46 ` Sharat Masetty
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