From: Sharat Masetty <smasetty@codeaurora.org>
To: freedreno@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org,
Sharat Masetty <smasetty@codeaurora.org>,
dri-devel@lists.freedesktop.org
Subject: [v2 4/7] drm/msm/adreno: Add registers in the GPU CX domain
Date: Fri, 5 Oct 2018 18:38:32 +0530 [thread overview]
Message-ID: <1538744915-25490-5-git-send-email-smasetty@codeaurora.org> (raw)
In-Reply-To: <1538744915-25490-1-git-send-email-smasetty@codeaurora.org>
Add the registers needed for configuring the system cache slice info and
other parameters in the GPU.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index 2206765..2645b8f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -1780,5 +1780,8 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
+#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
+
+#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
#endif /* A6XX_XML */
--
1.9.1
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next prev parent reply other threads:[~2018-10-05 13:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-05 13:08 [v2 0/7] drm/msm/a6xx: System Cache Support Sharat Masetty
2018-10-05 13:08 ` [v2 2/7] iommu/arm-smmu: Add support to use Last level cache Sharat Masetty
2018-10-05 13:08 ` [v2 3/7] drm/msm: rearrange the gpu_rmw() function Sharat Masetty
2018-10-05 13:08 ` Sharat Masetty [this message]
[not found] ` <1538744915-25490-5-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-10-05 15:01 ` [v2 4/7] drm/msm/adreno: Add registers in the GPU CX domain Jordan Crouse
[not found] ` <20181005150157.GI31641-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org>
2018-10-08 13:46 ` Sharat Masetty
[not found] ` <1538744915-25490-1-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-10-05 13:08 ` [v2 1/7] soc: qcom: llcc-slice: Add error checks for API functions Sharat Masetty
[not found] ` <1538744915-25490-2-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-11-14 18:00 ` Andy Gross
2018-10-05 13:08 ` [v2 5/7] arm64:dts:sdm845: Add register range for gpu CX Sharat Masetty
2018-10-05 13:08 ` [v2 6/7] drm/msm: Pass mmu features to generic layers Sharat Masetty
2018-10-05 13:08 ` [v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC) Sharat Masetty
2018-10-05 15:07 ` Jordan Crouse
[not found] ` <20181005150745.GJ31641-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org>
2018-10-08 13:59 ` Sharat Masetty
[not found] ` <4dd1439a-990e-6a34-0290-7adc4837ca7f-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-10-08 14:18 ` Jordan Crouse
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