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From: "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 09/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW
Date: Wed, 18 Sep 2019 19:03:40 +0000	[thread overview]
Message-ID: <190062bdc035cc63008ef79956e8ed41782a6099.camel@intel.com> (raw)
In-Reply-To: <20190718145053.25808-10-ville.syrjala@linux.intel.com>

On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On HSW the pipe colorspace is configured via PIPECONF
> (as opposed to PIPEMISC in BDW+). Let's configure+readout
> that stuff correctly.
> 
> Enablling YCbCr 4:4:4 output will now be a simple matter of
Typo: Enablling -> Enabling
> setting crtc_state->output_format appropriately in the encoder
> .compute_config().
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h              |  1 +
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1dd1aa29a649..bd3ff96c1618 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9430,6 +9430,10 @@ static void haswell_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
>  	else
>  		val |= PIPECONF_PROGRESSIVE;
>  
> +	if (IS_HASWELL(dev_priv) &&
> +	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> +		val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
> +
>  	I915_WRITE(PIPECONF(cpu_transcoder), val);
>  	POSTING_READ(PIPECONF(cpu_transcoder));
>  }
> @@ -10423,7 +10427,14 @@ static bool haswell_get_pipe_config(struct
> intel_crtc *crtc,
>  
>  	intel_get_pipe_src_size(crtc, pipe_config);
>  
> -	if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
> +	if (IS_HASWELL(dev_priv)) {
> +		u32 tmp = I915_READ(PIPECONF(pipe_config-
> >cpu_transcoder));
> +
> +		if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
> +			pipe_config->output_format =
> INTEL_OUTPUT_FORMAT_YCBCR444;
> +		else
> +			pipe_config->output_format =
> INTEL_OUTPUT_FORMAT_RGB;
> +	} else {
>  		pipe_config->output_format =
>  			bdw_get_pipemisc_output_format(crtc);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 66f7f417231f..58471312b8b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5712,6 +5712,7 @@ enum {
>  #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
>  #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
>  #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
> +#define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only
> */
>  #define   PIPECONF_BPC_MASK	(0x7 << 5)
>  #define   PIPECONF_8BPC		(0 << 5)
>  #define   PIPECONF_10BPC	(1 << 5)
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  reply	other threads:[~2019-09-18 19:03 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-18 14:50 [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Ville Syrjala
2019-07-18 14:50 ` [PATCH 01/12] drm/dp: Add definitons for MSA MISC bits Ville Syrjala
2019-09-18 18:55   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 02/12] drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication Ville Syrjala
2019-09-18 18:59   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 03/12] drm/i915: Fix AVI infoframe quantization range for YCbCr output Ville Syrjala
2019-09-20 12:56   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 04/12] drm/i915: Extract intel_hdmi_limited_color_range() Ville Syrjala
2019-09-18 19:00   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 05/12] drm/i915: Never set limited_color_range=true for YCbCr output Ville Syrjala
2019-07-18 16:45   ` [PATCH v2 " Ville Syrjala
2019-09-18 19:01     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 06/12] drm/i915: Switch to using DP_MSA_MISC_* defines Ville Syrjala
2019-09-18 19:01   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 07/12] drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout Ville Syrjala
2019-09-18 19:02   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 08/12] drm/i915: Simplify intel_get_crtc_ycbcr_config() Ville Syrjala
2019-09-18 19:02   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 09/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW Ville Syrjala
2019-09-18 19:03   ` Mun, Gwan-gyeong [this message]
2019-09-20 12:20     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 10/12] drm/i915: Document ILK+ pipe csc matrix better Ville Syrjala
2019-09-20 14:24   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-09-20 14:29     ` Ville Syrjälä
2019-07-18 14:50 ` [PATCH 11/12] drm/i915: Set up ILK/SNB csc unit properly for YCbCr output Ville Syrjala
2019-09-20 12:19   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 12/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB Ville Syrjala
2019-09-18 19:05   ` Mun, Gwan-gyeong
2019-09-20 12:21     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-09-20 18:48 ` [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Ville Syrjälä

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