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From: "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 02/12] drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication
Date: Wed, 18 Sep 2019 18:59:13 +0000	[thread overview]
Message-ID: <4ec2dea534f326ea4db0d7ce73b73bcc2c921b87.camel@intel.com> (raw)
In-Reply-To: <20190718145053.25808-3-ville.syrjala@linux.intel.com>

On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Looks like we're currently setting the MSA to xvYCC BT.709 instead
> of the YCbCr BT.601 claimed by the comment. But even that comment
> is wrong since we configure the CSC matrix to BT.709.
> 
> Let's remove the bogus statement from the comment and fix the
> MSA to indicate YCbCr BT.709 so that it matches the actual
> pixel data we're transmitting.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
>  drivers/gpu/drm/i915/i915_reg.h          | 3 ++-
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 18bc0f2690c9..157c5851a688 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1730,10 +1730,12 @@ void intel_ddi_set_pipe_settings(const struct
> intel_crtc_state *crtc_state)
>  	/*
>  	 * As per DP 1.2 spec section 2.3.4.3 while sending
>  	 * YCBCR 444 signals we should program MSA MISC1/0 fields with
> -	 * colorspace information. The output colorspace encoding is
> BT601.
> +	 * colorspace information.
>  	 */
>  	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
> -		temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
> +		temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR
> |
> +			TRANS_MSA_YCBCR_BT709;
> +
>  	/*
>  	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for
> Indication
>  	 * of Color Encoding Format and Content Color Gamut] while
> sending
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index fdd9bc01e694..35133b2ef6c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9605,7 +9605,8 @@ enum skl_power_gate {
>  
>  #define  TRANS_MSA_SYNC_CLK		(1 << 0)
>  #define  TRANS_MSA_SAMPLING_444		(2 << 1)
> -#define  TRANS_MSA_CLRSP_YCBCR		(2 << 3)
> +#define  TRANS_MSA_CLRSP_YCBCR		(1 << 3)
> +#define  TRANS_MSA_YCBCR_BT709		(1 << 4)
>  #define  TRANS_MSA_6_BPC		(0 << 5)
>  #define  TRANS_MSA_8_BPC		(1 << 5)
>  #define  TRANS_MSA_10_BPC		(2 << 5)
The changes look good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
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  reply	other threads:[~2019-09-18 18:59 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-18 14:50 [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Ville Syrjala
2019-07-18 14:50 ` [PATCH 01/12] drm/dp: Add definitons for MSA MISC bits Ville Syrjala
2019-09-18 18:55   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 02/12] drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication Ville Syrjala
2019-09-18 18:59   ` Mun, Gwan-gyeong [this message]
2019-07-18 14:50 ` [PATCH 03/12] drm/i915: Fix AVI infoframe quantization range for YCbCr output Ville Syrjala
2019-09-20 12:56   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 04/12] drm/i915: Extract intel_hdmi_limited_color_range() Ville Syrjala
2019-09-18 19:00   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 05/12] drm/i915: Never set limited_color_range=true for YCbCr output Ville Syrjala
2019-07-18 16:45   ` [PATCH v2 " Ville Syrjala
2019-09-18 19:01     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 06/12] drm/i915: Switch to using DP_MSA_MISC_* defines Ville Syrjala
2019-09-18 19:01   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 07/12] drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout Ville Syrjala
2019-09-18 19:02   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 08/12] drm/i915: Simplify intel_get_crtc_ycbcr_config() Ville Syrjala
2019-09-18 19:02   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 09/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW Ville Syrjala
2019-09-18 19:03   ` Mun, Gwan-gyeong
2019-09-20 12:20     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 10/12] drm/i915: Document ILK+ pipe csc matrix better Ville Syrjala
2019-09-20 14:24   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-09-20 14:29     ` Ville Syrjälä
2019-07-18 14:50 ` [PATCH 11/12] drm/i915: Set up ILK/SNB csc unit properly for YCbCr output Ville Syrjala
2019-09-20 12:19   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 12/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB Ville Syrjala
2019-09-18 19:05   ` Mun, Gwan-gyeong
2019-09-20 12:21     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-09-20 18:48 ` [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Ville Syrjälä

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