[PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC Gamma LUT

[PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC Gamma LUT

[Sean Paul]

From: Sean Paul <seanpaul@google.com>

Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming
is active by clamping Segment 2 to the last user-provided LUT entry
value instead of hardcoding it to 1.0 (1 << 24).

Signed-off-by: Sean Paul <seanpaul@google.com>
Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-sean@poorly.run/ #v1
Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-1-sean@poorly.run/ #v2

Changes in v2:
- Split out into separate patches for pre/post csc fixes
- Dropped loop bounds fix in favor of [1]
Changes in v3:
- None

[1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
---
 drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 7ef870cd9a16..7185f3628dcf 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -4038,11 +4038,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
 						   lut_val);
 			}
 
-			/* Segment 2 */
+			/* Segment 2 - clamp to the last LUT value to prevent step discontinuity */
 			do {
 				intel_de_write_dsb(display, dsb,
 						   PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
-						   (1 << 24));
+						   lut_val);
 			} while (i++ < 34);
 		} else {
 			/*TODO: Add for segment 0 */
-- 
Sean Paul, Software Engineer, Google / Chromium OS

[PATCH v3 2/2] drm/i915/color: Fix step discontinuity in Pre-CSC Gamma LUT

[Sean Paul]

From: Sean Paul <seanpaul@google.com>

Clamp Segment 2 to the last user-provided LUT entry value instead of
hardcoding it to 1.0 (1 << 24) to fix a step discontinuity.

Signed-off-by: Sean Paul <seanpaul@google.com>
Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-sean@poorly.run/ #v1
Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-2-sean@poorly.run/ #v2

Changes in v2:
- Split out into separate patches for pre/post csc fixes
- Dropped loop bounds fix in favor of [1]
Changes in v3:
- Fix stale commit message

[1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
---
 drivers/gpu/drm/i915/display/intel_color.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 7185f3628dcf..458508bcf1f4 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3968,6 +3968,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
 	enum plane_id plane = to_intel_plane(state->plane)->id;
 	const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
 	u32 i, lut_size;
+	u32 lut_val = 1 << 24;
 
 	if (icl_is_hdr_plane(display, plane)) {
 		lut_size = 128;
@@ -3978,7 +3979,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
 
 		if (pre_csc_lut) {
 			for (i = 0; i < lut_size; i++) {
-				u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
+				lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
 
 				intel_de_write_dsb(display, dsb,
 						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
@@ -3990,7 +3991,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
 			do {
 				intel_de_write_dsb(display, dsb,
 						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
-						   (1 << 24));
+						   lut_val);
 			} while (i++ < 130);
 		} else {
 			for (i = 0; i < lut_size; i++) {
-- 
Sean Paul, Software Engineer, Google / Chromium OS

RE: [PATCH v3 2/2] drm/i915/color: Fix step discontinuity in Pre-CSC Gamma LUT

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Sean Paul
> Sent: Friday, May 29, 2026 4:38 AM
> To: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Borah, Chaitanya
> Kumar <chaitanya.kumar.borah@intel.com>
> Cc: Sean Paul <seanpaul@google.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Tvrtko Ursulin
> <tursulin@ursulin.net>; David Airlie <airlied@gmail.com>; Simona Vetter
> <simona@ffwll.ch>; intel-xe@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Subject: [PATCH v3 2/2] drm/i915/color: Fix step discontinuity in Pre-CSC
> Gamma LUT
> 
> From: Sean Paul <seanpaul@google.com>
> 
> Clamp Segment 2 to the last user-provided LUT entry value instead of hardcoding
> it to 1.0 (1 << 24) to fix a step discontinuity.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com.

> Signed-off-by: Sean Paul <seanpaul@google.com>
> Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-
> sean@poorly.run/ #v1
> Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-2-
> sean@poorly.run/ #v2
> 
> Changes in v2:
> - Split out into separate patches for pre/post csc fixes
> - Dropped loop bounds fix in favor of [1] Changes in v3:
> - Fix stale commit message
> 
> [1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 7185f3628dcf..458508bcf1f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -3968,6 +3968,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb
> *dsb,
>  	enum plane_id plane = to_intel_plane(state->plane)->id;
>  	const struct drm_color_lut32 *pre_csc_lut = plane_state-
> >hw.degamma_lut->data;
>  	u32 i, lut_size;
> +	u32 lut_val = 1 << 24;
> 
>  	if (icl_is_hdr_plane(display, plane)) {
>  		lut_size = 128;
> @@ -3978,7 +3979,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb
> *dsb,
> 
>  		if (pre_csc_lut) {
>  			for (i = 0; i < lut_size; i++) {
> -				u32 lut_val =
> drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> +				lut_val =
> drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> 
>  				intel_de_write_dsb(display, dsb,
> 
> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), @@ -3990,7 +3991,7
> @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
>  			do {
>  				intel_de_write_dsb(display, dsb,
> 
> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> -						   (1 << 24));
> +						   lut_val);
>  			} while (i++ < 130);
>  		} else {
>  			for (i = 0; i < lut_size; i++) {
> --
> Sean Paul, Software Engineer, Google / Chromium OS

Re: [PATCH v3 2/2] drm/i915/color: Fix step discontinuity in Pre-CSC Gamma LUT

[Borah, Chaitanya Kumar]

On 5/29/2026 4:37 AM, Sean Paul wrote:
> From: Sean Paul <seanpaul@google.com>
> 
> Clamp Segment 2 to the last user-provided LUT entry value instead of
> hardcoding it to 1.0 (1 << 24) to fix a step discontinuity.
> 

It defintely make sense to me that the point corresponding to 1.0 should 
be programmed to the max lut value that user-space provide. I am not 
quite sure what should be the case for 3.0 and 7.0, however, I presume 
it should be harmless for now. So as of now LGTM.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> Signed-off-by: Sean Paul <seanpaul@google.com>
> Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-sean@poorly.run/ #v1
> Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-2-sean@poorly.run/ #v2
> 
> Changes in v2:
> - Split out into separate patches for pre/post csc fixes
> - Dropped loop bounds fix in favor of [1]
> Changes in v3:
> - Fix stale commit message
> 
> [1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 7185f3628dcf..458508bcf1f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -3968,6 +3968,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
>   	enum plane_id plane = to_intel_plane(state->plane)->id;
>   	const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
>   	u32 i, lut_size;
> +	u32 lut_val = 1 << 24;
>   
>   	if (icl_is_hdr_plane(display, plane)) {
>   		lut_size = 128;
> @@ -3978,7 +3979,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
>   
>   		if (pre_csc_lut) {
>   			for (i = 0; i < lut_size; i++) {
> -				u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> +				lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
>   
>   				intel_de_write_dsb(display, dsb,
>   						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> @@ -3990,7 +3991,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
>   			do {
>   				intel_de_write_dsb(display, dsb,
>   						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> -						   (1 << 24));
> +						   lut_val);
>   			} while (i++ < 130);
>   		} else {
>   			for (i = 0; i < lut_size; i++) {

RE: [PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC Gamma LUT

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Sean Paul
> Sent: Friday, May 29, 2026 4:38 AM
> To: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Borah, Chaitanya
> Kumar <chaitanya.kumar.borah@intel.com>
> Cc: Sean Paul <seanpaul@google.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Tvrtko Ursulin
> <tursulin@ursulin.net>; David Airlie <airlied@gmail.com>; Simona Vetter
> <simona@ffwll.ch>; intel-xe@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Subject: [PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC
> Gamma LUT
> 
> From: Sean Paul <seanpaul@google.com>
> 
> Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming is
> active by clamping Segment 2 to the last user-provided LUT entry value instead of
> hardcoding it to 1.0 (1 << 24).
> 

Hi Sean,
Yeah it was done as UAPI was limited to 0.16 format and hence 1.0 value was
Not possible through UAPI. Expectation was that userspace will send LUTs in range
Of 0 to 1.0 but agree it can limit the end point, so we can go with the whatever highest
value userspace provides. We are planning a new LUT type to represent segmented LUTS,
We can make this better including precision reporting and LUT caps. 
But till then, ok to go with your change.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Sean Paul <seanpaul@google.com>
> Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-
> sean@poorly.run/ #v1
> Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-1-
> sean@poorly.run/ #v2
> 
> Changes in v2:
> - Split out into separate patches for pre/post csc fixes
> - Dropped loop bounds fix in favor of [1] Changes in v3:
> - None
> 
> [1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 7ef870cd9a16..7185f3628dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -4038,11 +4038,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb
> *dsb,
>  						   lut_val);
>  			}
> 
> -			/* Segment 2 */
> +			/* Segment 2 - clamp to the last LUT value to prevent step
> +discontinuity */
>  			do {
>  				intel_de_write_dsb(display, dsb,
> 
> PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> -						   (1 << 24));
> +						   lut_val);
>  			} while (i++ < 34);
>  		} else {
>  			/*TODO: Add for segment 0 */
> --
> Sean Paul, Software Engineer, Google / Chromium OS

Re: [PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC Gamma LUT

[Borah, Chaitanya Kumar]

Hi Sean,

On 5/29/2026 4:37 AM, Sean Paul wrote:
> From: Sean Paul <seanpaul@google.com>
> 
> Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming
> is active by clamping Segment 2 to the last user-provided LUT entry
> value instead of hardcoding it to 1.0 (1 << 24).
> 
> Signed-off-by: Sean Paul <seanpaul@google.com>
> Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-sean@poorly.run/ #v1
> Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-1-sean@poorly.run/ #v2
> 

We might need to trigger a CI run on intel-xe/intel-gfx since your 
"poorly.run" e-mail id (unlike your google.com id) is not part of the 
"allow-list".

Otherwise, with the assumption made in [1], LGTM

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

[1] 
https://lore.kernel.org/intel-gfx/DM4PR11MB636049BA2E517A22FB43A404F4142@DM4PR11MB6360.namprd11.prod.outlook.com/T/#t

> Changes in v2:
> - Split out into separate patches for pre/post csc fixes
> - Dropped loop bounds fix in favor of [1]
> Changes in v3:
> - None
> 
> [1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 7ef870cd9a16..7185f3628dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -4038,11 +4038,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
>   						   lut_val);
>   			}
>   
> -			/* Segment 2 */
> +			/* Segment 2 - clamp to the last LUT value to prevent step discontinuity */
>   			do {
>   				intel_de_write_dsb(display, dsb,
>   						   PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> -						   (1 << 24));
> +						   lut_val);
>   			} while (i++ < 34);
>   		} else {
>   			/*TODO: Add for segment 0 */

RE: [PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC Gamma LUT

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Sean Paul
> Sent: Friday, May 29, 2026 4:38 AM
> To: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Borah, Chaitanya
> Kumar <chaitanya.kumar.borah@intel.com>
> Cc: Sean Paul <seanpaul@google.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Tvrtko Ursulin
> <tursulin@ursulin.net>; David Airlie <airlied@gmail.com>; Simona Vetter
> <simona@ffwll.ch>; intel-xe@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Subject: [PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC
> Gamma LUT
> 
> From: Sean Paul <seanpaul@google.com>
> 
> Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming is
> active by clamping Segment 2 to the last user-provided LUT entry value instead of
> hardcoding it to 1.0 (1 << 24).
> 
> Signed-off-by: Sean Paul <seanpaul@google.com>
> Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-
> sean@poorly.run/ #v1
> Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-1-
> sean@poorly.run/ #v2
> 
> Changes in v2:
> - Split out into separate patches for pre/post csc fixes
> - Dropped loop bounds fix in favor of [1] Changes in v3:
> - None

Patches in series pushed to drm-intel-next. Thanks for the fixes.

Regards,
Uma Shankar

> [1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 7ef870cd9a16..7185f3628dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -4038,11 +4038,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb
> *dsb,
>  						   lut_val);
>  			}
> 
> -			/* Segment 2 */
> +			/* Segment 2 - clamp to the last LUT value to prevent step
> +discontinuity */
>  			do {
>  				intel_de_write_dsb(display, dsb,
> 
> PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> -						   (1 << 24));
> +						   lut_val);
>  			} while (i++ < 34);
>  		} else {
>  			/*TODO: Add for segment 0 */
> --
> Sean Paul, Software Engineer, Google / Chromium OS