[PATCH 0/3] Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

[PATCH 0/3] Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

These patches enable packed format YUV422-Y210, Y212 and Y216
and YUV444-Y410, Y412, Y416 for 10, 12 and 16 bits for ICL+.

IGT needs libraries for Pixman and Cairo to support more than 8bpc.
Work going on from Maarten Lankhorst.

Initial review for Y2xx done https://patchwork.freedesktop.org/series/48729/
However, submitting new patch series consolidating Y2xx and Y4xx.

Swati Sharma (3):
  drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
  drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control
    definitions
  drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for
    universal planes

 drivers/gpu/drm/drm_fourcc.c         |  6 ++++
 drivers/gpu/drm/i915/i915_reg.h      |  6 ++++
 drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 61 ++++++++++++++++++++++++++++++++++--
 include/uapi/drm/drm_fourcc.h        | 18 ++++++++++-
 5 files changed, 118 insertions(+), 3 deletions(-)

-- 
1.9.1

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[PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.

Y210:	For each component, valid data occupies MSB 10 bits.
	LSB 6 bits are filled with zeroes.
Y212:	For each component, valid data occupies MSB 12 bits.
	LSB 4 bits are filled with zeroes.
Y216:	For each component valid data occupies 16 bits,
	doesn't require any padding bits.

First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.

The following pixel formats are packed format that follows 4:4:4
chroma sampling. Channels are arranged in the order UYVA in
increasing memory order.

Y410:	Each color component occupies 10 bits and X component
	takes 2 bits, thus each pixel occupies 32 bits.
Y412:   Each color component is 16 bits where valid data
	occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
	Thus, each pixel occupies 64 bits.
Y416:   Each color component occupies 16 bits for valid data,
	doesn't require any padding bits. Thus, each pixel
	occupies 64 bits.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/drm_fourcc.c  |  6 ++++++
 include/uapi/drm/drm_fourcc.h | 18 +++++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..639ab93 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_XYUV8888,	.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y410,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y412,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y416,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_Y0L0,		.depth = 0,  .num_planes = 1,
 		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
 		  .hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0b44260..97249a5 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,7 +151,23 @@
 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
 
 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV8888		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+
+/*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
+#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
+/*
+ * packed Y4xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb except Y410
+ */
+#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] X:V:Y:U 2:10:10:10 little endian */
+#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [64:0] X:V:Y:U 16:16:16:16 little endian */
 
 /*
  * packed YCbCr420 2x2 tiled formats
-- 
1.9.1

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[PATCH 2/3] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and
16 bits)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d9..7150bc5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6546,6 +6546,12 @@ enum {
 #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
 #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
+#define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
+#define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
+#define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
+#define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
+#define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
+#define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
-- 
1.9.1

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[PATCH 3/3] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 61 ++++++++++++++++++++++++++++++++++--
 2 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1cc441f..e7a86c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2633,6 +2633,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 		return DRM_FORMAT_RGB565;
 	case PLANE_CTL_FORMAT_NV12:
 		return DRM_FORMAT_NV12;
+	case PLANE_CTL_FORMAT_Y210:
+		return DRM_FORMAT_Y210;
+	case PLANE_CTL_FORMAT_Y212:
+		return DRM_FORMAT_Y212;
+	case PLANE_CTL_FORMAT_Y216:
+		return DRM_FORMAT_Y216;
+	case PLANE_CTL_FORMAT_Y410:
+		return DRM_FORMAT_Y410;
+	case PLANE_CTL_FORMAT_Y412:
+		return DRM_FORMAT_Y412;
+	case PLANE_CTL_FORMAT_Y416:
+		return DRM_FORMAT_Y416;
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
@@ -3529,6 +3541,18 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
+	case DRM_FORMAT_Y210:
+		return PLANE_CTL_FORMAT_Y210;
+	case DRM_FORMAT_Y212:
+		return PLANE_CTL_FORMAT_Y212;
+	case DRM_FORMAT_Y216:
+		return PLANE_CTL_FORMAT_Y216;
+	case DRM_FORMAT_Y410:
+		return PLANE_CTL_FORMAT_Y410;
+	case DRM_FORMAT_Y412:
+		return PLANE_CTL_FORMAT_Y412;
+	case DRM_FORMAT_Y416:
+		return PLANE_CTL_FORMAT_Y416;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -5022,6 +5046,12 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
+	case DRM_FORMAT_Y410:
+	case DRM_FORMAT_Y412:
+	case DRM_FORMAT_Y416:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8f3982c..f1bc46d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1750,6 +1750,27 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
 	DRM_FORMAT_VYUY,
 };
 
+static const uint32_t icl_plane_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+	DRM_FORMAT_Y410,
+	DRM_FORMAT_Y412,
+	DRM_FORMAT_Y416,
+};
+
 static const uint32_t skl_planar_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
@@ -1766,6 +1787,28 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
 	DRM_FORMAT_NV12,
 };
 
+static const uint32_t icl_planar_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+	DRM_FORMAT_Y410,
+	DRM_FORMAT_Y412,
+	DRM_FORMAT_Y416,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1904,6 +1947,12 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
+	case DRM_FORMAT_Y410:
+	case DRM_FORMAT_Y412:
+	case DRM_FORMAT_Y416:
 	case DRM_FORMAT_NV12:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
@@ -2045,8 +2094,16 @@ struct intel_plane *
 		plane->update_slave = icl_update_slave;
 
 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
-		formats = skl_planar_formats;
-		num_formats = ARRAY_SIZE(skl_planar_formats);
+		if (INTEL_GEN(dev_priv) >= 11) {
+			formats = icl_planar_formats;
+			num_formats = ARRAY_SIZE(icl_planar_formats);
+		} else {
+			formats = skl_planar_formats;
+			num_formats = ARRAY_SIZE(skl_planar_formats);
+		}
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		formats = icl_plane_formats;
+		num_formats = ARRAY_SIZE(icl_plane_formats);
 	} else {
 		formats = skl_plane_formats;
 		num_formats = ARRAY_SIZE(skl_plane_formats);
-- 
1.9.1

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Re: [PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

[Juha-Pekka Heikkila]

On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> The following pixel formats are packed format that follows 4:2:2
> chroma sampling. For memory represenation each component is
> allocated 16 bits each. Thus each pixel occupies 32bit.
> 
> Y210:	For each component, valid data occupies MSB 10 bits.
> 	LSB 6 bits are filled with zeroes.
> Y212:	For each component, valid data occupies MSB 12 bits.
> 	LSB 4 bits are filled with zeroes.
> Y216:	For each component valid data occupies 16 bits,
> 	doesn't require any padding bits.
> 
> First 16 bits stores the Y value and the next 16 bits stores one
> of the chroma samples alternatively. The first luma sample will
> be accompanied by first U sample and second luma sample is
> accompanied by the first V sample.
> 
> The following pixel formats are packed format that follows 4:4:4
> chroma sampling. Channels are arranged in the order UYVA in
> increasing memory order.
> 
> Y410:	Each color component occupies 10 bits and X component
> 	takes 2 bits, thus each pixel occupies 32 bits.
> Y412:   Each color component is 16 bits where valid data
> 	occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
> 	Thus, each pixel occupies 64 bits.
> Y416:   Each color component occupies 16 bits for valid data,
> 	doesn't require any padding bits. Thus, each pixel
> 	occupies 64 bits.
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/drm_fourcc.c  |  6 ++++++
>   include/uapi/drm/drm_fourcc.h | 18 +++++++++++++++++-
>   2 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index d90ee03..639ab93 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
>   		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>   		{ .format = DRM_FORMAT_XYUV8888,	.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>   		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y410,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y412,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y416,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>   		{ .format = DRM_FORMAT_Y0L0,		.depth = 0,  .num_planes = 1,
>   		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
>   		  .hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 0b44260..97249a5 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -151,7 +151,23 @@
>   #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>   
>   #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> -#define DRM_FORMAT_XYUV8888		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
> +
> +/*
> + * packed Y2xx indicate for each component, xx valid data occupy msb
> + * 16-xx padding occupy lsb
> + */
> +#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
> +#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
> +#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
> +
> +/*
> + * packed Y4xx indicate for each component, xx valid data occupy msb
> + * 16-xx padding occupy lsb except Y410
> + */
> +#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] X:V:Y:U 2:10:10:10 little endian */
> +#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
> +#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [64:0] X:V:Y:U 16:16:16:16 little endian */
^^
[63:0] maybe?

/Juha-Pekka

>   
>   /*
>    * packed YCbCr420 2x2 tiled formats
> 

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Re: [PATCH 2/3] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

[Juha-Pekka Heikkila]

On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and
> 16 bits)
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44958d9..7150bc5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6546,6 +6546,12 @@ enum {
>   #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>   #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
>   #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
> +#define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
> +#define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
> +#define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
> +#define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
> +#define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
> +#define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
>   #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
>   #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
>   #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
> 

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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Re: [PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

[Sharma, Swati2]

On 11-Jan-19 6:17 PM, Juha-Pekka Heikkila wrote:
> On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> The following pixel formats are packed format that follows 4:2:2
>> chroma sampling. For memory represenation each component is
>> allocated 16 bits each. Thus each pixel occupies 32bit.
>>
>> Y210:    For each component, valid data occupies MSB 10 bits.
>>     LSB 6 bits are filled with zeroes.
>> Y212:    For each component, valid data occupies MSB 12 bits.
>>     LSB 4 bits are filled with zeroes.
>> Y216:    For each component valid data occupies 16 bits,
>>     doesn't require any padding bits.
>>
>> First 16 bits stores the Y value and the next 16 bits stores one
>> of the chroma samples alternatively. The first luma sample will
>> be accompanied by first U sample and second luma sample is
>> accompanied by the first V sample.
>>
>> The following pixel formats are packed format that follows 4:4:4
>> chroma sampling. Channels are arranged in the order UYVA in
>> increasing memory order.
>>
>> Y410:    Each color component occupies 10 bits and X component
>>     takes 2 bits, thus each pixel occupies 32 bits.
>> Y412:   Each color component is 16 bits where valid data
>>     occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
>>     Thus, each pixel occupies 64 bits.
>> Y416:   Each color component occupies 16 bits for valid data,
>>     doesn't require any padding bits. Thus, each pixel
>>     occupies 64 bits.
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>>   drivers/gpu/drm/drm_fourcc.c  |  6 ++++++
>>   include/uapi/drm/drm_fourcc.h | 18 +++++++++++++++++-
>>   2 files changed, 23 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index d90ee03..639ab93 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -226,6 +226,12 @@ const struct drm_format_info 
>> *__drm_format_info(u32 format)
>>           { .format = DRM_FORMAT_VYUY,        .depth = 0, .num_planes 
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>>           { .format = DRM_FORMAT_XYUV8888,    .depth = 0, .num_planes 
>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>>           { .format = DRM_FORMAT_AYUV,        .depth = 0, .num_planes 
>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, 
>> .is_yuv = true },
>> +        { .format = DRM_FORMAT_Y210,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y212,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y216,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y410,            .depth = 0, 
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y412,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y416,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = 
>> true },
>>           { .format = DRM_FORMAT_Y0L0,        .depth = 0, .num_planes 
>> = 1,
>>             .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, 
>> .block_h = { 2, 0, 0 },
>>             .hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
>> diff --git a/include/uapi/drm/drm_fourcc.h 
>> b/include/uapi/drm/drm_fourcc.h
>> index 0b44260..97249a5 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -151,7 +151,23 @@
>>   #define DRM_FORMAT_VYUY        fourcc_code('V', 'Y', 'U', 'Y') /* 
>> [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>>     #define DRM_FORMAT_AYUV        fourcc_code('A', 'Y', 'U', 'V') /* 
>> [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>> -#define DRM_FORMAT_XYUV8888        fourcc_code('X', 'Y', 'U', 'V') 
>> /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
>> +#define DRM_FORMAT_XYUV8888    fourcc_code('X', 'Y', 'U', 'V') /* 
>> [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
>> +
>> +/*
>> + * packed Y2xx indicate for each component, xx valid data occupy msb
>> + * 16-xx padding occupy lsb
>> + */
>> +#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* 
>> [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
>> +#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* 
>> [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
>> +#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* 
>> [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
>> +
>> +/*
>> + * packed Y4xx indicate for each component, xx valid data occupy msb
>> + * 16-xx padding occupy lsb except Y410
>> + */
>> +#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* 
>> [31:0] X:V:Y:U 2:10:10:10 little endian */
>> +#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* 
>> [64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
>> +#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* 
>> [64:0] X:V:Y:U 16:16:16:16 little endian */
> ^^
> [63:0] maybe?
ohh sorry. Will correct in next patch series.
>
> /Juha-Pekka
>
>>     /*
>>    * packed YCbCr420 2x2 tiled formats
>>
>

-- 
Thanks and Regards,
Swati

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Re: [PATCH 3/3] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

[Juha-Pekka Heikkila]

On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++
>   drivers/gpu/drm/i915/intel_sprite.c  | 61 ++++++++++++++++++++++++++++++++++--
>   2 files changed, 89 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1cc441f..e7a86c6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2633,6 +2633,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>   		return DRM_FORMAT_RGB565;
>   	case PLANE_CTL_FORMAT_NV12:
>   		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_Y210:
> +		return DRM_FORMAT_Y210;
> +	case PLANE_CTL_FORMAT_Y212:
> +		return DRM_FORMAT_Y212;
> +	case PLANE_CTL_FORMAT_Y216:
> +		return DRM_FORMAT_Y216;
> +	case PLANE_CTL_FORMAT_Y410:
> +		return DRM_FORMAT_Y410;
> +	case PLANE_CTL_FORMAT_Y412:
> +		return DRM_FORMAT_Y412;
> +	case PLANE_CTL_FORMAT_Y416:
> +		return DRM_FORMAT_Y416;
>   	default:
>   	case PLANE_CTL_FORMAT_XRGB_8888:
>   		if (rgb_order) {
> @@ -3529,6 +3541,18 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>   		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>   	case DRM_FORMAT_NV12:
>   		return PLANE_CTL_FORMAT_NV12;
> +	case DRM_FORMAT_Y210:
> +		return PLANE_CTL_FORMAT_Y210;
> +	case DRM_FORMAT_Y212:
> +		return PLANE_CTL_FORMAT_Y212;
> +	case DRM_FORMAT_Y216:
> +		return PLANE_CTL_FORMAT_Y216;
> +	case DRM_FORMAT_Y410:
> +		return PLANE_CTL_FORMAT_Y410;
> +	case DRM_FORMAT_Y412:
> +		return PLANE_CTL_FORMAT_Y412;
> +	case DRM_FORMAT_Y416:
> +		return PLANE_CTL_FORMAT_Y416;
>   	default:
>   		MISSING_CASE(pixel_format);
>   	}
> @@ -5022,6 +5046,12 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>   	case DRM_FORMAT_UYVY:
>   	case DRM_FORMAT_VYUY:
>   	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_Y210:
> +	case DRM_FORMAT_Y212:
> +	case DRM_FORMAT_Y216:
> +	case DRM_FORMAT_Y410:
> +	case DRM_FORMAT_Y412:
> +	case DRM_FORMAT_Y416:
>   		break;
>   	default:
>   		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8f3982c..f1bc46d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1750,6 +1750,27 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
>   	DRM_FORMAT_VYUY,
>   };
>   
> +static const uint32_t icl_plane_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +	DRM_FORMAT_Y410,
> +	DRM_FORMAT_Y412,
> +	DRM_FORMAT_Y416,
> +};
> +
>   static const uint32_t skl_planar_formats[] = {
>   	DRM_FORMAT_C8,
>   	DRM_FORMAT_RGB565,
> @@ -1766,6 +1787,28 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
>   	DRM_FORMAT_NV12,
>   };
>   
> +static const uint32_t icl_planar_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_NV12,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +	DRM_FORMAT_Y410,
> +	DRM_FORMAT_Y412,
> +	DRM_FORMAT_Y416,
> +};
> +
>   static const uint64_t skl_plane_format_modifiers_noccs[] = {
>   	I915_FORMAT_MOD_Yf_TILED,
>   	I915_FORMAT_MOD_Y_TILED,
> @@ -1904,6 +1947,12 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>   	case DRM_FORMAT_YVYU:
>   	case DRM_FORMAT_UYVY:
>   	case DRM_FORMAT_VYUY:
> +	case DRM_FORMAT_Y210:
> +	case DRM_FORMAT_Y212:
> +	case DRM_FORMAT_Y216:
> +	case DRM_FORMAT_Y410:
> +	case DRM_FORMAT_Y412:
> +	case DRM_FORMAT_Y416:
>   	case DRM_FORMAT_NV12:
>   		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>   			return true;
> @@ -2045,8 +2094,16 @@ struct intel_plane *
>   		plane->update_slave = icl_update_slave;
>   
>   	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> -		formats = skl_planar_formats;
> -		num_formats = ARRAY_SIZE(skl_planar_formats);
> +		if (INTEL_GEN(dev_priv) >= 11) {
> +			formats = icl_planar_formats;
> +			num_formats = ARRAY_SIZE(icl_planar_formats);
> +		} else {
> +			formats = skl_planar_formats;
> +			num_formats = ARRAY_SIZE(skl_planar_formats);
> +		}
> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		formats = icl_plane_formats;
> +		num_formats = ARRAY_SIZE(icl_plane_formats);
>   	} else {
>   		formats = skl_plane_formats;
>   		num_formats = ARRAY_SIZE(skl_plane_formats);
> 

Look good to me. There will be collision with my Pxxx patches if those 
ever go upstream but it is issue of that time. I guess these patches 
will also wait for IGT support?

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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