[PATCH 1/2] drm/dp: Add defines for latency in sink

[PATCH 1/2] drm/dp: Add defines for latency in sink

[vathsala nagaraju]

Add defines for dpcd register 2009 (synchronization latency
in sink).

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 include/drm/drm_dp_helper.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11c39f1..846004e6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -735,6 +735,9 @@
 # define DP_PSR_SINK_INTERNAL_ERROR         7
 # define DP_PSR_SINK_STATE_MASK             0x07
 
+#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
+# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
+
 #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
 # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
 
-- 
1.9.1

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[PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[vathsala nagaraju]

Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.

v2 :
 - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
 - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
 - add check ==1 for dpcd_read call (ville)

v3 : (Rodrigo)
 - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
 - replace with &=

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 +-
 drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..b880c84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4047,7 +4047,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
-#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..adf7abc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 */
 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 	uint32_t val;
+	uint8_t sink_latency;
 
 	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
 	val |= EDP_PSR2_ENABLE |
-		EDP_SU_TRACK_ENABLE |
-		EDP_FRAMES_BEFORE_SU_ENTRY;
+		EDP_SU_TRACK_ENABLE;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+				&sink_latency) == 1) {
+		sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
+	} else {
+		sink_latency = 0;
+	}
+	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Jani Nikula]

On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
>  - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
>  - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
>  - add check ==1 for dpcd_read call (ville)
>
> v3 : (Rodrigo)
>  - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
>  - replace with &=
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>  2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..b880c84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4047,7 +4047,7 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK		0xf
> -#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)

In the register definitions we use the shift values directly, not the
macro. That's the style we've adopted. Please stick to it.

Ditto for the indent, why do you remove it?


BR,
Jani.

>  
>  #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..adf7abc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	uint32_t val;
> +	uint8_t sink_latency;
>  
>  	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
>  	val |= EDP_PSR2_ENABLE |
> -		EDP_SU_TRACK_ENABLE |
> -		EDP_FRAMES_BEFORE_SU_ENTRY;
> +		EDP_SU_TRACK_ENABLE;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> +				&sink_latency) == 1) {
> +		sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
> +	} else {
> +		sink_latency = 0;
> +	}
> +	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[vathsala nagaraju]

[-- Attachment #1.1: Type: text/plain, Size: 2884 bytes --]

On Monday 25 September 2017 02:00 PM, Jani Nikula wrote:
> On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> Set frames before SU entry value for max resync frame count of
>> dpcd register 2009, bit field 0:3.
>>
>> v2 :
>>   - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
>>   - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
>>   - add check ==1 for dpcd_read call (ville)
>>
>> v3 : (Rodrigo)
>>   - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
>>   - replace with &=
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h  |  2 +-
>>   drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>>   2 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 82f36dd..b880c84 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4047,7 +4047,7 @@ enum {
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>   #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>>   #define   EDP_PSR2_IDLE_MASK		0xf
>> -#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
>> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
> In the register definitions we use the shift values directly, not the
> macro. That's the style we've adopted. Please stick to it.
Macro was suggested by Rodrigo.
>
> Ditto for the indent, why do you remove it?
BR, Jani.
>>   
>>   #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>>   #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 0a17d1f..adf7abc 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>   	 */
>>   	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>>   	uint32_t val;
>> +	uint8_t sink_latency;
>>   
>>   	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>>   
>> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>   	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>>   	 * good enough. */
>>   	val |= EDP_PSR2_ENABLE |
>> -		EDP_SU_TRACK_ENABLE |
>> -		EDP_FRAMES_BEFORE_SU_ENTRY;
>> +		EDP_SU_TRACK_ENABLE;
>> +
>> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
>> +				&sink_latency) == 1) {
>> +		sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
>> +	} else {
>> +		sink_latency = 0;
>> +	}
>> +	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>>   
>>   	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>>   		val |= EDP_PSR2_TP2_TIME_2500;


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Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Rodrigo Vivi]

On Mon, Sep 25, 2017 at 09:10:28AM +0000, vathsala nagaraju wrote:
> On Monday 25 September 2017 02:00 PM, Jani Nikula wrote:
> 
>     On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> 
>         Set frames before SU entry value for max resync frame count of
>         dpcd register 2009, bit field 0:3.
> 
>         v2 :
>          - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
>          - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
>          - add check ==1 for dpcd_read call (ville)
> 
>         v3 : (Rodrigo)
>          - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
>          - replace with &=
> 
>         Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>         CC: Puthikorn Voravootivat <puthik@chromium.org>
>         Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>         Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>         ---
>          drivers/gpu/drm/i915/i915_reg.h  |  2 +-
>          drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>          2 files changed, 11 insertions(+), 3 deletions(-)
> 
>         diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>         index 82f36dd..b880c84 100644
>         --- a/drivers/gpu/drm/i915/i915_reg.h
>         +++ b/drivers/gpu/drm/i915/i915_reg.h
>         @@ -4047,7 +4047,7 @@ enum {
>          #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>          #define   EDP_PSR2_FRAME_BEFORE_SU_MASK        (0xf<<4)
>          #define   EDP_PSR2_IDLE_MASK           0xf
>         -#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
>         +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
> 
>     In the register definitions we use the shift values directly, not the
>     macro. That's the style we've adopted. Please stick to it.
> 
> Macro was suggested by Rodrigo.

Well, one bad review is not an excuse to ignore a good review ;)

But what Jani mentioned and he is absolutelly right is to use the shift value
directly instead the SHIFT macro, not to avoid the function-like macro that I
suggested.

In other words:

#define   EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)

Please also note his request on the spaces required for proper identation.

And also please address his comments on the first patch to make the defines
in total sync with DP Spec.

Thanks,
Rodrigo.

> 
> 
>     Ditto for the indent, why do you remove it?
> 
> BR, Jani.
> 
> 
>          #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>          #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
>         diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>         index 0a17d1f..adf7abc 100644
>         --- a/drivers/gpu/drm/i915/intel_psr.c
>         +++ b/drivers/gpu/drm/i915/intel_psr.c
>         @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>                  */
>                 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>                 uint32_t val;
>         +       uint8_t sink_latency;
> 
>                 val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> 
>         @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>                  * mesh at all with our frontbuffer tracking. And the hw alone isn't
>                  * good enough. */
>                 val |= EDP_PSR2_ENABLE |
>         -               EDP_SU_TRACK_ENABLE |
>         -               EDP_FRAMES_BEFORE_SU_ENTRY;
>         +               EDP_SU_TRACK_ENABLE;
>         +
>         +       if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
>         +                               &sink_latency) == 1) {
>         +               sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
>         +       } else {
>         +               sink_latency = 0;
>         +       }
>         +       val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
> 
>                 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>                         val |= EDP_PSR2_TP2_TIME_2500;
> 
> 
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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Jani Nikula]

On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 11c39f1..846004e6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -735,6 +735,9 @@
>  # define DP_PSR_SINK_INTERNAL_ERROR         7
>  # define DP_PSR_SINK_STATE_MASK             0x07
>  
> +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
> +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf

For the DP spec, please don't invent the names, use the ones from the
spec. At most drop excess stuff from the end.

#define DP_SYNCHRONIZATION_LATENCY_IN_SINK
# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
# define DP_MAX_RESYNC_FRAME_COUNT_MASK

And while at it, please add the full register contents.

BR,
Jani.

> +
>  #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
>  # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)

-- 
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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[vathsala nagaraju]

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On Monday 25 September 2017 01:53 PM, Jani Nikula wrote:
> On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> Add defines for dpcd register 2009 (synchronization latency
>> in sink).
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   include/drm/drm_dp_helper.h | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index 11c39f1..846004e6 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -735,6 +735,9 @@
>>   # define DP_PSR_SINK_INTERNAL_ERROR         7
>>   # define DP_PSR_SINK_STATE_MASK             0x07
>>   
>> +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
>> +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
> For the DP spec, please don't invent the names, use the ones from the
> spec. At most drop excess stuff from the end.
In edp 1.4b spec , the register name 2009 is "DEBUG 0 SYNCHRONIZATION 
LATENCY SINK "  and bit 0:3 "MAX RE-SYNC FRAME COUNT"
>
> #define DP_SYNCHRONIZATION_LATENCY_IN_SINK
> # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
> # define DP_MAX_RESYNC_FRAME_COUNT_MASK
>
> And while at it, please add the full register contents.
>
> BR,
> Jani.
>
>> +
>>   #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
>>   # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)


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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Rodrigo Vivi]

On Mon, Sep 25, 2017 at 09:01:38AM +0000, vathsala nagaraju wrote:
> On Monday 25 September 2017 01:53 PM, Jani Nikula wrote:
> 
>     On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> 
>         Add defines for dpcd register 2009 (synchronization latency
>         in sink).
> 
>         Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>         CC: Puthikorn Voravootivat <puthik@chromium.org>
>         Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>         Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>         ---
>          include/drm/drm_dp_helper.h | 3 +++
>          1 file changed, 3 insertions(+)
> 
>         diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>         index 11c39f1..846004e6 100644
>         --- a/include/drm/drm_dp_helper.h
>         +++ b/include/drm/drm_dp_helper.h
>         @@ -735,6 +735,9 @@
>          # define DP_PSR_SINK_INTERNAL_ERROR         7
>          # define DP_PSR_SINK_STATE_MASK             0x07
> 
>         +#define DP_SINK_SYNCHRONIZATION_LATENCY            0x2009
>         +# define DP_MAX_RESYNC_FRAME_CNT_MASK      0xf
> 
>     For the DP spec, please don't invent the names, use the ones from the
>     spec. At most drop excess stuff from the end.
> 
> In edp 1.4b spec , the register name 2009 is "DEBUG 0 SYNCHRONIZATION LATENCY SINK "  and
> bit 0:3 "MAX RE-SYNC FRAME COUNT"

probably he meant something like:

# define DP_SYNCHRONIZATION_LATENCY_IN_SINK            0x2009
# define DP_MAX_RESYNC_FRAME_COUNT_MASK      0xf

but he is the best one to confirm that...

> 
> 
>     #define DP_SYNCHRONIZATION_LATENCY_IN_SINK
>     # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
>     # define DP_MAX_RESYNC_FRAME_COUNT_MASK
> 
>     And while at it, please add the full register contents.
> 
>     BR,
>     Jani.
> 
> 
>         +
>          #define DP_RECEIVER_ALPM_STATUS                    0x200b  /* eDP 1.4 */
>          # define DP_ALPM_LOCK_TIMEOUT_ERROR        (1 << 0)
> 
> 
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Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

[Jani Nikula]

On Mon, 25 Sep 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Mon, Sep 25, 2017 at 09:01:38AM +0000, vathsala nagaraju wrote:
>> On Monday 25 September 2017 01:53 PM, Jani Nikula wrote:
>> 
>>     On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> 
>>         Add defines for dpcd register 2009 (synchronization latency
>>         in sink).
>> 
>>         Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>         CC: Puthikorn Voravootivat <puthik@chromium.org>
>>         Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>         Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>         ---
>>          include/drm/drm_dp_helper.h | 3 +++
>>          1 file changed, 3 insertions(+)
>> 
>>         diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>>         index 11c39f1..846004e6 100644
>>         --- a/include/drm/drm_dp_helper.h
>>         +++ b/include/drm/drm_dp_helper.h
>>         @@ -735,6 +735,9 @@
>>          # define DP_PSR_SINK_INTERNAL_ERROR         7
>>          # define DP_PSR_SINK_STATE_MASK             0x07
>> 
>>         +#define DP_SINK_SYNCHRONIZATION_LATENCY            0x2009
>>         +# define DP_MAX_RESYNC_FRAME_CNT_MASK      0xf
>> 
>>     For the DP spec, please don't invent the names, use the ones from the
>>     spec. At most drop excess stuff from the end.
>> 
>> In edp 1.4b spec , the register name 2009 is "DEBUG 0 SYNCHRONIZATION LATENCY SINK "  and
>> bit 0:3 "MAX RE-SYNC FRAME COUNT"
>
> probably he meant something like:
>
> # define DP_SYNCHRONIZATION_LATENCY_IN_SINK            0x2009
> # define DP_MAX_RESYNC_FRAME_COUNT_MASK      0xf
>
> but he is the best one to confirm that...

I wrote exactly that in my review, see below.

BR,
Jani.

>
>> 
>> 
>>     #define DP_SYNCHRONIZATION_LATENCY_IN_SINK
>>     # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
>>     # define DP_MAX_RESYNC_FRAME_COUNT_MASK
>> 
>>     And while at it, please add the full register contents.
>> 
>>     BR,
>>     Jani.
>> 
>> 
>>         +
>>          #define DP_RECEIVER_ALPM_STATUS                    0x200b  /* eDP 1.4 */
>>          # define DP_ALPM_LOCK_TIMEOUT_ERROR        (1 << 0)
>> 
>> 

-- 
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Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

[Daniel Vetter]

On Mon, Sep 25, 2017 at 11:23:26AM +0300, Jani Nikula wrote:
> On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> > Add defines for dpcd register 2009 (synchronization latency
> > in sink).
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Puthikorn Voravootivat <puthik@chromium.org>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 11c39f1..846004e6 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -735,6 +735,9 @@
> >  # define DP_PSR_SINK_INTERNAL_ERROR         7
> >  # define DP_PSR_SINK_STATE_MASK             0x07
> >  
> > +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
> > +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
> 
> For the DP spec, please don't invent the names, use the ones from the
> spec. At most drop excess stuff from the end.
> 
> #define DP_SYNCHRONIZATION_LATENCY_IN_SINK
> # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
> # define DP_MAX_RESYNC_FRAME_COUNT_MASK
> 
> And while at it, please add the full register contents.

Please also annotate in which version of the spec we can find this, e.g.

#define DP_SYNCHRONIZATION_LATENCY_IN_SINK	/* eDP 1.4b */
# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
# define DP_MAX_RESYNC_FRAME_COUNT_MASK

Bringing this up since previous versions of this confused Rodrigo
-Daniel

> 
> BR,
> Jani.
> 
> > +
> >  #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
> >  # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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