[PATCH 06/64] drm: Restore double clflush on the last partial cacheline

[PATCH 06/64] drm: Restore double clflush on the last partial cacheline

[Chris Wilson]

This effectively reverts

commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Jun 10 15:58:01 2015 +0100

    drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()

as we have observed issues with serialisation of the clflush operations
on Baytrail+ Atoms with partial updates. Applying the double flush on the
last cacheline forces that clflush to be ordered with respect to the
previous clflush, and the mfence then protects against prefetches crossing
the clflush boundary.

The same issue can be demonstrated in userspace with igt/gem_exec_flush.

Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...)
Testcase: igt/gem_concurrent_blit
Testcase: igt/gem_partial_pread_pwrite
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: dri-devel@lists.freedesktop.org
Cc: Akash Goel <akash.goel@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/drm_cache.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 059f7c39c582..a7916e5f8864 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length)
 		mb();
 		for (; addr < end; addr += size)
 			clflushopt(addr);
+		clflushopt(end - 1); /* force serialisation */
 		mb();
 		return;
 	}
-- 
2.8.1

Re: [PATCH 06/64] drm: Restore double clflush on the last partial cacheline

[Daniel Vetter]

On Thu, Jul 07, 2016 at 09:41:12AM +0100, Chris Wilson wrote:
> This effectively reverts
> 
> commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Wed Jun 10 15:58:01 2015 +0100
> 
>     drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
> 
> as we have observed issues with serialisation of the clflush operations
> on Baytrail+ Atoms with partial updates. Applying the double flush on the
> last cacheline forces that clflush to be ordered with respect to the
> previous clflush, and the mfence then protects against prefetches crossing
> the clflush boundary.
> 
> The same issue can be demonstrated in userspace with igt/gem_exec_flush.
> 
> Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...)
> Testcase: igt/gem_concurrent_blit
> Testcase: igt/gem_partial_pread_pwrite
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Akash Goel <akash.goel@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Jason Ekstrand <jason.ekstrand@intel.com>
> Cc: stable@vger.kernel.org
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

It's duct-tape, but oh well. Applied to drm-misc.
-Daniel

> ---
>  drivers/gpu/drm/drm_cache.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 059f7c39c582..a7916e5f8864 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>  		mb();
>  		for (; addr < end; addr += size)
>  			clflushopt(addr);
> +		clflushopt(end - 1); /* force serialisation */
>  		mb();
>  		return;
>  	}
> -- 
> 2.8.1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 06/64] drm: Restore double clflush on the last partial cacheline

[Mika Kuoppala]

Daniel Vetter <daniel@ffwll.ch> writes:

> On Thu, Jul 07, 2016 at 09:41:12AM +0100, Chris Wilson wrote:
>> This effectively reverts
>> 
>> commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
>> Author: Chris Wilson <chris@chris-wilson.co.uk>
>> Date:   Wed Jun 10 15:58:01 2015 +0100
>> 
>>     drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
>> 
>> as we have observed issues with serialisation of the clflush operations
>> on Baytrail+ Atoms with partial updates. Applying the double flush on the
>> last cacheline forces that clflush to be ordered with respect to the
>> previous clflush, and the mfence then protects against prefetches crossing
>> the clflush boundary.
>> 
>> The same issue can be demonstrated in userspace with igt/gem_exec_flush.
>> 
>> Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...)
>> Testcase: igt/gem_concurrent_blit
>> Testcase: igt/gem_partial_pread_pwrite
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: dri-devel@lists.freedesktop.org
>> Cc: Akash Goel <akash.goel@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Cc: Jason Ekstrand <jason.ekstrand@intel.com>
>> Cc: stable@vger.kernel.org
>> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
>
> It's duct-tape, but oh well. Applied to drm-misc.

We were confused how many layers we need.

-Mika

> -Daniel
>
>> ---
>>  drivers/gpu/drm/drm_cache.c | 1 +
>>  1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
>> index 059f7c39c582..a7916e5f8864 100644
>> --- a/drivers/gpu/drm/drm_cache.c
>> +++ b/drivers/gpu/drm/drm_cache.c
>> @@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>>  		mb();
>>  		for (; addr < end; addr += size)
>>  			clflushopt(addr);
>> +		clflushopt(end - 1); /* force serialisation */
>>  		mb();
>>  		return;
>>  	}
>> -- 
>> 2.8.1
>> 
>
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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