* [PATCH 06/64] drm: Restore double clflush on the last partial cacheline [not found] <1467880930-23082-1-git-send-email-chris@chris-wilson.co.uk> @ 2016-07-07 8:41 ` Chris Wilson 2016-07-12 13:57 ` Daniel Vetter 0 siblings, 1 reply; 3+ messages in thread From: Chris Wilson @ 2016-07-07 8:41 UTC (permalink / raw) To: intel-gfx Cc: Chris Wilson, dri-devel, Akash Goel, Imre Deak, Daniel Vetter, Jason Ekstrand, stable This effectively reverts commit afcd950cafea6e27b739fe7772cbbeed37d05b8b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Wed Jun 10 15:58:01 2015 +0100 drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range() as we have observed issues with serialisation of the clflush operations on Baytrail+ Atoms with partial updates. Applying the double flush on the last cacheline forces that clflush to be ordered with respect to the previous clflush, and the mfence then protects against prefetches crossing the clflush boundary. The same issue can be demonstrated in userspace with igt/gem_exec_flush. Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...) Testcase: igt/gem_concurrent_blit Testcase: igt/gem_partial_pread_pwrite Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: dri-devel@lists.freedesktop.org Cc: Akash Goel <akash.goel@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jason Ekstrand <jason.ekstrand@intel.com> Cc: stable@vger.kernel.org Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/drm_cache.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 059f7c39c582..a7916e5f8864 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length) mb(); for (; addr < end; addr += size) clflushopt(addr); + clflushopt(end - 1); /* force serialisation */ mb(); return; } -- 2.8.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 06/64] drm: Restore double clflush on the last partial cacheline 2016-07-07 8:41 ` [PATCH 06/64] drm: Restore double clflush on the last partial cacheline Chris Wilson @ 2016-07-12 13:57 ` Daniel Vetter 2016-07-13 8:07 ` Mika Kuoppala 0 siblings, 1 reply; 3+ messages in thread From: Daniel Vetter @ 2016-07-12 13:57 UTC (permalink / raw) To: Chris Wilson Cc: Daniel Vetter, dri-devel, Jason Ekstrand, Akash Goel, stable, intel-gfx On Thu, Jul 07, 2016 at 09:41:12AM +0100, Chris Wilson wrote: > This effectively reverts > > commit afcd950cafea6e27b739fe7772cbbeed37d05b8b > Author: Chris Wilson <chris@chris-wilson.co.uk> > Date: Wed Jun 10 15:58:01 2015 +0100 > > drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range() > > as we have observed issues with serialisation of the clflush operations > on Baytrail+ Atoms with partial updates. Applying the double flush on the > last cacheline forces that clflush to be ordered with respect to the > previous clflush, and the mfence then protects against prefetches crossing > the clflush boundary. > > The same issue can be demonstrated in userspace with igt/gem_exec_flush. > > Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...) > Testcase: igt/gem_concurrent_blit > Testcase: igt/gem_partial_pread_pwrite > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: dri-devel@lists.freedesktop.org > Cc: Akash Goel <akash.goel@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Cc: Jason Ekstrand <jason.ekstrand@intel.com> > Cc: stable@vger.kernel.org > Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> It's duct-tape, but oh well. Applied to drm-misc. -Daniel > --- > drivers/gpu/drm/drm_cache.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c > index 059f7c39c582..a7916e5f8864 100644 > --- a/drivers/gpu/drm/drm_cache.c > +++ b/drivers/gpu/drm/drm_cache.c > @@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length) > mb(); > for (; addr < end; addr += size) > clflushopt(addr); > + clflushopt(end - 1); /* force serialisation */ > mb(); > return; > } > -- > 2.8.1 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 06/64] drm: Restore double clflush on the last partial cacheline 2016-07-12 13:57 ` Daniel Vetter @ 2016-07-13 8:07 ` Mika Kuoppala 0 siblings, 0 replies; 3+ messages in thread From: Mika Kuoppala @ 2016-07-13 8:07 UTC (permalink / raw) To: Daniel Vetter, Chris Wilson Cc: Daniel Vetter, intel-gfx, stable, Jason Ekstrand, Akash Goel, dri-devel Daniel Vetter <daniel@ffwll.ch> writes: > On Thu, Jul 07, 2016 at 09:41:12AM +0100, Chris Wilson wrote: >> This effectively reverts >> >> commit afcd950cafea6e27b739fe7772cbbeed37d05b8b >> Author: Chris Wilson <chris@chris-wilson.co.uk> >> Date: Wed Jun 10 15:58:01 2015 +0100 >> >> drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range() >> >> as we have observed issues with serialisation of the clflush operations >> on Baytrail+ Atoms with partial updates. Applying the double flush on the >> last cacheline forces that clflush to be ordered with respect to the >> previous clflush, and the mfence then protects against prefetches crossing >> the clflush boundary. >> >> The same issue can be demonstrated in userspace with igt/gem_exec_flush. >> >> Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...) >> Testcase: igt/gem_concurrent_blit >> Testcase: igt/gem_partial_pread_pwrite >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845 >> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: dri-devel@lists.freedesktop.org >> Cc: Akash Goel <akash.goel@intel.com> >> Cc: Imre Deak <imre.deak@intel.com> >> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> >> Cc: Jason Ekstrand <jason.ekstrand@intel.com> >> Cc: stable@vger.kernel.org >> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > > It's duct-tape, but oh well. Applied to drm-misc. We were confused how many layers we need. -Mika > -Daniel > >> --- >> drivers/gpu/drm/drm_cache.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c >> index 059f7c39c582..a7916e5f8864 100644 >> --- a/drivers/gpu/drm/drm_cache.c >> +++ b/drivers/gpu/drm/drm_cache.c >> @@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length) >> mb(); >> for (; addr < end; addr += size) >> clflushopt(addr); >> + clflushopt(end - 1); /* force serialisation */ >> mb(); >> return; >> } >> -- >> 2.8.1 >> > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-07-07 8:41 ` [PATCH 06/64] drm: Restore double clflush on the last partial cacheline Chris Wilson
2016-07-12 13:57 ` Daniel Vetter
2016-07-13 8:07 ` Mika Kuoppala
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