[MODERATED] [PATCH v4 7/8] [PATCH v4 7/8] Linux Patch #7

[MODERATED] [PATCH v4 7/8] [PATCH v4 7/8] Linux Patch #7

[konrad.wilk]

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
 arch/x86/kvm/vmx.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index e7c69ef5b918..9b18848ccaba 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2439,9 +2439,9 @@ static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 }
 
 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
-				  u64 guest_val, u64 host_val)
+				  u64 guest_val, u64 host_val, bool entry_only)
 {
-	int i, j;
+	int i, j = 0;
 	struct msr_autoload *m = &vmx->msr_autoload;
 
 	switch (msr) {
@@ -2477,7 +2477,9 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 	}
 
 	i = find_msr(&m->guest, msr);
-	j = find_msr(&m->host, msr);
+	if (!entry_only)
+		j = find_msr(&m->host, msr);
+
 	if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
 		printk_once(KERN_WARNING "Not enough msr switch entries. "
 				"Can't add msr %x\n", msr);
@@ -2487,12 +2489,16 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 		i = m->guest.nr++;
 		vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 	}
+	m->guest.val[i].index = msr;
+	m->guest.val[i].value = guest_val;
+
+	if (entry_only)
+		return;
+
 	if (j < 0) {
 		j = m->host.nr++;
 		vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 	}
-	m->guest.val[i].index = msr;
-	m->guest.val[i].value = guest_val;
 	m->host.val[j].index = msr;
 	m->host.val[j].value = host_val;
 }
@@ -2538,7 +2544,7 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 			guest_efer &= ~EFER_LME;
 		if (guest_efer != host_efer)
 			add_atomic_switch_msr(vmx, MSR_EFER,
-					      guest_efer, host_efer);
+					      guest_efer, host_efer, false);
 		return false;
 	} else {
 		guest_efer &= ~ignore_bits;
@@ -4031,7 +4037,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		vcpu->arch.ia32_xss = data;
 		if (vcpu->arch.ia32_xss != host_xss)
 			add_atomic_switch_msr(vmx, MSR_IA32_XSS,
-				vcpu->arch.ia32_xss, host_xss);
+				vcpu->arch.ia32_xss, host_xss, false);
 		else
 			clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
 		break;
@@ -9978,7 +9984,7 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
 			clear_atomic_switch_msr(vmx, msrs[i].msr);
 		else
 			add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
-					msrs[i].host);
+					msrs[i].host, false);
 }
 
 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
-- 
2.14.3

Re: [PATCH v4 7/8] [PATCH v4 7/8] Linux Patch #7

[Thomas Gleixner]

On Sat, 23 Jun 2018, speck for konrad.wilk_at_oracle.com wrote:

> x86/KVM/VMX: Add framework for having disjoint amount of MSRs to save/restore

I have a hard time to find the framework ...

Changed that to:

x86/KVM/VMX: Extend add_atomic_switch_msr() to allow VMENTER only MSRs

The IA32_FLUSH_CMD MSR needs only to be written on VMENTER. Extend
add_atomic_switch_msr() with an entry_only parameter to allow storing the
MSR only in the guest (ENTRY) MST array.

Hmm?

Thanks,

	tglx

[MODERATED] Re: [PATCH v4 7/8] [PATCH v4 7/8] Linux Patch #7

[Konrad Rzeszutek Wilk]

On Wed, Jun 27, 2018 at 12:52:57PM +0200, speck for Thomas Gleixner wrote:
> On Sat, 23 Jun 2018, speck for konrad.wilk_at_oracle.com wrote:
> 
> > x86/KVM/VMX: Add framework for having disjoint amount of MSRs to save/restore
> 
> I have a hard time to find the framework ...

I am being optimistic :-)
> 
> Changed that to:
> 
> x86/KVM/VMX: Extend add_atomic_switch_msr() to allow VMENTER only MSRs
> 
> The IA32_FLUSH_CMD MSR needs only to be written on VMENTER. Extend
> add_atomic_switch_msr() with an entry_only parameter to allow storing the
> MSR only in the guest (ENTRY) MST array.
> 
> Hmm?

<nods>

Albeit do you want to wait a bit until I have the performance numbers at
hand on how much this helps vs doing it the old-fashioned way (WRMSRL right
before VMENTER)?


> 
> Thanks,
> 
> 	tglx

[MODERATED] Re: [PATCH v4 7/8] [PATCH v4 7/8] Linux Patch #7

[Andrew Cooper]

On 27/06/18 15:32, speck for Konrad Rzeszutek Wilk wrote:
>
>> Changed that to:
>>
>> x86/KVM/VMX: Extend add_atomic_switch_msr() to allow VMENTER only MSRs
>>
>> The IA32_FLUSH_CMD MSR needs only to be written on VMENTER. Extend
>> add_atomic_switch_msr() with an entry_only parameter to allow storing the
>> MSR only in the guest (ENTRY) MST array.
>>
>> Hmm?
> <nods>
>
> Albeit do you want to wait a bit until I have the performance numbers at
> hand on how much this helps vs doing it the old-fashioned way (WRMSRL right
> before VMENTER)?

I've been told multiple times that MSR load/save lists are more than
twice as slow as the equivalent rdmsr/wrmsr's in real code.

However in this case, you've got a meaningful difference in which data
is flushed from the L1D cache depending on the positioning.  Using the
MSR load/save list is the only way to the GPRs flushed.

~Andrew