* [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-07 14:33 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
@ 2024-11-07 14:33 ` Pravalika Gurram
2024-11-07 17:08 ` Zbigniew Kempczyński
0 siblings, 1 reply; 18+ messages in thread
From: Pravalika Gurram @ 2024-11-07 14:33 UTC (permalink / raw)
To: igt-dev; +Cc: Pravalika Gurram
move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
to xe spin lib to avoid code redundancy.
Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
---
lib/xe/xe_spin.c | 118 +++++++++++++++++++++++
lib/xe/xe_spin.h | 23 +++++
tests/intel/xe_drm_fdinfo.c | 185 ++++++------------------------------
3 files changed, 170 insertions(+), 156 deletions(-)
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 3adacc3a8..8ba7b8875 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -292,6 +292,124 @@ void xe_spin_free(int fd, struct igt_spin *spin)
free(spin);
}
+struct spin_ctx *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
+ uint16_t width, uint16_t num_placements)
+{
+ struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
+
+ igt_assert(width && num_placements &&
+ (width == 1 || num_placements == 1));
+ igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
+
+ ctx->class = hwe->engine_class;
+ ctx->width = width;
+ ctx->num_placements = num_placements;
+ ctx->vm = vm;
+
+ ctx->ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ ctx->exec.num_batch_buffer = width;
+ ctx->exec.num_syncs = 2;
+ ctx->exec.syncs = to_user_pointer(ctx->sync);
+
+ ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+ ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+ ctx->sync[0].handle = syncobj_create(fd, 0);
+
+ ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+ ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+ ctx->sync[1].handle = syncobj_create(fd, 0);
+
+ ctx->bo_size = sizeof(struct xe_spin);
+ ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
+ ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
+ vram_if_possible(fd, hwe->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ if (ctx->ahnd > 0) {
+ for (unsigned int i = 0; i < width; i++)
+ ctx->addr[i] = intel_allocator_alloc_with_strategy(ctx->ahnd,
+ ctx->bo, ctx->bo_size, 0,
+ ALLOC_STRATEGY_LOW_TO_HIGH);
+ } else {
+ for (unsigned int i = 0; i < width; i++)
+ ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
+ }
+
+ ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
+
+ igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
+ hwe, 0, &ctx->exec_queue), 0);
+
+ xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
+ ctx->sync, 1);
+
+ return ctx;
+}
+
+void xe_spin_sync_start(int fd, struct spin_ctx *ctx)
+{
+ if (!ctx)
+ return;
+
+ ctx->spin_opts.addr = ctx->addr[0];
+ ctx->spin_opts.write_timestamp = true;
+ ctx->spin_opts.preempt = true;
+ xe_spin_init(ctx->spin, &ctx->spin_opts);
+
+ /* re-use sync[0] for exec */
+ ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+
+ ctx->exec.exec_queue_id = ctx->exec_queue;
+
+ if (ctx->width > 1)
+ ctx->exec.address = to_user_pointer(ctx->addr);
+ else
+ ctx->exec.address = ctx->addr[0];
+
+ xe_exec(fd, &ctx->exec);
+
+ xe_spin_wait_started(ctx->spin);
+ igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
+
+ igt_debug("%d: spinner started\n", ctx->class);
+}
+
+void xe_spin_sync_end(int fd, struct spin_ctx *ctx)
+{
+ if (!ctx || ctx->ended)
+ return;
+
+ xe_spin_end(ctx->spin);
+
+ igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
+ igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
+ igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ ctx->ended = true;
+ igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
+ ctx->spin->timestamp);
+}
+
+void xe_spin_ctx_destroy(int fd, struct spin_ctx *ctx)
+{
+ if (!ctx)
+ return;
+
+ syncobj_destroy(fd, ctx->sync[0].handle);
+ syncobj_destroy(fd, ctx->sync[1].handle);
+ xe_exec_queue_destroy(fd, ctx->exec_queue);
+
+ munmap(ctx->spin, ctx->bo_size);
+ gem_close(fd, ctx->bo);
+ put_ahnd(ctx->ahnd);
+
+ free(ctx);
+}
+
void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
struct xe_cork *cork)
{
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index d65adb05c..a35b06109 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -43,9 +43,30 @@ struct xe_spin {
uint32_t timestamp;
};
+struct spin_ctx {
+ uint32_t vm;
+ uint64_t addr[XE_MAX_ENGINE_INSTANCE];
+ struct drm_xe_sync sync[2];
+ struct drm_xe_exec exec;
+ uint32_t exec_queue;
+ size_t bo_size;
+ uint32_t bo;
+ struct xe_spin *spin;
+ struct xe_spin_opts spin_opts;
+ bool ended;
+ uint16_t class;
+ uint16_t width;
+ uint16_t num_placements;
+ uint64_t ahnd;
+};
+
igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
+struct spin_ctx *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
+ uint16_t width, uint16_t num_placements);
+void xe_spin_ctx_destroy(int fd, struct spin_ctx *ctx);
#define xe_spin_init_opts(fd, ...) \
xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
@@ -55,6 +76,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
void xe_spin_wait_started(struct xe_spin *spin);
void xe_spin_end(struct xe_spin *spin);
void xe_spin_free(int fd, struct igt_spin *spin);
+void xe_spin_sync_start(int fd, struct spin_ctx *ctx);
+void xe_spin_sync_end(int fd, struct spin_ctx *ctx);
struct xe_cork {
struct xe_spin *spin;
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 5fd7c0416..4a6dfa73c 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
igt_require(info.num_engines);
}
-struct spin_ctx {
- uint32_t vm;
- uint64_t addr[XE_MAX_ENGINE_INSTANCE];
- struct drm_xe_sync sync[2];
- struct drm_xe_exec exec;
- uint32_t exec_queue;
- size_t bo_size;
- uint32_t bo;
- struct xe_spin *spin;
- struct xe_spin_opts spin_opts;
- bool ended;
- uint16_t class;
- uint16_t width;
- uint16_t num_placements;
-};
-
-static struct spin_ctx *
-spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
- uint16_t width, uint16_t num_placements)
-{
- struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
-
- igt_assert(width && num_placements &&
- (width == 1 || num_placements == 1));
- igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
-
- ctx->class = hwe->engine_class;
- ctx->width = width;
- ctx->num_placements = num_placements;
- ctx->vm = vm;
-
- for (unsigned int i = 0; i < width; i++)
- ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
-
- ctx->exec.num_batch_buffer = width;
- ctx->exec.num_syncs = 2;
- ctx->exec.syncs = to_user_pointer(ctx->sync);
-
- ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
- ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
- ctx->sync[0].handle = syncobj_create(fd, 0);
-
- ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
- ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
- ctx->sync[1].handle = syncobj_create(fd, 0);
-
- ctx->bo_size = sizeof(struct xe_spin);
- ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
- ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
- vram_if_possible(fd, hwe->gt_id),
- DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
- ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
-
- igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
- hwe, 0, &ctx->exec_queue), 0);
-
- xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
- ctx->sync, 1);
-
- return ctx;
-}
-
-static void
-spin_sync_start(int fd, struct spin_ctx *ctx)
-{
- if (!ctx)
- return;
-
- ctx->spin_opts.addr = ctx->addr[0];
- ctx->spin_opts.write_timestamp = true;
- ctx->spin_opts.preempt = true;
- xe_spin_init(ctx->spin, &ctx->spin_opts);
-
- /* re-use sync[0] for exec */
- ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
-
- ctx->exec.exec_queue_id = ctx->exec_queue;
-
- if (ctx->width > 1)
- ctx->exec.address = to_user_pointer(ctx->addr);
- else
- ctx->exec.address = ctx->addr[0];
-
- xe_exec(fd, &ctx->exec);
-
- xe_spin_wait_started(ctx->spin);
- igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
-
- igt_debug("%s: spinner started\n", engine_map[ctx->class]);
-}
-
-static void
-spin_sync_end(int fd, struct spin_ctx *ctx)
-{
- if (!ctx || ctx->ended)
- return;
-
- xe_spin_end(ctx->spin);
-
- igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
- igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
- ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
- xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
- igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
- ctx->ended = true;
- igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
- ctx->spin->timestamp);
-}
-
-static void
-spin_ctx_destroy(int fd, struct spin_ctx *ctx)
-{
- if (!ctx)
- return;
-
- syncobj_destroy(fd, ctx->sync[0].handle);
- syncobj_destroy(fd, ctx->sync[1].handle);
- xe_exec_queue_destroy(fd, ctx->exec_queue);
-
- munmap(ctx->spin, ctx->bo_size);
- gem_close(fd, ctx->bo);
-
- free(ctx);
-}
-
static void
check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
int class, int width, enum expected_load expected_load)
@@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
vm = xe_vm_create(fd, 0, 0);
if (flags & TEST_BUSY) {
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
}
read_engine_cycles(fd, pceu1[0]);
@@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
usleep(batch_duration_usec);
if (flags & TEST_TRAILING_IDLE)
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu2[0]);
if (flags & TEST_ISOLATION)
@@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
close(new_fd);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
@@ -588,15 +461,15 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
uint32_t vm;
vm = xe_vm_create(fd, 0, 0);
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
/* destroy queue before sampling again */
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
read_engine_cycles(fd, pceu2);
@@ -616,12 +489,12 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
vm = xe_vm_create(fd, 0, 0);
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
check_results(pceu1, pceu2, class, 1, expected_load);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
@@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
if (_class == hwe->engine_class || ctx[_class])
continue;
- ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
- spin_sync_start(fd, ctx[_class]);
+ ctx[_class] = xe_spin_ctx_init(fd, _hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx[_class]);
}
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
xe_for_each_engine_class(class)
- spin_sync_end(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
continue;
check_results(pceu1, pceu2, class, 1, expected_load);
- spin_sync_end(fd, ctx[class]);
- spin_ctx_destroy(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
+ xe_spin_ctx_destroy(fd, ctx[class]);
}
xe_vm_destroy(fd, vm);
@@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
if (ctx[class])
continue;
- ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx[class]);
+ ctx[class] = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx[class]);
}
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
xe_for_each_engine_class(class)
- spin_sync_end(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
continue;
check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
- spin_sync_end(fd, ctx[class]);
- spin_ctx_destroy(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
+ xe_spin_ctx_destroy(fd, ctx[class]);
}
xe_vm_destroy(fd, vm);
@@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
vm = xe_vm_create(fd, 0, 0);
if (flags & TEST_BUSY) {
- ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, eci, vm, width, num_placements);
+ xe_spin_sync_start(fd, ctx);
}
read_engine_cycles(fd, pceu[0]);
@@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
usleep(batch_duration_usec);
if (flags & TEST_TRAILING_IDLE)
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu[1]);
if (flags & TEST_ISOLATION)
@@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
close(fd_spill);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-07 14:33 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
@ 2024-11-07 17:08 ` Zbigniew Kempczyński
0 siblings, 0 replies; 18+ messages in thread
From: Zbigniew Kempczyński @ 2024-11-07 17:08 UTC (permalink / raw)
To: Pravalika Gurram; +Cc: igt-dev
On Thu, Nov 07, 2024 at 08:03:21PM +0530, Pravalika Gurram wrote:
> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
> to xe spin lib to avoid code redundancy.
>
> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
> ---
> lib/xe/xe_spin.c | 118 +++++++++++++++++++++++
> lib/xe/xe_spin.h | 23 +++++
> tests/intel/xe_drm_fdinfo.c | 185 ++++++------------------------------
> 3 files changed, 170 insertions(+), 156 deletions(-)
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 3adacc3a8..8ba7b8875 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -292,6 +292,124 @@ void xe_spin_free(int fd, struct igt_spin *spin)
> free(spin);
> }
>
> +struct spin_ctx *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> + uint16_t width, uint16_t num_placements)
> +{
> + struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> +
> + igt_assert(width && num_placements &&
> + (width == 1 || num_placements == 1));
> + igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> +
> + ctx->class = hwe->engine_class;
> + ctx->width = width;
> + ctx->num_placements = num_placements;
> + ctx->vm = vm;
> +
> + ctx->ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
Ahnd must come from the caller,
> +
> + ctx->exec.num_batch_buffer = width;
> + ctx->exec.num_syncs = 2;
> + ctx->exec.syncs = to_user_pointer(ctx->sync);
> +
> + ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[0].handle = syncobj_create(fd, 0);
> +
> + ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[1].handle = syncobj_create(fd, 0);
> +
> + ctx->bo_size = sizeof(struct xe_spin);
> + ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> + ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> + vram_if_possible(fd, hwe->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + if (ctx->ahnd > 0) {
otherwise you'll here always. I think depending on developer preference
ahnd which is created in upper scope may be used or
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = intel_allocator_alloc_with_strategy(ctx->ahnd,
> + ctx->bo, ctx->bo_size, 0,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
> + } else {
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
calculated here (caller should pass ahnd == 0 what means no allocator
will be used, but arbitrary offset calculation relative to hwe).
--
Zbigniew
> + }
> +
> + ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> +
> + igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> + hwe, 0, &ctx->exec_queue), 0);
> +
> + xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> + ctx->sync, 1);
> +
> + return ctx;
> +}
> +
> +void xe_spin_sync_start(int fd, struct spin_ctx *ctx)
> +{
> + if (!ctx)
> + return;
> +
> + ctx->spin_opts.addr = ctx->addr[0];
> + ctx->spin_opts.write_timestamp = true;
> + ctx->spin_opts.preempt = true;
> + xe_spin_init(ctx->spin, &ctx->spin_opts);
> +
> + /* re-use sync[0] for exec */
> + ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> +
> + ctx->exec.exec_queue_id = ctx->exec_queue;
> +
> + if (ctx->width > 1)
> + ctx->exec.address = to_user_pointer(ctx->addr);
> + else
> + ctx->exec.address = ctx->addr[0];
> +
> + xe_exec(fd, &ctx->exec);
> +
> + xe_spin_wait_started(ctx->spin);
> + igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> +
> + igt_debug("%d: spinner started\n", ctx->class);
> +}
> +
> +void xe_spin_sync_end(int fd, struct spin_ctx *ctx)
> +{
> + if (!ctx || ctx->ended)
> + return;
> +
> + xe_spin_end(ctx->spin);
> +
> + igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + ctx->ended = true;
> + igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
> + ctx->spin->timestamp);
> +}
> +
> +void xe_spin_ctx_destroy(int fd, struct spin_ctx *ctx)
> +{
> + if (!ctx)
> + return;
> +
> + syncobj_destroy(fd, ctx->sync[0].handle);
> + syncobj_destroy(fd, ctx->sync[1].handle);
> + xe_exec_queue_destroy(fd, ctx->exec_queue);
> +
> + munmap(ctx->spin, ctx->bo_size);
> + gem_close(fd, ctx->bo);
> + put_ahnd(ctx->ahnd);
> +
> + free(ctx);
> +}
> +
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork)
> {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index d65adb05c..a35b06109 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -43,9 +43,30 @@ struct xe_spin {
> uint32_t timestamp;
> };
>
> +struct spin_ctx {
I would rename this to xe_spin_ctx to avoid name clashes.
> + uint32_t vm;
> + uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> + struct drm_xe_sync sync[2];
> + struct drm_xe_exec exec;
> + uint32_t exec_queue;
> + size_t bo_size;
> + uint32_t bo;
> + struct xe_spin *spin;
> + struct xe_spin_opts spin_opts;
> + bool ended;
> + uint16_t class;
> + uint16_t width;
> + uint16_t num_placements;
> + uint64_t ahnd;
> +};
> +
> igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
> void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
> +struct spin_ctx *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> + uint16_t width, uint16_t num_placements);
> +void xe_spin_ctx_destroy(int fd, struct spin_ctx *ctx);
>
> #define xe_spin_init_opts(fd, ...) \
> xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
> @@ -55,6 +76,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> void xe_spin_wait_started(struct xe_spin *spin);
> void xe_spin_end(struct xe_spin *spin);
> void xe_spin_free(int fd, struct igt_spin *spin);
> +void xe_spin_sync_start(int fd, struct spin_ctx *ctx);
> +void xe_spin_sync_end(int fd, struct spin_ctx *ctx);
>
> struct xe_cork {
> struct xe_spin *spin;
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 5fd7c0416..4a6dfa73c 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
> igt_require(info.num_engines);
> }
>
> -struct spin_ctx {
> - uint32_t vm;
> - uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> - struct drm_xe_sync sync[2];
> - struct drm_xe_exec exec;
> - uint32_t exec_queue;
> - size_t bo_size;
> - uint32_t bo;
> - struct xe_spin *spin;
> - struct xe_spin_opts spin_opts;
> - bool ended;
> - uint16_t class;
> - uint16_t width;
> - uint16_t num_placements;
> -};
> -
> -static struct spin_ctx *
> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> - uint16_t width, uint16_t num_placements)
> -{
> - struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> -
> - igt_assert(width && num_placements &&
> - (width == 1 || num_placements == 1));
> - igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> -
> - ctx->class = hwe->engine_class;
> - ctx->width = width;
> - ctx->num_placements = num_placements;
> - ctx->vm = vm;
> -
> - for (unsigned int i = 0; i < width; i++)
> - ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> -
> - ctx->exec.num_batch_buffer = width;
> - ctx->exec.num_syncs = 2;
> - ctx->exec.syncs = to_user_pointer(ctx->sync);
> -
> - ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[0].handle = syncobj_create(fd, 0);
> -
> - ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[1].handle = syncobj_create(fd, 0);
> -
> - ctx->bo_size = sizeof(struct xe_spin);
> - ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> - ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> - vram_if_possible(fd, hwe->gt_id),
> - DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> - ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> -
> - igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> - hwe, 0, &ctx->exec_queue), 0);
> -
> - xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> - ctx->sync, 1);
> -
> - return ctx;
> -}
> -
> -static void
> -spin_sync_start(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - ctx->spin_opts.addr = ctx->addr[0];
> - ctx->spin_opts.write_timestamp = true;
> - ctx->spin_opts.preempt = true;
> - xe_spin_init(ctx->spin, &ctx->spin_opts);
> -
> - /* re-use sync[0] for exec */
> - ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> -
> - ctx->exec.exec_queue_id = ctx->exec_queue;
> -
> - if (ctx->width > 1)
> - ctx->exec.address = to_user_pointer(ctx->addr);
> - else
> - ctx->exec.address = ctx->addr[0];
> -
> - xe_exec(fd, &ctx->exec);
> -
> - xe_spin_wait_started(ctx->spin);
> - igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> -
> - igt_debug("%s: spinner started\n", engine_map[ctx->class]);
> -}
> -
> -static void
> -spin_sync_end(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx || ctx->ended)
> - return;
> -
> - xe_spin_end(ctx->spin);
> -
> - igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> - xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->ended = true;
> - igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
> - ctx->spin->timestamp);
> -}
> -
> -static void
> -spin_ctx_destroy(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - syncobj_destroy(fd, ctx->sync[0].handle);
> - syncobj_destroy(fd, ctx->sync[1].handle);
> - xe_exec_queue_destroy(fd, ctx->exec_queue);
> -
> - munmap(ctx->spin, ctx->bo_size);
> - gem_close(fd, ctx->bo);
> -
> - free(ctx);
> -}
> -
> static void
> check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> int class, int width, enum expected_load expected_load)
> @@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu1[0]);
> @@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu2[0]);
> if (flags & TEST_ISOLATION)
> @@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> close(new_fd);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -588,15 +461,15 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
> uint32_t vm;
>
> vm = xe_vm_create(fd, 0, 0);
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
>
> /* destroy queue before sampling again */
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> read_engine_cycles(fd, pceu2);
>
> @@ -616,12 +489,12 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>
> vm = xe_vm_create(fd, 0, 0);
>
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> check_results(pceu1, pceu2, class, 1, expected_load);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> if (_class == hwe->engine_class || ctx[_class])
> continue;
>
> - ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[_class]);
> + ctx[_class] = xe_spin_ctx_init(fd, _hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[_class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> continue;
>
> check_results(pceu1, pceu2, class, 1, expected_load);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
> if (ctx[class])
> continue;
>
> - ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[class]);
> + ctx[class] = xe_spin_ctx_init(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
> continue;
>
> check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, eci, vm, width, num_placements);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu[0]);
> @@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu[1]);
> if (flags & TEST_ISOLATION)
> @@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
> close(fd_spill);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> xe_vm_destroy(fd, vm);
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-08 7:44 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
@ 2024-11-08 7:44 ` Pravalika Gurram
2024-11-08 9:01 ` Zbigniew Kempczyński
0 siblings, 1 reply; 18+ messages in thread
From: Pravalika Gurram @ 2024-11-08 7:44 UTC (permalink / raw)
To: igt-dev; +Cc: Pravalika Gurram
move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
to xe spin lib to avoid code redundancy.
v2: use allocator based on developer preference.
change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
---
lib/xe/xe_spin.c | 115 +++++++++++++++++++++
lib/xe/xe_spin.h | 22 ++++
tests/intel/xe_drm_fdinfo.c | 197 +++++++-----------------------------
3 files changed, 172 insertions(+), 162 deletions(-)
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 3adacc3a8..b611ac5c1 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
free(spin);
}
+struct xe_spin_ctx *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
+ uint16_t width, uint16_t num_placements)
+{
+ struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
+
+ igt_assert(width && num_placements &&
+ (width == 1 || num_placements == 1));
+ igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
+
+ ctx->class = hwe->engine_class;
+ ctx->width = width;
+ ctx->num_placements = num_placements;
+ ctx->vm = vm;
+
+ ctx->exec.num_batch_buffer = width;
+ ctx->exec.num_syncs = 2;
+ ctx->exec.syncs = to_user_pointer(ctx->sync);
+
+ ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+ ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+ ctx->sync[0].handle = syncobj_create(fd, 0);
+
+ ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+ ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+ ctx->sync[1].handle = syncobj_create(fd, 0);
+
+ ctx->bo_size = sizeof(struct xe_spin);
+ ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
+ ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
+ vram_if_possible(fd, hwe->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ if (ahnd) {
+ for (unsigned int i = 0; i < width; i++)
+ ctx->addr[i] = intel_allocator_alloc_with_strategy(ahnd,
+ ctx->bo, ctx->bo_size, 0,
+ ALLOC_STRATEGY_LOW_TO_HIGH);
+ } else {
+ for (unsigned int i = 0; i < width; i++)
+ ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
+ }
+
+ ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
+
+ igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
+ hwe, 0, &ctx->exec_queue), 0);
+
+ xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
+ ctx->sync, 1);
+
+ return ctx;
+}
+
+void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx)
+{
+ if (!ctx)
+ return;
+
+ ctx->spin_opts.addr = ctx->addr[0];
+ ctx->spin_opts.write_timestamp = true;
+ ctx->spin_opts.preempt = true;
+ xe_spin_init(ctx->spin, &ctx->spin_opts);
+
+ /* re-use sync[0] for exec */
+ ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+
+ ctx->exec.exec_queue_id = ctx->exec_queue;
+
+ if (ctx->width > 1)
+ ctx->exec.address = to_user_pointer(ctx->addr);
+ else
+ ctx->exec.address = ctx->addr[0];
+
+ xe_exec(fd, &ctx->exec);
+
+ xe_spin_wait_started(ctx->spin);
+ igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
+
+ igt_debug("%d: spinner started\n", ctx->class);
+}
+
+void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx)
+{
+ if (!ctx || ctx->ended)
+ return;
+
+ xe_spin_end(ctx->spin);
+
+ igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
+ igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
+ igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ ctx->ended = true;
+ igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
+ ctx->spin->timestamp);
+}
+
+void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx)
+{
+ if (!ctx)
+ return;
+
+ syncobj_destroy(fd, ctx->sync[0].handle);
+ syncobj_destroy(fd, ctx->sync[1].handle);
+ xe_exec_queue_destroy(fd, ctx->exec_queue);
+
+ munmap(ctx->spin, ctx->bo_size);
+ gem_close(fd, ctx->bo);
+
+ free(ctx);
+}
+
void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
struct xe_cork *cork)
{
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index d65adb05c..18706dcdf 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -43,9 +43,29 @@ struct xe_spin {
uint32_t timestamp;
};
+struct xe_spin_ctx {
+ uint32_t vm;
+ uint64_t addr[XE_MAX_ENGINE_INSTANCE];
+ struct drm_xe_sync sync[2];
+ struct drm_xe_exec exec;
+ uint32_t exec_queue;
+ size_t bo_size;
+ uint32_t bo;
+ struct xe_spin *spin;
+ struct xe_spin_opts spin_opts;
+ bool ended;
+ uint16_t class;
+ uint16_t width;
+ uint16_t num_placements;
+};
+
igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
+struct xe_spin_ctx *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
+ uint16_t width, uint16_t num_placements);
+void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
#define xe_spin_init_opts(fd, ...) \
xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
@@ -55,6 +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
void xe_spin_wait_started(struct xe_spin *spin);
void xe_spin_end(struct xe_spin *spin);
void xe_spin_free(int fd, struct igt_spin *spin);
+void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx);
+void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
struct xe_cork {
struct xe_spin *spin;
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 5fd7c0416..91ff4a5af 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
igt_require(info.num_engines);
}
-struct spin_ctx {
- uint32_t vm;
- uint64_t addr[XE_MAX_ENGINE_INSTANCE];
- struct drm_xe_sync sync[2];
- struct drm_xe_exec exec;
- uint32_t exec_queue;
- size_t bo_size;
- uint32_t bo;
- struct xe_spin *spin;
- struct xe_spin_opts spin_opts;
- bool ended;
- uint16_t class;
- uint16_t width;
- uint16_t num_placements;
-};
-
-static struct spin_ctx *
-spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
- uint16_t width, uint16_t num_placements)
-{
- struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
-
- igt_assert(width && num_placements &&
- (width == 1 || num_placements == 1));
- igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
-
- ctx->class = hwe->engine_class;
- ctx->width = width;
- ctx->num_placements = num_placements;
- ctx->vm = vm;
-
- for (unsigned int i = 0; i < width; i++)
- ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
-
- ctx->exec.num_batch_buffer = width;
- ctx->exec.num_syncs = 2;
- ctx->exec.syncs = to_user_pointer(ctx->sync);
-
- ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
- ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
- ctx->sync[0].handle = syncobj_create(fd, 0);
-
- ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
- ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
- ctx->sync[1].handle = syncobj_create(fd, 0);
-
- ctx->bo_size = sizeof(struct xe_spin);
- ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
- ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
- vram_if_possible(fd, hwe->gt_id),
- DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
- ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
-
- igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
- hwe, 0, &ctx->exec_queue), 0);
-
- xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
- ctx->sync, 1);
-
- return ctx;
-}
-
-static void
-spin_sync_start(int fd, struct spin_ctx *ctx)
-{
- if (!ctx)
- return;
-
- ctx->spin_opts.addr = ctx->addr[0];
- ctx->spin_opts.write_timestamp = true;
- ctx->spin_opts.preempt = true;
- xe_spin_init(ctx->spin, &ctx->spin_opts);
-
- /* re-use sync[0] for exec */
- ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
-
- ctx->exec.exec_queue_id = ctx->exec_queue;
-
- if (ctx->width > 1)
- ctx->exec.address = to_user_pointer(ctx->addr);
- else
- ctx->exec.address = ctx->addr[0];
-
- xe_exec(fd, &ctx->exec);
-
- xe_spin_wait_started(ctx->spin);
- igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
-
- igt_debug("%s: spinner started\n", engine_map[ctx->class]);
-}
-
-static void
-spin_sync_end(int fd, struct spin_ctx *ctx)
-{
- if (!ctx || ctx->ended)
- return;
-
- xe_spin_end(ctx->spin);
-
- igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
- igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
- ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
- xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
- igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
- ctx->ended = true;
- igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
- ctx->spin->timestamp);
-}
-
-static void
-spin_ctx_destroy(int fd, struct spin_ctx *ctx)
-{
- if (!ctx)
- return;
-
- syncobj_destroy(fd, ctx->sync[0].handle);
- syncobj_destroy(fd, ctx->sync[1].handle);
- xe_exec_queue_destroy(fd, ctx->exec_queue);
-
- munmap(ctx->spin, ctx->bo_size);
- gem_close(fd, ctx->bo);
-
- free(ctx);
-}
-
static void
check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
int class, int width, enum expected_load expected_load)
@@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
{
struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx = NULL;
+ struct xe_spin_ctx *ctx = NULL;
enum expected_load expected_load;
uint32_t vm;
int new_fd;
@@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
vm = xe_vm_create(fd, 0, 0);
if (flags & TEST_BUSY) {
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
}
read_engine_cycles(fd, pceu1[0]);
@@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
usleep(batch_duration_usec);
if (flags & TEST_TRAILING_IDLE)
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu2[0]);
if (flags & TEST_ISOLATION)
@@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
close(new_fd);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
@@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx = NULL;
+ struct xe_spin_ctx *ctx = NULL;
uint32_t vm;
vm = xe_vm_create(fd, 0, 0);
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
/* destroy queue before sampling again */
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
read_engine_cycles(fd, pceu2);
@@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx = NULL;
+ struct xe_spin_ctx *ctx = NULL;
uint32_t vm;
int class;
vm = xe_vm_create(fd, 0, 0);
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
check_results(pceu1, pceu2, class, 1, expected_load);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
@@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+ struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
struct drm_xe_engine_class_instance *_hwe;
uint32_t vm;
int class;
@@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
if (_class == hwe->engine_class || ctx[_class])
continue;
- ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
- spin_sync_start(fd, ctx[_class]);
+ ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx[_class]);
}
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
xe_for_each_engine_class(class)
- spin_sync_end(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
continue;
check_results(pceu1, pceu2, class, 1, expected_load);
- spin_sync_end(fd, ctx[class]);
- spin_ctx_destroy(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
+ xe_spin_ctx_destroy(fd, ctx[class]);
}
xe_vm_destroy(fd, vm);
@@ -685,7 +558,7 @@ utilization_all_full_load(int fd)
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+ struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
struct drm_xe_engine_class_instance *hwe;
uint32_t vm;
int class;
@@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
if (ctx[class])
continue;
- ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx[class]);
+ ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx[class]);
}
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
xe_for_each_engine_class(class)
- spin_sync_end(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
continue;
check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
- spin_sync_end(fd, ctx[class]);
- spin_ctx_destroy(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
+ xe_spin_ctx_destroy(fd, ctx[class]);
}
xe_vm_destroy(fd, vm);
@@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
- struct spin_ctx *ctx = NULL;
+ struct xe_spin_ctx *ctx = NULL;
enum expected_load expected_load;
int fd_spill, num_placements;
uint32_t vm;
@@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
vm = xe_vm_create(fd, 0, 0);
if (flags & TEST_BUSY) {
- ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init(fd, eci, 0, vm, width, num_placements);
+ xe_spin_sync_start(fd, ctx);
}
read_engine_cycles(fd, pceu[0]);
@@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
usleep(batch_duration_usec);
if (flags & TEST_TRAILING_IDLE)
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu[1]);
if (flags & TEST_ISOLATION)
@@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
close(fd_spill);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-08 7:44 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
@ 2024-11-08 9:01 ` Zbigniew Kempczyński
2024-11-08 15:38 ` Lucas De Marchi
0 siblings, 1 reply; 18+ messages in thread
From: Zbigniew Kempczyński @ 2024-11-08 9:01 UTC (permalink / raw)
To: Pravalika Gurram, Lucas De Marchi; +Cc: igt-dev
+Lucas
On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
> to xe spin lib to avoid code redundancy.
>
> v2: use allocator based on developer preference.
> change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
>
> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
> ---
> lib/xe/xe_spin.c | 115 +++++++++++++++++++++
> lib/xe/xe_spin.h | 22 ++++
> tests/intel/xe_drm_fdinfo.c | 197 +++++++-----------------------------
> 3 files changed, 172 insertions(+), 162 deletions(-)
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 3adacc3a8..b611ac5c1 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
> free(spin);
> }
>
> +struct xe_spin_ctx *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
> + uint16_t width, uint16_t num_placements)
> +{
> + struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
> +
> + igt_assert(width && num_placements &&
> + (width == 1 || num_placements == 1));
> + igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> +
> + ctx->class = hwe->engine_class;
> + ctx->width = width;
> + ctx->num_placements = num_placements;
> + ctx->vm = vm;
> +
> + ctx->exec.num_batch_buffer = width;
> + ctx->exec.num_syncs = 2;
> + ctx->exec.syncs = to_user_pointer(ctx->sync);
> +
> + ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[0].handle = syncobj_create(fd, 0);
> +
> + ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[1].handle = syncobj_create(fd, 0);
> +
> + ctx->bo_size = sizeof(struct xe_spin);
> + ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> + ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> + vram_if_possible(fd, hwe->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + if (ahnd) {
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = intel_allocator_alloc_with_strategy(ahnd,
> + ctx->bo, ctx->bo_size, 0,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
> + } else {
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> + }
> +
> + ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> +
> + igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> + hwe, 0, &ctx->exec_queue), 0);
> +
> + xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> + ctx->sync, 1);
@Lucas
I'm looking here and I've doubts what's going on in 'utilization_multi'
subtest where width > 1. I mean we bind only addr[0], but according
to exec with width > 1 I assume addr[1] should be bound as well.
What I'm missing here?
--
Zbigniew
> +
> + return ctx;
> +}
> +
> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx)
> +{
> + if (!ctx)
> + return;
> +
> + ctx->spin_opts.addr = ctx->addr[0];
> + ctx->spin_opts.write_timestamp = true;
> + ctx->spin_opts.preempt = true;
> + xe_spin_init(ctx->spin, &ctx->spin_opts);
> +
> + /* re-use sync[0] for exec */
> + ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> +
> + ctx->exec.exec_queue_id = ctx->exec_queue;
> +
> + if (ctx->width > 1)
> + ctx->exec.address = to_user_pointer(ctx->addr);
> + else
> + ctx->exec.address = ctx->addr[0];
> +
> + xe_exec(fd, &ctx->exec);
> +
> + xe_spin_wait_started(ctx->spin);
> + igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> +
> + igt_debug("%d: spinner started\n", ctx->class);
> +}
> +
> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx)
> +{
> + if (!ctx || ctx->ended)
> + return;
> +
> + xe_spin_end(ctx->spin);
> +
> + igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + ctx->ended = true;
> + igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
> + ctx->spin->timestamp);
> +}
> +
> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx)
> +{
> + if (!ctx)
> + return;
> +
> + syncobj_destroy(fd, ctx->sync[0].handle);
> + syncobj_destroy(fd, ctx->sync[1].handle);
> + xe_exec_queue_destroy(fd, ctx->exec_queue);
> +
> + munmap(ctx->spin, ctx->bo_size);
> + gem_close(fd, ctx->bo);
> +
> + free(ctx);
> +}
> +
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork)
> {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index d65adb05c..18706dcdf 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -43,9 +43,29 @@ struct xe_spin {
> uint32_t timestamp;
> };
>
> +struct xe_spin_ctx {
> + uint32_t vm;
> + uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> + struct drm_xe_sync sync[2];
> + struct drm_xe_exec exec;
> + uint32_t exec_queue;
> + size_t bo_size;
> + uint32_t bo;
> + struct xe_spin *spin;
> + struct xe_spin_opts spin_opts;
> + bool ended;
> + uint16_t class;
> + uint16_t width;
> + uint16_t num_placements;
> +};
> +
> igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
> void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
> +struct xe_spin_ctx *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
> + uint16_t width, uint16_t num_placements);
> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
>
> #define xe_spin_init_opts(fd, ...) \
> xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
> @@ -55,6 +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> void xe_spin_wait_started(struct xe_spin *spin);
> void xe_spin_end(struct xe_spin *spin);
> void xe_spin_free(int fd, struct igt_spin *spin);
> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx);
> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
>
> struct xe_cork {
> struct xe_spin *spin;
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 5fd7c0416..91ff4a5af 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
> igt_require(info.num_engines);
> }
>
> -struct spin_ctx {
> - uint32_t vm;
> - uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> - struct drm_xe_sync sync[2];
> - struct drm_xe_exec exec;
> - uint32_t exec_queue;
> - size_t bo_size;
> - uint32_t bo;
> - struct xe_spin *spin;
> - struct xe_spin_opts spin_opts;
> - bool ended;
> - uint16_t class;
> - uint16_t width;
> - uint16_t num_placements;
> -};
> -
> -static struct spin_ctx *
> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> - uint16_t width, uint16_t num_placements)
> -{
> - struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> -
> - igt_assert(width && num_placements &&
> - (width == 1 || num_placements == 1));
> - igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> -
> - ctx->class = hwe->engine_class;
> - ctx->width = width;
> - ctx->num_placements = num_placements;
> - ctx->vm = vm;
> -
> - for (unsigned int i = 0; i < width; i++)
> - ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> -
> - ctx->exec.num_batch_buffer = width;
> - ctx->exec.num_syncs = 2;
> - ctx->exec.syncs = to_user_pointer(ctx->sync);
> -
> - ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[0].handle = syncobj_create(fd, 0);
> -
> - ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[1].handle = syncobj_create(fd, 0);
> -
> - ctx->bo_size = sizeof(struct xe_spin);
> - ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> - ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> - vram_if_possible(fd, hwe->gt_id),
> - DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> - ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> -
> - igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> - hwe, 0, &ctx->exec_queue), 0);
> -
> - xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> - ctx->sync, 1);
> -
> - return ctx;
> -}
> -
> -static void
> -spin_sync_start(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - ctx->spin_opts.addr = ctx->addr[0];
> - ctx->spin_opts.write_timestamp = true;
> - ctx->spin_opts.preempt = true;
> - xe_spin_init(ctx->spin, &ctx->spin_opts);
> -
> - /* re-use sync[0] for exec */
> - ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> -
> - ctx->exec.exec_queue_id = ctx->exec_queue;
> -
> - if (ctx->width > 1)
> - ctx->exec.address = to_user_pointer(ctx->addr);
> - else
> - ctx->exec.address = ctx->addr[0];
> -
> - xe_exec(fd, &ctx->exec);
> -
> - xe_spin_wait_started(ctx->spin);
> - igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> -
> - igt_debug("%s: spinner started\n", engine_map[ctx->class]);
> -}
> -
> -static void
> -spin_sync_end(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx || ctx->ended)
> - return;
> -
> - xe_spin_end(ctx->spin);
> -
> - igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> - xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->ended = true;
> - igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
> - ctx->spin->timestamp);
> -}
> -
> -static void
> -spin_ctx_destroy(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - syncobj_destroy(fd, ctx->sync[0].handle);
> - syncobj_destroy(fd, ctx->sync[1].handle);
> - xe_exec_queue_destroy(fd, ctx->exec_queue);
> -
> - munmap(ctx->spin, ctx->bo_size);
> - gem_close(fd, ctx->bo);
> -
> - free(ctx);
> -}
> -
> static void
> check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> int class, int width, enum expected_load expected_load)
> @@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> {
> struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_spin_ctx *ctx = NULL;
> enum expected_load expected_load;
> uint32_t vm;
> int new_fd;
> @@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu1[0]);
> @@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu2[0]);
> if (flags & TEST_ISOLATION)
> @@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> close(new_fd);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_spin_ctx *ctx = NULL;
> uint32_t vm;
>
> vm = xe_vm_create(fd, 0, 0);
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
>
> /* destroy queue before sampling again */
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> read_engine_cycles(fd, pceu2);
>
> @@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_spin_ctx *ctx = NULL;
> uint32_t vm;
> int class;
>
> vm = xe_vm_create(fd, 0, 0);
>
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> check_results(pceu1, pceu2, class, 1, expected_load);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> + struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> struct drm_xe_engine_class_instance *_hwe;
> uint32_t vm;
> int class;
> @@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> if (_class == hwe->engine_class || ctx[_class])
> continue;
>
> - ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[_class]);
> + ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[_class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> continue;
>
> check_results(pceu1, pceu2, class, 1, expected_load);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -685,7 +558,7 @@ utilization_all_full_load(int fd)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> + struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> struct drm_xe_engine_class_instance *hwe;
> uint32_t vm;
> int class;
> @@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
> if (ctx[class])
> continue;
>
> - ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[class]);
> + ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
> continue;
>
> check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
> struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
> - struct spin_ctx *ctx = NULL;
> + struct xe_spin_ctx *ctx = NULL;
> enum expected_load expected_load;
> int fd_spill, num_placements;
> uint32_t vm;
> @@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init(fd, eci, 0, vm, width, num_placements);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu[0]);
> @@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu[1]);
> if (flags & TEST_ISOLATION)
> @@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
> close(fd_spill);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> xe_vm_destroy(fd, vm);
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-08 9:01 ` Zbigniew Kempczyński
@ 2024-11-08 15:38 ` Lucas De Marchi
2024-11-13 16:13 ` Gurram, Pravalika
0 siblings, 1 reply; 18+ messages in thread
From: Lucas De Marchi @ 2024-11-08 15:38 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: Pravalika Gurram, igt-dev, Matthew Brost
On Fri, Nov 08, 2024 at 10:01:41AM +0100, Zbigniew Kempczyński wrote:
>+Lucas
Pravalika, please keep me in Cc. I don't watch the igt mailing list
close enough, particularly when it's a follow up to a suggestion I gave.
>
>On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
>> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
>> to xe spin lib to avoid code redundancy.
>>
>> v2: use allocator based on developer preference.
>> change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
but we already have another thing named ctx there, the rename doesn't
improve it.
From lib/xe/xe_spin.h, what should be added on is
struct xe_cork {
struct xe_spin *spin;
int fd;
uint32_t vm;
uint32_t bo;
uint32_t exec_queue;
uint32_t syncobj;
};
I don't really like that name, but we can do a rename on top... or we
can rename it now and then move things.
>>
>> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
>> ---
>> lib/xe/xe_spin.c | 115 +++++++++++++++++++++
>> lib/xe/xe_spin.h | 22 ++++
>> tests/intel/xe_drm_fdinfo.c | 197 +++++++-----------------------------
>> 3 files changed, 172 insertions(+), 162 deletions(-)
>>
>> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
>> index 3adacc3a8..b611ac5c1 100644
>> --- a/lib/xe/xe_spin.c
>> +++ b/lib/xe/xe_spin.c
>> @@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
>> free(spin);
>> }
>>
>> +struct xe_spin_ctx *
>> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
>> + uint16_t width, uint16_t num_placements)
>> +{
>> + struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
>> +
>> + igt_assert(width && num_placements &&
>> + (width == 1 || num_placements == 1));
>> + igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
I think those asserts are fine for a lib since it would be a programming
error.
>> +
>> + ctx->class = hwe->engine_class;
>> + ctx->width = width;
>> + ctx->num_placements = num_placements;
>> + ctx->vm = vm;
>> +
>> + ctx->exec.num_batch_buffer = width;
>> + ctx->exec.num_syncs = 2;
>> + ctx->exec.syncs = to_user_pointer(ctx->sync);
>> +
>> + ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> + ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> + ctx->sync[0].handle = syncobj_create(fd, 0);
>> +
>> + ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> + ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> + ctx->sync[1].handle = syncobj_create(fd, 0);
>> +
>> + ctx->bo_size = sizeof(struct xe_spin);
>> + ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
>> + ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
>> + vram_if_possible(fd, hwe->gt_id),
>> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> + if (ahnd) {
we need a better set of functions for handling an optional arg like
this.
>> + for (unsigned int i = 0; i < width; i++)
>> + ctx->addr[i] = intel_allocator_alloc_with_strategy(ahnd,
>> + ctx->bo, ctx->bo_size, 0,
>> + ALLOC_STRATEGY_LOW_TO_HIGH);
>> + } else {
>> + for (unsigned int i = 0; i < width; i++)
>> + ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
>> + }
>> +
>> + ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
>> +
>> + igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
>> + hwe, 0, &ctx->exec_queue), 0);
this assert should probably be handled as an error, and let the test do
the assert. This way this can be easily used by others libs and tools. I
was chatting recently with other people that it'd be good to have a
gpu-stress (whatever the name, may be xe-spinner if not generalized) so
we can easily exercise the engines.
>> +
>> + xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
>> + ctx->sync, 1);
>
>@Lucas
>
>I'm looking here and I've doubts what's going on in 'utilization_multi'
>subtest where width > 1. I mean we bind only addr[0], but according
>to exec with width > 1 I assume addr[1] should be bound as well.
we may need to change that to generalize in the lib. In the case of that
specific test we setup the addr per class:
num_placements = xe_gt_fill_engines_by_class()
if TEST_PARALLEL {
width = num_placements
num_placements = 1
}
...
for (unsigned int i = 0; i < width; i++)
ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
So if width > 1, all of them point to the same address.
To make it generic I think we will have to change that, yes.
+Matt Brost
Lucas De Marchi
>
>What I'm missing here?
>
>--
>Zbigniew
>
>> +
>> + return ctx;
>> +}
>> +
>> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx)
>> +{
>> + if (!ctx)
>> + return;
>> +
>> + ctx->spin_opts.addr = ctx->addr[0];
>> + ctx->spin_opts.write_timestamp = true;
>> + ctx->spin_opts.preempt = true;
>> + xe_spin_init(ctx->spin, &ctx->spin_opts);
>> +
>> + /* re-use sync[0] for exec */
>> + ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>> +
>> + ctx->exec.exec_queue_id = ctx->exec_queue;
>> +
>> + if (ctx->width > 1)
>> + ctx->exec.address = to_user_pointer(ctx->addr);
>> + else
>> + ctx->exec.address = ctx->addr[0];
>> +
>> + xe_exec(fd, &ctx->exec);
>> +
>> + xe_spin_wait_started(ctx->spin);
>> + igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
>> +
>> + igt_debug("%d: spinner started\n", ctx->class);
>> +}
>> +
>> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx)
>> +{
>> + if (!ctx || ctx->ended)
>> + return;
>> +
>> + xe_spin_end(ctx->spin);
>> +
>> + igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
>> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> + ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> + xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
>> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> + ctx->ended = true;
>> + igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
>> + ctx->spin->timestamp);
>> +}
>> +
>> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx)
>> +{
>> + if (!ctx)
>> + return;
>> +
>> + syncobj_destroy(fd, ctx->sync[0].handle);
>> + syncobj_destroy(fd, ctx->sync[1].handle);
>> + xe_exec_queue_destroy(fd, ctx->exec_queue);
>> +
>> + munmap(ctx->spin, ctx->bo_size);
>> + gem_close(fd, ctx->bo);
>> +
>> + free(ctx);
>> +}
>> +
>> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>> struct xe_cork *cork)
>> {
>> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
>> index d65adb05c..18706dcdf 100644
>> --- a/lib/xe/xe_spin.h
>> +++ b/lib/xe/xe_spin.h
>> @@ -43,9 +43,29 @@ struct xe_spin {
>> uint32_t timestamp;
>> };
>>
>> +struct xe_spin_ctx {
>> + uint32_t vm;
>> + uint64_t addr[XE_MAX_ENGINE_INSTANCE];
>> + struct drm_xe_sync sync[2];
>> + struct drm_xe_exec exec;
>> + uint32_t exec_queue;
>> + size_t bo_size;
>> + uint32_t bo;
>> + struct xe_spin *spin;
>> + struct xe_spin_opts spin_opts;
>> + bool ended;
>> + uint16_t class;
>> + uint16_t width;
>> + uint16_t num_placements;
>> +};
>> +
>> igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
>> uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
>> void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
>> +struct xe_spin_ctx *
>> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
>> + uint16_t width, uint16_t num_placements);
>> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
>>
>> #define xe_spin_init_opts(fd, ...) \
>> xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
>> @@ -55,6 +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
>> void xe_spin_wait_started(struct xe_spin *spin);
>> void xe_spin_end(struct xe_spin *spin);
>> void xe_spin_free(int fd, struct igt_spin *spin);
>> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx);
>> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
>>
>> struct xe_cork {
>> struct xe_spin *spin;
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index 5fd7c0416..91ff4a5af 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
>> igt_require(info.num_engines);
>> }
>>
>> -struct spin_ctx {
>> - uint32_t vm;
>> - uint64_t addr[XE_MAX_ENGINE_INSTANCE];
>> - struct drm_xe_sync sync[2];
>> - struct drm_xe_exec exec;
>> - uint32_t exec_queue;
>> - size_t bo_size;
>> - uint32_t bo;
>> - struct xe_spin *spin;
>> - struct xe_spin_opts spin_opts;
>> - bool ended;
>> - uint16_t class;
>> - uint16_t width;
>> - uint16_t num_placements;
>> -};
>> -
>> -static struct spin_ctx *
>> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
>> - uint16_t width, uint16_t num_placements)
>> -{
>> - struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
>> -
>> - igt_assert(width && num_placements &&
>> - (width == 1 || num_placements == 1));
>> - igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
>> -
>> - ctx->class = hwe->engine_class;
>> - ctx->width = width;
>> - ctx->num_placements = num_placements;
>> - ctx->vm = vm;
>> -
>> - for (unsigned int i = 0; i < width; i++)
>> - ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
>> -
>> - ctx->exec.num_batch_buffer = width;
>> - ctx->exec.num_syncs = 2;
>> - ctx->exec.syncs = to_user_pointer(ctx->sync);
>> -
>> - ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> - ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> - ctx->sync[0].handle = syncobj_create(fd, 0);
>> -
>> - ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> - ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> - ctx->sync[1].handle = syncobj_create(fd, 0);
>> -
>> - ctx->bo_size = sizeof(struct xe_spin);
>> - ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
>> - ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
>> - vram_if_possible(fd, hwe->gt_id),
>> - DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> - ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
>> -
>> - igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
>> - hwe, 0, &ctx->exec_queue), 0);
>> -
>> - xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
>> - ctx->sync, 1);
>> -
>> - return ctx;
>> -}
>> -
>> -static void
>> -spin_sync_start(int fd, struct spin_ctx *ctx)
>> -{
>> - if (!ctx)
>> - return;
>> -
>> - ctx->spin_opts.addr = ctx->addr[0];
>> - ctx->spin_opts.write_timestamp = true;
>> - ctx->spin_opts.preempt = true;
>> - xe_spin_init(ctx->spin, &ctx->spin_opts);
>> -
>> - /* re-use sync[0] for exec */
>> - ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>> -
>> - ctx->exec.exec_queue_id = ctx->exec_queue;
>> -
>> - if (ctx->width > 1)
>> - ctx->exec.address = to_user_pointer(ctx->addr);
>> - else
>> - ctx->exec.address = ctx->addr[0];
>> -
>> - xe_exec(fd, &ctx->exec);
>> -
>> - xe_spin_wait_started(ctx->spin);
>> - igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
>> -
>> - igt_debug("%s: spinner started\n", engine_map[ctx->class]);
>> -}
>> -
>> -static void
>> -spin_sync_end(int fd, struct spin_ctx *ctx)
>> -{
>> - if (!ctx || ctx->ended)
>> - return;
>> -
>> - xe_spin_end(ctx->spin);
>> -
>> - igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
>> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> -
>> - ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> - xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
>> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> -
>> - ctx->ended = true;
>> - igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
>> - ctx->spin->timestamp);
>> -}
>> -
>> -static void
>> -spin_ctx_destroy(int fd, struct spin_ctx *ctx)
>> -{
>> - if (!ctx)
>> - return;
>> -
>> - syncobj_destroy(fd, ctx->sync[0].handle);
>> - syncobj_destroy(fd, ctx->sync[1].handle);
>> - xe_exec_queue_destroy(fd, ctx->exec_queue);
>> -
>> - munmap(ctx->spin, ctx->bo_size);
>> - gem_close(fd, ctx->bo);
>> -
>> - free(ctx);
>> -}
>> -
>> static void
>> check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>> int class, int width, enum expected_load expected_load)
>> @@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>> {
>> struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> - struct spin_ctx *ctx = NULL;
>> + struct xe_spin_ctx *ctx = NULL;
>> enum expected_load expected_load;
>> uint32_t vm;
>> int new_fd;
>> @@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>
>> vm = xe_vm_create(fd, 0, 0);
>> if (flags & TEST_BUSY) {
>> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>> - spin_sync_start(fd, ctx);
>> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> + xe_spin_sync_start(fd, ctx);
>> }
>>
>> read_engine_cycles(fd, pceu1[0]);
>> @@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>
>> usleep(batch_duration_usec);
>> if (flags & TEST_TRAILING_IDLE)
>> - spin_sync_end(fd, ctx);
>> + xe_spin_sync_end(fd, ctx);
>>
>> read_engine_cycles(fd, pceu2[0]);
>> if (flags & TEST_ISOLATION)
>> @@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>> close(new_fd);
>> }
>>
>> - spin_sync_end(fd, ctx);
>> - spin_ctx_destroy(fd, ctx);
>> + xe_spin_sync_end(fd, ctx);
>> + xe_spin_ctx_destroy(fd, ctx);
>> xe_vm_destroy(fd, vm);
>> }
>>
>> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>> {
>> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> - struct spin_ctx *ctx = NULL;
>> + struct xe_spin_ctx *ctx = NULL;
>> uint32_t vm;
>>
>> vm = xe_vm_create(fd, 0, 0);
>> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>> - spin_sync_start(fd, ctx);
>> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> + xe_spin_sync_start(fd, ctx);
>>
>> read_engine_cycles(fd, pceu1);
>> usleep(batch_duration_usec);
>>
>> /* destroy queue before sampling again */
>> - spin_sync_end(fd, ctx);
>> - spin_ctx_destroy(fd, ctx);
>> + xe_spin_sync_end(fd, ctx);
>> + xe_spin_ctx_destroy(fd, ctx);
>>
>> read_engine_cycles(fd, pceu2);
>>
>> @@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>> {
>> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> - struct spin_ctx *ctx = NULL;
>> + struct xe_spin_ctx *ctx = NULL;
>> uint32_t vm;
>> int class;
>>
>> vm = xe_vm_create(fd, 0, 0);
>>
>> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>> - spin_sync_start(fd, ctx);
>> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> + xe_spin_sync_start(fd, ctx);
>>
>> read_engine_cycles(fd, pceu1);
>> usleep(batch_duration_usec);
>> - spin_sync_end(fd, ctx);
>> + xe_spin_sync_end(fd, ctx);
>> read_engine_cycles(fd, pceu2);
>>
>> xe_for_each_engine_class(class) {
>> @@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>> check_results(pceu1, pceu2, class, 1, expected_load);
>> }
>>
>> - spin_sync_end(fd, ctx);
>> - spin_ctx_destroy(fd, ctx);
>> + xe_spin_sync_end(fd, ctx);
>> + xe_spin_ctx_destroy(fd, ctx);
>> xe_vm_destroy(fd, vm);
>> }
>>
>> @@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>> {
>> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>> + struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>> struct drm_xe_engine_class_instance *_hwe;
>> uint32_t vm;
>> int class;
>> @@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>> if (_class == hwe->engine_class || ctx[_class])
>> continue;
>>
>> - ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
>> - spin_sync_start(fd, ctx[_class]);
>> + ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
>> + xe_spin_sync_start(fd, ctx[_class]);
>> }
>>
>> read_engine_cycles(fd, pceu1);
>> usleep(batch_duration_usec);
>> xe_for_each_engine_class(class)
>> - spin_sync_end(fd, ctx[class]);
>> + xe_spin_sync_end(fd, ctx[class]);
>> read_engine_cycles(fd, pceu2);
>>
>> xe_for_each_engine_class(class) {
>> @@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>> continue;
>>
>> check_results(pceu1, pceu2, class, 1, expected_load);
>> - spin_sync_end(fd, ctx[class]);
>> - spin_ctx_destroy(fd, ctx[class]);
>> + xe_spin_sync_end(fd, ctx[class]);
>> + xe_spin_ctx_destroy(fd, ctx[class]);
>> }
>>
>> xe_vm_destroy(fd, vm);
>> @@ -685,7 +558,7 @@ utilization_all_full_load(int fd)
>> {
>> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>> + struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>> struct drm_xe_engine_class_instance *hwe;
>> uint32_t vm;
>> int class;
>> @@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
>> if (ctx[class])
>> continue;
>>
>> - ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
>> - spin_sync_start(fd, ctx[class]);
>> + ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> + xe_spin_sync_start(fd, ctx[class]);
>> }
>>
>> read_engine_cycles(fd, pceu1);
>> usleep(batch_duration_usec);
>> xe_for_each_engine_class(class)
>> - spin_sync_end(fd, ctx[class]);
>> + xe_spin_sync_end(fd, ctx[class]);
>> read_engine_cycles(fd, pceu2);
>>
>> xe_for_each_engine_class(class) {
>> @@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
>> continue;
>>
>> check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
>> - spin_sync_end(fd, ctx[class]);
>> - spin_ctx_destroy(fd, ctx[class]);
>> + xe_spin_sync_end(fd, ctx[class]);
>> + xe_spin_ctx_destroy(fd, ctx[class]);
>> }
>>
>> xe_vm_destroy(fd, vm);
>> @@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>> struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
>> - struct spin_ctx *ctx = NULL;
>> + struct xe_spin_ctx *ctx = NULL;
>> enum expected_load expected_load;
>> int fd_spill, num_placements;
>> uint32_t vm;
>> @@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>>
>> vm = xe_vm_create(fd, 0, 0);
>> if (flags & TEST_BUSY) {
>> - ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
>> - spin_sync_start(fd, ctx);
>> + ctx = xe_spin_ctx_init(fd, eci, 0, vm, width, num_placements);
>> + xe_spin_sync_start(fd, ctx);
>> }
>>
>> read_engine_cycles(fd, pceu[0]);
>> @@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>>
>> usleep(batch_duration_usec);
>> if (flags & TEST_TRAILING_IDLE)
>> - spin_sync_end(fd, ctx);
>> + xe_spin_sync_end(fd, ctx);
>>
>> read_engine_cycles(fd, pceu[1]);
>> if (flags & TEST_ISOLATION)
>> @@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>> close(fd_spill);
>> }
>>
>> - spin_sync_end(fd, ctx);
>> - spin_ctx_destroy(fd, ctx);
>> + xe_spin_sync_end(fd, ctx);
>> + xe_spin_ctx_destroy(fd, ctx);
>>
>> xe_vm_destroy(fd, vm);
>> }
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-08 15:38 ` Lucas De Marchi
@ 2024-11-13 16:13 ` Gurram, Pravalika
2024-11-13 16:57 ` Lucas De Marchi
0 siblings, 1 reply; 18+ messages in thread
From: Gurram, Pravalika @ 2024-11-13 16:13 UTC (permalink / raw)
To: De Marchi, Lucas, Kempczynski, Zbigniew
Cc: igt-dev@lists.freedesktop.org, Brost, Matthew
> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Friday, November 8, 2024 9:09 PM
> To: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> Cc: Gurram, Pravalika <pravalika.gurram@intel.com>; igt-
> dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
> Subject: Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions
> to lib
>
> On Fri, Nov 08, 2024 at 10:01:41AM +0100, Zbigniew Kempczyński wrote:
> >+Lucas
>
> Pravalika, please keep me in Cc. I don't watch the igt mailing list close
> enough, particularly when it's a follow up to a suggestion I gave.
>
> >
> >On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
> >> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
> >> to xe spin lib to avoid code redundancy.
> >>
> >> v2: use allocator based on developer preference.
> >> change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
>
> but we already have another thing named ctx there, the rename doesn't
> improve it.
>
> From lib/xe/xe_spin.h, what should be added on is
>
> struct xe_cork {
> struct xe_spin *spin;
> int fd;
> uint32_t vm;
> uint32_t bo;
> uint32_t exec_queue;
> uint32_t syncobj;
> };
>
> I don't really like that name, but we can do a rename on top... or we can
> rename it now and then move things.
>
could you please suggest the name in place of xe_cork
-- Pravalika
> >>
> >> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
> >> ---
> >> lib/xe/xe_spin.c | 115 +++++++++++++++++++++
> >> lib/xe/xe_spin.h | 22 ++++
> >> tests/intel/xe_drm_fdinfo.c | 197
> >> +++++++-----------------------------
> >> 3 files changed, 172 insertions(+), 162 deletions(-)
> >>
> >> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index
> >> 3adacc3a8..b611ac5c1 100644
> >> --- a/lib/xe/xe_spin.c
> >> +++ b/lib/xe/xe_spin.c
> >> @@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
> >> free(spin);
> >> }
> >>
> >> +struct xe_spin_ctx *
> >> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> uint64_t ahnd, uint32_t vm,
> >> + uint16_t width, uint16_t num_placements) {
> >> + struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
> >> +
> >> + igt_assert(width && num_placements &&
> >> + (width == 1 || num_placements == 1));
> >> + igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
>
> I think those asserts are fine for a lib since it would be a programming error.
>
> >> +
> >> + ctx->class = hwe->engine_class;
> >> + ctx->width = width;
> >> + ctx->num_placements = num_placements;
> >> + ctx->vm = vm;
> >> +
> >> + ctx->exec.num_batch_buffer = width;
> >> + ctx->exec.num_syncs = 2;
> >> + ctx->exec.syncs = to_user_pointer(ctx->sync);
> >> +
> >> + ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> + ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> + ctx->sync[0].handle = syncobj_create(fd, 0);
> >> +
> >> + ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> + ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> + ctx->sync[1].handle = syncobj_create(fd, 0);
> >> +
> >> + ctx->bo_size = sizeof(struct xe_spin);
> >> + ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> >> + ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> >> + vram_if_possible(fd, hwe->gt_id),
> >> +
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> >> + if (ahnd) {
>
> we need a better set of functions for handling an optional arg like this.
>
> >> + for (unsigned int i = 0; i < width; i++)
> >> + ctx->addr[i] =
> intel_allocator_alloc_with_strategy(ahnd,
> >> + ctx->bo, ctx->bo_size, 0,
> >> + ALLOC_STRATEGY_LOW_TO_HIGH);
> >> + } else {
> >> + for (unsigned int i = 0; i < width; i++)
> >> + ctx->addr[i] = 0x100000 + 0x100000 * hwe-
> >engine_class;
> >> + }
> >> +
> >> + ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> >> +
> >> + igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width,
> num_placements,
> >> + hwe, 0, &ctx->exec_queue), 0);
>
> this assert should probably be handled as an error, and let the test do the
> assert. This way this can be easily used by others libs and tools. I was chatting
> recently with other people that it'd be good to have a gpu-stress (whatever
> the name, may be xe-spinner if not generalized) so we can easily exercise
> the engines.
>
> >> +
> >> + xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx-
> >bo_size,
> >> + ctx->sync, 1);
> >
> >@Lucas
> >
> >I'm looking here and I've doubts what's going on in 'utilization_multi'
> >subtest where width > 1. I mean we bind only addr[0], but according to
> >exec with width > 1 I assume addr[1] should be bound as well.
>
> we may need to change that to generalize in the lib. In the case of that
> specific test we setup the addr per class:
>
> num_placements = xe_gt_fill_engines_by_class()
> if TEST_PARALLEL {
> width = num_placements
> num_placements = 1
> }
> ...
> for (unsigned int i = 0; i < width; i++)
> ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
>
> So if width > 1, all of them point to the same address.
> To make it generic I think we will have to change that, yes.
>
> +Matt Brost
>
> Lucas De Marchi
>
> >
> >What I'm missing here?
> >
> >--
> >Zbigniew
> >
> >> +
> >> + return ctx;
> >> +}
> >> +
> >> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx) {
> >> + if (!ctx)
> >> + return;
> >> +
> >> + ctx->spin_opts.addr = ctx->addr[0];
> >> + ctx->spin_opts.write_timestamp = true;
> >> + ctx->spin_opts.preempt = true;
> >> + xe_spin_init(ctx->spin, &ctx->spin_opts);
> >> +
> >> + /* re-use sync[0] for exec */
> >> + ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> >> +
> >> + ctx->exec.exec_queue_id = ctx->exec_queue;
> >> +
> >> + if (ctx->width > 1)
> >> + ctx->exec.address = to_user_pointer(ctx->addr);
> >> + else
> >> + ctx->exec.address = ctx->addr[0];
> >> +
> >> + xe_exec(fd, &ctx->exec);
> >> +
> >> + xe_spin_wait_started(ctx->spin);
> >> + igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> >> +
> >> + igt_debug("%d: spinner started\n", ctx->class); }
> >> +
> >> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx) {
> >> + if (!ctx || ctx->ended)
> >> + return;
> >> +
> >> + xe_spin_end(ctx->spin);
> >> +
> >> + igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0,
> NULL));
> >> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> >> +NULL));
> >> +
> >> + ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> >> + xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size,
> ctx->sync, 1);
> >> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> >> +NULL));
> >> +
> >> + ctx->ended = true;
> >> + igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
> >> + ctx->spin->timestamp);
> >> +}
> >> +
> >> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx) {
> >> + if (!ctx)
> >> + return;
> >> +
> >> + syncobj_destroy(fd, ctx->sync[0].handle);
> >> + syncobj_destroy(fd, ctx->sync[1].handle);
> >> + xe_exec_queue_destroy(fd, ctx->exec_queue);
> >> +
> >> + munmap(ctx->spin, ctx->bo_size);
> >> + gem_close(fd, ctx->bo);
> >> +
> >> + free(ctx);
> >> +}
> >> +
> >> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> >> struct xe_cork *cork)
> >> {
> >> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index
> >> d65adb05c..18706dcdf 100644
> >> --- a/lib/xe/xe_spin.h
> >> +++ b/lib/xe/xe_spin.h
> >> @@ -43,9 +43,29 @@ struct xe_spin {
> >> uint32_t timestamp;
> >> };
> >>
> >> +struct xe_spin_ctx {
> >> + uint32_t vm;
> >> + uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> >> + struct drm_xe_sync sync[2];
> >> + struct drm_xe_exec exec;
> >> + uint32_t exec_queue;
> >> + size_t bo_size;
> >> + uint32_t bo;
> >> + struct xe_spin *spin;
> >> + struct xe_spin_opts spin_opts;
> >> + bool ended;
> >> + uint16_t class;
> >> + uint16_t width;
> >> + uint16_t num_placements;
> >> +};
> >> +
> >> igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory
> >> *opt); uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t
> >> ns); void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts
> >> *opts);
> >> +struct xe_spin_ctx *
> >> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> uint64_t ahnd, uint32_t vm,
> >> + uint16_t width, uint16_t num_placements); void
> >> +xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
> >>
> >> #define xe_spin_init_opts(fd, ...) \
> >> xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__})) @@ -55,6
> >> +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin); void
> >> xe_spin_wait_started(struct xe_spin *spin); void xe_spin_end(struct
> >> xe_spin *spin); void xe_spin_free(int fd, struct igt_spin *spin);
> >> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx); void
> >> +xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
> >>
> >> struct xe_cork {
> >> struct xe_spin *spin;
> >> diff --git a/tests/intel/xe_drm_fdinfo.c
> >> b/tests/intel/xe_drm_fdinfo.c index 5fd7c0416..91ff4a5af 100644
> >> --- a/tests/intel/xe_drm_fdinfo.c
> >> +++ b/tests/intel/xe_drm_fdinfo.c
> >> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
> >> igt_require(info.num_engines);
> >> }
> >>
> >> -struct spin_ctx {
> >> - uint32_t vm;
> >> - uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> >> - struct drm_xe_sync sync[2];
> >> - struct drm_xe_exec exec;
> >> - uint32_t exec_queue;
> >> - size_t bo_size;
> >> - uint32_t bo;
> >> - struct xe_spin *spin;
> >> - struct xe_spin_opts spin_opts;
> >> - bool ended;
> >> - uint16_t class;
> >> - uint16_t width;
> >> - uint16_t num_placements;
> >> -};
> >> -
> >> -static struct spin_ctx *
> >> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> uint32_t vm,
> >> - uint16_t width, uint16_t num_placements)
> >> -{
> >> - struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> >> -
> >> - igt_assert(width && num_placements &&
> >> - (width == 1 || num_placements == 1));
> >> - igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> >> -
> >> - ctx->class = hwe->engine_class;
> >> - ctx->width = width;
> >> - ctx->num_placements = num_placements;
> >> - ctx->vm = vm;
> >> -
> >> - for (unsigned int i = 0; i < width; i++)
> >> - ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> >> -
> >> - ctx->exec.num_batch_buffer = width;
> >> - ctx->exec.num_syncs = 2;
> >> - ctx->exec.syncs = to_user_pointer(ctx->sync);
> >> -
> >> - ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> - ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> - ctx->sync[0].handle = syncobj_create(fd, 0);
> >> -
> >> - ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> - ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> - ctx->sync[1].handle = syncobj_create(fd, 0);
> >> -
> >> - ctx->bo_size = sizeof(struct xe_spin);
> >> - ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> >> - ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> >> - vram_if_possible(fd, hwe->gt_id),
> >> -
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> >> - ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> >> -
> >> - igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width,
> num_placements,
> >> - hwe, 0, &ctx->exec_queue), 0);
> >> -
> >> - xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx-
> >bo_size,
> >> - ctx->sync, 1);
> >> -
> >> - return ctx;
> >> -}
> >> -
> >> -static void
> >> -spin_sync_start(int fd, struct spin_ctx *ctx) -{
> >> - if (!ctx)
> >> - return;
> >> -
> >> - ctx->spin_opts.addr = ctx->addr[0];
> >> - ctx->spin_opts.write_timestamp = true;
> >> - ctx->spin_opts.preempt = true;
> >> - xe_spin_init(ctx->spin, &ctx->spin_opts);
> >> -
> >> - /* re-use sync[0] for exec */
> >> - ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> >> -
> >> - ctx->exec.exec_queue_id = ctx->exec_queue;
> >> -
> >> - if (ctx->width > 1)
> >> - ctx->exec.address = to_user_pointer(ctx->addr);
> >> - else
> >> - ctx->exec.address = ctx->addr[0];
> >> -
> >> - xe_exec(fd, &ctx->exec);
> >> -
> >> - xe_spin_wait_started(ctx->spin);
> >> - igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> >> -
> >> - igt_debug("%s: spinner started\n", engine_map[ctx->class]);
> >> -}
> >> -
> >> -static void
> >> -spin_sync_end(int fd, struct spin_ctx *ctx) -{
> >> - if (!ctx || ctx->ended)
> >> - return;
> >> -
> >> - xe_spin_end(ctx->spin);
> >> -
> >> - igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0,
> NULL));
> >> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> NULL));
> >> -
> >> - ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> >> - xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size,
> ctx->sync, 1);
> >> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> NULL));
> >> -
> >> - ctx->ended = true;
> >> - igt_debug("%s: spinner ended (timestamp=%u)\n",
> engine_map[ctx->class],
> >> - ctx->spin->timestamp);
> >> -}
> >> -
> >> -static void
> >> -spin_ctx_destroy(int fd, struct spin_ctx *ctx) -{
> >> - if (!ctx)
> >> - return;
> >> -
> >> - syncobj_destroy(fd, ctx->sync[0].handle);
> >> - syncobj_destroy(fd, ctx->sync[1].handle);
> >> - xe_exec_queue_destroy(fd, ctx->exec_queue);
> >> -
> >> - munmap(ctx->spin, ctx->bo_size);
> >> - gem_close(fd, ctx->bo);
> >> -
> >> - free(ctx);
> >> -}
> >> -
> >> static void
> >> check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> >> int class, int width, enum expected_load expected_load) @@
> >> -535,7 +408,7 @@ utilization_single(int fd, struct
> >> drm_xe_engine_class_instance *hwe, unsigned in {
> >> struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE +
> 1];
> >> struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE +
> 1];
> >> - struct spin_ctx *ctx = NULL;
> >> + struct xe_spin_ctx *ctx = NULL;
> >> enum expected_load expected_load;
> >> uint32_t vm;
> >> int new_fd;
> >> @@ -545,8 +418,8 @@ utilization_single(int fd, struct
> >> drm_xe_engine_class_instance *hwe, unsigned in
> >>
> >> vm = xe_vm_create(fd, 0, 0);
> >> if (flags & TEST_BUSY) {
> >> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> - spin_sync_start(fd, ctx);
> >> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> + xe_spin_sync_start(fd, ctx);
> >> }
> >>
> >> read_engine_cycles(fd, pceu1[0]);
> >> @@ -555,7 +428,7 @@ utilization_single(int fd, struct
> >> drm_xe_engine_class_instance *hwe, unsigned in
> >>
> >> usleep(batch_duration_usec);
> >> if (flags & TEST_TRAILING_IDLE)
> >> - spin_sync_end(fd, ctx);
> >> + xe_spin_sync_end(fd, ctx);
> >>
> >> read_engine_cycles(fd, pceu2[0]);
> >> if (flags & TEST_ISOLATION)
> >> @@ -574,8 +447,8 @@ utilization_single(int fd, struct
> drm_xe_engine_class_instance *hwe, unsigned in
> >> close(new_fd);
> >> }
> >>
> >> - spin_sync_end(fd, ctx);
> >> - spin_ctx_destroy(fd, ctx);
> >> + xe_spin_sync_end(fd, ctx);
> >> + xe_spin_ctx_destroy(fd, ctx);
> >> xe_vm_destroy(fd, vm);
> >> }
> >>
> >> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct
> >> drm_xe_engine_class_instance *hw {
> >> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> - struct spin_ctx *ctx = NULL;
> >> + struct xe_spin_ctx *ctx = NULL;
> >> uint32_t vm;
> >>
> >> vm = xe_vm_create(fd, 0, 0);
> >> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> - spin_sync_start(fd, ctx);
> >> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> + xe_spin_sync_start(fd, ctx);
> >>
> >> read_engine_cycles(fd, pceu1);
> >> usleep(batch_duration_usec);
> >>
> >> /* destroy queue before sampling again */
> >> - spin_sync_end(fd, ctx);
> >> - spin_ctx_destroy(fd, ctx);
> >> + xe_spin_sync_end(fd, ctx);
> >> + xe_spin_ctx_destroy(fd, ctx);
> >>
> >> read_engine_cycles(fd, pceu2);
> >>
> >> @@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct
> >> drm_xe_engine_class_instance *hwe) {
> >> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> - struct spin_ctx *ctx = NULL;
> >> + struct xe_spin_ctx *ctx = NULL;
> >> uint32_t vm;
> >> int class;
> >>
> >> vm = xe_vm_create(fd, 0, 0);
> >>
> >> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> - spin_sync_start(fd, ctx);
> >> + ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> + xe_spin_sync_start(fd, ctx);
> >>
> >> read_engine_cycles(fd, pceu1);
> >> usleep(batch_duration_usec);
> >> - spin_sync_end(fd, ctx);
> >> + xe_spin_sync_end(fd, ctx);
> >> read_engine_cycles(fd, pceu2);
> >>
> >> xe_for_each_engine_class(class) {
> >> @@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct
> drm_xe_engine_class_instance *hwe)
> >> check_results(pceu1, pceu2, class, 1, expected_load);
> >> }
> >>
> >> - spin_sync_end(fd, ctx);
> >> - spin_ctx_destroy(fd, ctx);
> >> + xe_spin_sync_end(fd, ctx);
> >> + xe_spin_ctx_destroy(fd, ctx);
> >> xe_vm_destroy(fd, vm);
> >> }
> >>
> >> @@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct
> >> drm_xe_engine_class_instance *hwe) {
> >> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> >> + struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] =
> {};
> >> struct drm_xe_engine_class_instance *_hwe;
> >> uint32_t vm;
> >> int class;
> >> @@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct
> drm_xe_engine_class_instance *hwe)
> >> if (_class == hwe->engine_class || ctx[_class])
> >> continue;
> >>
> >> - ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> >> - spin_sync_start(fd, ctx[_class]);
> >> + ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
> >> + xe_spin_sync_start(fd, ctx[_class]);
> >> }
> >>
> >> read_engine_cycles(fd, pceu1);
> >> usleep(batch_duration_usec);
> >> xe_for_each_engine_class(class)
> >> - spin_sync_end(fd, ctx[class]);
> >> + xe_spin_sync_end(fd, ctx[class]);
> >> read_engine_cycles(fd, pceu2);
> >>
> >> xe_for_each_engine_class(class) {
> >> @@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct
> drm_xe_engine_class_instance *hwe)
> >> continue;
> >>
> >> check_results(pceu1, pceu2, class, 1, expected_load);
> >> - spin_sync_end(fd, ctx[class]);
> >> - spin_ctx_destroy(fd, ctx[class]);
> >> + xe_spin_sync_end(fd, ctx[class]);
> >> + xe_spin_ctx_destroy(fd, ctx[class]);
> >> }
> >>
> >> xe_vm_destroy(fd, vm);
> >> @@ -685,7 +558,7 @@ utilization_all_full_load(int fd) {
> >> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> >> + struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] =
> {};
> >> struct drm_xe_engine_class_instance *hwe;
> >> uint32_t vm;
> >> int class;
> >> @@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
> >> if (ctx[class])
> >> continue;
> >>
> >> - ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> - spin_sync_start(fd, ctx[class]);
> >> + ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> + xe_spin_sync_start(fd, ctx[class]);
> >> }
> >>
> >> read_engine_cycles(fd, pceu1);
> >> usleep(batch_duration_usec);
> >> xe_for_each_engine_class(class)
> >> - spin_sync_end(fd, ctx[class]);
> >> + xe_spin_sync_end(fd, ctx[class]);
> >> read_engine_cycles(fd, pceu2);
> >>
> >> xe_for_each_engine_class(class) {
> >> @@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
> >> continue;
> >>
> >> check_results(pceu1, pceu2, class, 1,
> EXPECTED_LOAD_FULL);
> >> - spin_sync_end(fd, ctx[class]);
> >> - spin_ctx_destroy(fd, ctx[class]);
> >> + xe_spin_sync_end(fd, ctx[class]);
> >> + xe_spin_ctx_destroy(fd, ctx[class]);
> >> }
> >>
> >> xe_vm_destroy(fd, vm);
> >> @@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int
> flags)
> >> struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> struct pceu_cycles
> pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> struct drm_xe_engine_class_instance
> eci[XE_MAX_ENGINE_INSTANCE];
> >> - struct spin_ctx *ctx = NULL;
> >> + struct xe_spin_ctx *ctx = NULL;
> >> enum expected_load expected_load;
> >> int fd_spill, num_placements;
> >> uint32_t vm;
> >> @@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class,
> >> unsigned int flags)
> >>
> >> vm = xe_vm_create(fd, 0, 0);
> >> if (flags & TEST_BUSY) {
> >> - ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> >> - spin_sync_start(fd, ctx);
> >> + ctx = xe_spin_ctx_init(fd, eci, 0, vm, width,
> num_placements);
> >> + xe_spin_sync_start(fd, ctx);
> >> }
> >>
> >> read_engine_cycles(fd, pceu[0]);
> >> @@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class,
> >> unsigned int flags)
> >>
> >> usleep(batch_duration_usec);
> >> if (flags & TEST_TRAILING_IDLE)
> >> - spin_sync_end(fd, ctx);
> >> + xe_spin_sync_end(fd, ctx);
> >>
> >> read_engine_cycles(fd, pceu[1]);
> >> if (flags & TEST_ISOLATION)
> >> @@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int
> flags)
> >> close(fd_spill);
> >> }
> >>
> >> - spin_sync_end(fd, ctx);
> >> - spin_ctx_destroy(fd, ctx);
> >> + xe_spin_sync_end(fd, ctx);
> >> + xe_spin_ctx_destroy(fd, ctx);
> >>
> >> xe_vm_destroy(fd, vm);
> >> }
> >> --
> >> 2.34.1
> >>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-13 16:13 ` Gurram, Pravalika
@ 2024-11-13 16:57 ` Lucas De Marchi
0 siblings, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2024-11-13 16:57 UTC (permalink / raw)
To: Gurram, Pravalika
Cc: Kempczynski, Zbigniew, igt-dev@lists.freedesktop.org,
Brost, Matthew
On Wed, Nov 13, 2024 at 10:13:06AM -0600, Gurram, Pravalika wrote:
>
>
>> -----Original Message-----
>> From: De Marchi, Lucas <lucas.demarchi@intel.com>
>> Sent: Friday, November 8, 2024 9:09 PM
>> To: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
>> Cc: Gurram, Pravalika <pravalika.gurram@intel.com>; igt-
>> dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
>> Subject: Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions
>> to lib
>>
>> On Fri, Nov 08, 2024 at 10:01:41AM +0100, Zbigniew Kempczyński wrote:
>> >+Lucas
>>
>> Pravalika, please keep me in Cc. I don't watch the igt mailing list close
>> enough, particularly when it's a follow up to a suggestion I gave.
>>
>> >
>> >On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
>> >> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
>> >> to xe spin lib to avoid code redundancy.
>> >>
>> >> v2: use allocator based on developer preference.
>> >> change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
>>
>> but we already have another thing named ctx there, the rename doesn't
>> improve it.
>>
>> From lib/xe/xe_spin.h, what should be added on is
>>
>> struct xe_cork {
>> struct xe_spin *spin;
>> int fd;
>> uint32_t vm;
>> uint32_t bo;
>> uint32_t exec_queue;
>> uint32_t syncobj;
>> };
>>
>> I don't really like that name, but we can do a rename on top... or we can
>> rename it now and then move things.
>>
>
>could you please suggest the name in place of xe_cork
not sure... I think we can probably have:
Current alternative1 alternative2 alternative3
xe_spin xe_spin_bo xe_spin xe_spin
xe_cork xe_spinner xe_spin_ctx xe_spinner
Or keep as is and let the rename to be done when everything is added. As
the original author of xe_cork, I'd wait on Matt Brost about a rename.
Lucas De Marchi
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check
@ 2024-11-13 17:52 Pravalika Gurram
2024-11-13 17:52 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Pravalika Gurram @ 2024-11-13 17:52 UTC (permalink / raw)
To: lucas.demarchi, igt-dev; +Cc: Pravalika Gurram
move the spinner related functions to lib
check the ctx_timestamp register post gt reset for each engine.
Pravalika Gurram (2):
lib/xe/xe_spin: move the spinner related functions to lib
tests/xe_spin_batch: Add spin-timestamp-check
lib/xe/xe_spin.c | 116 +++++++++++++++++++++
lib/xe/xe_spin.h | 40 ++++++--
tests/intel/xe_drm_fdinfo.c | 200 +++++++-----------------------------
tests/intel/xe_spin_batch.c | 121 ++++++++++++++++++++++
4 files changed, 304 insertions(+), 173 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
@ 2024-11-13 17:52 ` Pravalika Gurram
2024-11-28 8:24 ` Peter Senna Tschudin
2024-12-04 9:09 ` Zbigniew Kempczyński
2024-11-13 17:52 ` [PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
` (5 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Pravalika Gurram @ 2024-11-13 17:52 UTC (permalink / raw)
To: lucas.demarchi, igt-dev; +Cc: Pravalika Gurram
move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
to xe spin lib to avoid code redundancy.
v2: use allocator based on developer preference.
change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
v3: Integrate spin_ctx to xe_cork
use designated structure initialization for optional arg [Lucas]
Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
---
lib/xe/xe_spin.c | 116 +++++++++++++++++++++
lib/xe/xe_spin.h | 40 ++++++--
tests/intel/xe_drm_fdinfo.c | 200 +++++++-----------------------------
3 files changed, 183 insertions(+), 173 deletions(-)
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 3adacc3a8..41679d9c6 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -292,6 +292,122 @@ void xe_spin_free(int fd, struct igt_spin *spin)
free(spin);
}
+struct xe_cork *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
+ uint32_t vm, uint16_t width, uint16_t num_placements,
+ struct xe_cork_opts *opts)
+{
+ struct xe_cork *ctx = calloc(1, sizeof(*ctx));
+
+ igt_assert(width && num_placements &&
+ (width == 1 || num_placements == 1));
+ igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
+
+ ctx->class = hwe->engine_class;
+ ctx->width = width;
+ ctx->num_placements = num_placements;
+ ctx->vm = vm;
+
+ ctx->exec.num_batch_buffer = width;
+ ctx->exec.num_syncs = 2;
+ ctx->exec.syncs = to_user_pointer(ctx->sync);
+
+ ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+ ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+ ctx->sync[0].handle = syncobj_create(fd, 0);
+
+ ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+ ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+ ctx->sync[1].handle = syncobj_create(fd, 0);
+
+ ctx->bo_size = sizeof(struct xe_spin);
+ ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
+ ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
+ vram_if_possible(fd, hwe->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ if (opts->ahnd) {
+ for (unsigned int i = 0; i < width; i++)
+ ctx->addr[i] = intel_allocator_alloc_with_strategy(opts->ahnd,
+ ctx->bo, ctx->bo_size, 0,
+ ALLOC_STRATEGY_LOW_TO_HIGH);
+ } else {
+ for (unsigned int i = 0; i < width; i++)
+ ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
+ }
+
+ ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
+
+ igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
+ hwe, 0, &ctx->exec_queue), 0);
+
+ xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
+ ctx->sync, 1);
+
+ return ctx;
+}
+
+void xe_spin_sync_start(int fd, struct xe_cork *ctx)
+{
+ if (!ctx)
+ return;
+
+ ctx->spin_opts.addr = ctx->addr[0];
+ ctx->spin_opts.write_timestamp = true;
+ ctx->spin_opts.preempt = true;
+ xe_spin_init(ctx->spin, &ctx->spin_opts);
+
+ /* re-use sync[0] for exec */
+ ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+
+ ctx->exec.exec_queue_id = ctx->exec_queue;
+
+ if (ctx->width > 1)
+ ctx->exec.address = to_user_pointer(ctx->addr);
+ else
+ ctx->exec.address = ctx->addr[0];
+
+ xe_exec(fd, &ctx->exec);
+
+ xe_spin_wait_started(ctx->spin);
+ igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
+
+ igt_debug("%d: spinner started\n", ctx->class);
+}
+
+void xe_spin_sync_end(int fd, struct xe_cork *ctx)
+{
+ if (!ctx || ctx->ended)
+ return;
+
+ xe_spin_end(ctx->spin);
+
+ igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
+ igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
+ igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ ctx->ended = true;
+ igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
+ ctx->spin->timestamp);
+}
+
+void xe_spin_ctx_destroy(int fd, struct xe_cork *ctx)
+{
+ if (!ctx)
+ return;
+
+ syncobj_destroy(fd, ctx->sync[0].handle);
+ syncobj_destroy(fd, ctx->sync[1].handle);
+ xe_exec_queue_destroy(fd, ctx->exec_queue);
+
+ munmap(ctx->spin, ctx->bo_size);
+ gem_close(fd, ctx->bo);
+
+ free(ctx);
+}
+
void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
struct xe_cork *cork)
{
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index d65adb05c..21488b071 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -32,6 +32,10 @@ struct xe_spin_opts {
bool write_timestamp;
};
+struct xe_cork_opts {
+ uint64_t ahnd;
+};
+
/* Mapped GPU object */
struct xe_spin {
uint32_t batch[128];
@@ -43,9 +47,35 @@ struct xe_spin {
uint32_t timestamp;
};
+struct xe_cork {
+ struct xe_spin *spin;
+ int fd;
+ uint32_t vm;
+ uint32_t bo;
+ uint32_t exec_queue;
+ uint32_t syncobj;
+ uint64_t addr[XE_MAX_ENGINE_INSTANCE];
+ struct drm_xe_sync sync[2];
+ struct drm_xe_exec exec;
+ size_t bo_size;
+ struct xe_spin_opts spin_opts;
+ bool ended;
+ uint16_t class;
+ uint16_t width;
+ uint16_t num_placements;
+};
+
igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
+struct xe_cork *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
+ uint16_t width, uint16_t num_placements, struct xe_cork_opts *opts);
+void xe_spin_ctx_destroy(int fd, struct xe_cork *ctx);
+
+#define xe_spin_ctx_init_opts(fd, hwe, vm, width, num_placements, ...) \
+ xe_spin_ctx_init(fd, hwe, vm, width, num_placements, \
+ &((struct xe_cork_opts){__VA_ARGS__}))
#define xe_spin_init_opts(fd, ...) \
xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
@@ -55,15 +85,9 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
void xe_spin_wait_started(struct xe_spin *spin);
void xe_spin_end(struct xe_spin *spin);
void xe_spin_free(int fd, struct igt_spin *spin);
+void xe_spin_sync_start(int fd, struct xe_cork *ctx);
+void xe_spin_sync_end(int fd, struct xe_cork *ctx);
-struct xe_cork {
- struct xe_spin *spin;
- int fd;
- uint32_t vm;
- uint32_t bo;
- uint32_t exec_queue;
- uint32_t syncobj;
-};
void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
struct xe_cork *cork);
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 5fd7c0416..d7d392000 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
igt_require(info.num_engines);
}
-struct spin_ctx {
- uint32_t vm;
- uint64_t addr[XE_MAX_ENGINE_INSTANCE];
- struct drm_xe_sync sync[2];
- struct drm_xe_exec exec;
- uint32_t exec_queue;
- size_t bo_size;
- uint32_t bo;
- struct xe_spin *spin;
- struct xe_spin_opts spin_opts;
- bool ended;
- uint16_t class;
- uint16_t width;
- uint16_t num_placements;
-};
-
-static struct spin_ctx *
-spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
- uint16_t width, uint16_t num_placements)
-{
- struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
-
- igt_assert(width && num_placements &&
- (width == 1 || num_placements == 1));
- igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
-
- ctx->class = hwe->engine_class;
- ctx->width = width;
- ctx->num_placements = num_placements;
- ctx->vm = vm;
-
- for (unsigned int i = 0; i < width; i++)
- ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
-
- ctx->exec.num_batch_buffer = width;
- ctx->exec.num_syncs = 2;
- ctx->exec.syncs = to_user_pointer(ctx->sync);
-
- ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
- ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
- ctx->sync[0].handle = syncobj_create(fd, 0);
-
- ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
- ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
- ctx->sync[1].handle = syncobj_create(fd, 0);
-
- ctx->bo_size = sizeof(struct xe_spin);
- ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
- ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
- vram_if_possible(fd, hwe->gt_id),
- DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
- ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
-
- igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
- hwe, 0, &ctx->exec_queue), 0);
-
- xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
- ctx->sync, 1);
-
- return ctx;
-}
-
-static void
-spin_sync_start(int fd, struct spin_ctx *ctx)
-{
- if (!ctx)
- return;
-
- ctx->spin_opts.addr = ctx->addr[0];
- ctx->spin_opts.write_timestamp = true;
- ctx->spin_opts.preempt = true;
- xe_spin_init(ctx->spin, &ctx->spin_opts);
-
- /* re-use sync[0] for exec */
- ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
-
- ctx->exec.exec_queue_id = ctx->exec_queue;
-
- if (ctx->width > 1)
- ctx->exec.address = to_user_pointer(ctx->addr);
- else
- ctx->exec.address = ctx->addr[0];
-
- xe_exec(fd, &ctx->exec);
-
- xe_spin_wait_started(ctx->spin);
- igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
-
- igt_debug("%s: spinner started\n", engine_map[ctx->class]);
-}
-
-static void
-spin_sync_end(int fd, struct spin_ctx *ctx)
-{
- if (!ctx || ctx->ended)
- return;
-
- xe_spin_end(ctx->spin);
-
- igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
- igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
- ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
- xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
- igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
- ctx->ended = true;
- igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
- ctx->spin->timestamp);
-}
-
-static void
-spin_ctx_destroy(int fd, struct spin_ctx *ctx)
-{
- if (!ctx)
- return;
-
- syncobj_destroy(fd, ctx->sync[0].handle);
- syncobj_destroy(fd, ctx->sync[1].handle);
- xe_exec_queue_destroy(fd, ctx->exec_queue);
-
- munmap(ctx->spin, ctx->bo_size);
- gem_close(fd, ctx->bo);
-
- free(ctx);
-}
-
static void
check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
int class, int width, enum expected_load expected_load)
@@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
{
struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx = NULL;
+ struct xe_cork *ctx = NULL;
enum expected_load expected_load;
uint32_t vm;
int new_fd;
@@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
vm = xe_vm_create(fd, 0, 0);
if (flags & TEST_BUSY) {
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
}
read_engine_cycles(fd, pceu1[0]);
@@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
usleep(batch_duration_usec);
if (flags & TEST_TRAILING_IDLE)
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu2[0]);
if (flags & TEST_ISOLATION)
@@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
close(new_fd);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
@@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx = NULL;
+ struct xe_cork *ctx = NULL;
uint32_t vm;
vm = xe_vm_create(fd, 0, 0);
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
/* destroy queue before sampling again */
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
read_engine_cycles(fd, pceu2);
@@ -610,18 +483,17 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx = NULL;
+ struct xe_cork *ctx = NULL;
uint32_t vm;
int class;
vm = xe_vm_create(fd, 0, 0);
-
- ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx);
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -631,8 +503,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
check_results(pceu1, pceu2, class, 1, expected_load);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
@@ -641,7 +513,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+ struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
struct drm_xe_engine_class_instance *_hwe;
uint32_t vm;
int class;
@@ -654,15 +526,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
if (_class == hwe->engine_class || ctx[_class])
continue;
-
- ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
- spin_sync_start(fd, ctx[_class]);
+ ctx[_class] = xe_spin_ctx_init_opts(fd, _hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx[_class]);
}
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
xe_for_each_engine_class(class)
- spin_sync_end(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -673,8 +544,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
continue;
check_results(pceu1, pceu2, class, 1, expected_load);
- spin_sync_end(fd, ctx[class]);
- spin_ctx_destroy(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
+ xe_spin_ctx_destroy(fd, ctx[class]);
}
xe_vm_destroy(fd, vm);
@@ -685,7 +556,7 @@ utilization_all_full_load(int fd)
{
struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
- struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+ struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
struct drm_xe_engine_class_instance *hwe;
uint32_t vm;
int class;
@@ -697,15 +568,14 @@ utilization_all_full_load(int fd)
class = hwe->engine_class;
if (ctx[class])
continue;
-
- ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
- spin_sync_start(fd, ctx[class]);
+ ctx[class] = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
+ xe_spin_sync_start(fd, ctx[class]);
}
read_engine_cycles(fd, pceu1);
usleep(batch_duration_usec);
xe_for_each_engine_class(class)
- spin_sync_end(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
read_engine_cycles(fd, pceu2);
xe_for_each_engine_class(class) {
@@ -713,8 +583,8 @@ utilization_all_full_load(int fd)
continue;
check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
- spin_sync_end(fd, ctx[class]);
- spin_ctx_destroy(fd, ctx[class]);
+ xe_spin_sync_end(fd, ctx[class]);
+ xe_spin_ctx_destroy(fd, ctx[class]);
}
xe_vm_destroy(fd, vm);
@@ -741,7 +611,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
- struct spin_ctx *ctx = NULL;
+ struct xe_cork *ctx = NULL;
enum expected_load expected_load;
int fd_spill, num_placements;
uint32_t vm;
@@ -767,8 +637,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
vm = xe_vm_create(fd, 0, 0);
if (flags & TEST_BUSY) {
- ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
- spin_sync_start(fd, ctx);
+ ctx = xe_spin_ctx_init_opts(fd, eci, vm, width, num_placements);
+ xe_spin_sync_start(fd, ctx);
}
read_engine_cycles(fd, pceu[0]);
@@ -777,7 +647,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
usleep(batch_duration_usec);
if (flags & TEST_TRAILING_IDLE)
- spin_sync_end(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
read_engine_cycles(fd, pceu[1]);
if (flags & TEST_ISOLATION)
@@ -797,8 +667,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
close(fd_spill);
}
- spin_sync_end(fd, ctx);
- spin_ctx_destroy(fd, ctx);
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
xe_vm_destroy(fd, vm);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check
2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
2024-11-13 17:52 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
@ 2024-11-13 17:52 ` Pravalika Gurram
2024-11-28 8:26 ` Peter Senna Tschudin
2024-11-13 20:07 ` ✓ Fi.CI.BAT: success for tests/xe_spin_batch: Add spin-timestamp-check (rev4) Patchwork
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Pravalika Gurram @ 2024-11-13 17:52 UTC (permalink / raw)
To: lucas.demarchi, igt-dev; +Cc: Pravalika Gurram, Zbigniew Kempczyński
check the ctx_timestamp register post gt reset for each engine.
V2: move spinner code to lib avoid code redundancy
use flags to maintain the readability
use READ_ONCE to prevent compiler from optimizing it out [Lucas]
V3: call allocator in run_spinner and pass to spinner ctx [Zbigniew]
v4: Integrate spin_ctx to xe_cork [Lucas]
Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/intel/xe_spin_batch.c | 121 ++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 9314e229e..9a5cdb830 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -309,6 +309,121 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
put_ahnd(ahnd);
}
+static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
+ bool hang)
+{
+ uint64_t ahnd, bb_size, bb_addr;
+ uint32_t vm, exec_queue, bb;
+#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
+ struct drm_xe_sync syncobj = {
+ .type = DRM_XE_SYNC_TYPE_USER_FENCE,
+ .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+ .timeline_value = USER_FENCE_VALUE,
+ };
+
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 1,
+ .syncs = to_user_pointer(&syncobj),
+ };
+ struct {
+ uint32_t batch[16];
+ uint64_t pad;
+ uint32_t data;
+ uint64_t vm_sync;
+ uint64_t exec_sync;
+ } *data;
+ uint64_t batch_offset, batch_addr, sdi_offset, sdi_addr;
+ int64_t timeout = NSEC_PER_SEC;
+ int i, ret;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ vm = xe_vm_create(fd, 0, 0);
+ exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
+ bb_size = xe_bb_size(fd, sizeof(*data));
+ bb = xe_bo_create(fd, vm, bb_size, vram_if_possible(fd, eci->gt_id), 0);
+ bb_addr = intel_allocator_alloc_with_strategy(ahnd, bb, bb_size, 0,
+ ALLOC_STRATEGY_LOW_TO_HIGH);
+ data = xe_bo_map(fd, bb, bb_size);
+ syncobj.addr = to_user_pointer(&data->vm_sync);
+ xe_vm_bind_async(fd, vm, 0, bb, 0, bb_addr, bb_size, &syncobj, 1);
+ xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
+
+ batch_offset = (char *)&data->batch - (char *)data;
+ batch_addr = bb_addr + batch_offset;
+ sdi_offset = (char *)&data->data - (char *)data;
+ sdi_addr = bb_addr + sdi_offset;
+
+ i = 0;
+
+ data->batch[i++] = MI_STORE_DWORD_IMM_GEN4;
+ data->batch[i++] = sdi_addr;
+ data->batch[i++] = sdi_addr >> 32;
+ data->batch[i++] = 0;
+ if (!hang)
+ data->batch[i++] = MI_BATCH_BUFFER_END;
+ igt_assert(i <= ARRAY_SIZE(data->batch));
+
+ syncobj.addr = bb_addr + (char *)&data->exec_sync - (char *)data;
+ exec.exec_queue_id = exec_queue;
+ exec.address = batch_addr;
+ xe_exec(fd, &exec);
+ ret = __xe_wait_ufence(fd, &data->exec_sync, USER_FENCE_VALUE, 0, &timeout);
+ igt_assert(hang ? ret < 0 : ret == 0);
+
+ munmap(data, bb_size);
+ gem_close(fd, bb);
+
+ xe_exec_queue_destroy(fd, exec_queue);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
+{
+ struct xe_cork *ctx = NULL;
+ uint32_t vm;
+ uint32_t ts_1, ts_2;
+ uint64_t ahnd;
+
+ vm = xe_vm_create(fd, 0, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ ctx = xe_spin_ctx_init_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
+ xe_spin_sync_start(fd, ctx);
+
+ /* Collect and check timestamps before stopping the spinner */
+ usleep(50000);
+ ts_1 = READ_ONCE(ctx->spin->timestamp);
+ usleep(50000);
+ ts_2 = READ_ONCE(ctx->spin->timestamp);
+ igt_assert_neq_u32(ts_1, ts_2);
+
+ xe_spin_sync_end(fd, ctx);
+ xe_spin_ctx_destroy(fd, ctx);
+
+ xe_vm_destroy(fd, vm);
+ put_ahnd(ahnd);
+}
+
+#define TRUE 1
+#define FALSE 0
+/**
+ * SUBTEST: spin-timestamp-check
+ * Description: Intiate gt reset then check the timestamp register for each engine.
+ * Test category: functionality test
+ */
+static void xe_spin_timestamp_check(int fd, struct drm_xe_engine_class_instance *eci)
+{
+ /*sanity check for exec submission*/
+ exec_store(fd, eci, FALSE);
+
+ exec_store(fd, eci, TRUE);
+
+ run_spinner(fd, eci);
+}
+
igt_main
{
struct drm_xe_engine_class_instance *hwe;
@@ -343,6 +458,12 @@ igt_main
xe_for_each_engine_class(class)
xe_spin_fixed_duration(fd, gt, class, SPIN_FIX_DURATION_PREEMPT);
+ igt_subtest_with_dynamic("spin-timestamp-check")
+ xe_for_each_engine(fd, hwe) {
+ igt_dynamic_f("engine-%s", xe_engine_class_string(hwe->engine_class))
+ xe_spin_timestamp_check(fd, hwe);
+ }
+
igt_fixture
drm_close_driver(fd);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for tests/xe_spin_batch: Add spin-timestamp-check (rev4)
2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
2024-11-13 17:52 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
2024-11-13 17:52 ` [PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
@ 2024-11-13 20:07 ` Patchwork
2024-11-13 20:08 ` ✓ CI.xeBAT: " Patchwork
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-11-13 20:07 UTC (permalink / raw)
To: Pravalika Gurram; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3216 bytes --]
== Series Details ==
Series: tests/xe_spin_batch: Add spin-timestamp-check (rev4)
URL : https://patchwork.freedesktop.org/series/140933/
State : success
== Summary ==
CI Bug Log - changes from IGT_8107 -> IGTPW_12095
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/index.html
Participating hosts (47 -> 44)
------------------------------
Missing (3): bat-mtlp-9 bat-arls-5 fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_12095 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live:
- bat-mtlp-8: [PASS][1] -> [ABORT][2] ([i915#12061]) +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8107/bat-mtlp-8/igt@i915_selftest@live.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/bat-mtlp-8/igt@i915_selftest@live.html
- bat-arlh-3: [PASS][3] -> [ABORT][4] ([i915#10341])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8107/bat-arlh-3/igt@i915_selftest@live.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/bat-arlh-3/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [PASS][5] -> [ABORT][6] ([i915#12061])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8107/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/bat-arlh-3/igt@i915_selftest@live@workarounds.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-dg2-8: [DMESG-FAIL][7] ([i915#12759]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8107/bat-dg2-8/igt@i915_selftest@live.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/bat-dg2-8/igt@i915_selftest@live.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-8: [DMESG-FAIL][9] ([i915#9500]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8107/bat-dg2-8/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/bat-dg2-8/igt@i915_selftest@live@hangcheck.html
[i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12759]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12759
[i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_8107 -> IGTPW_12095
* Linux: CI_DRM_15689 -> CI_DRM_15690
CI-20190529: 20190529
CI_DRM_15689: 169c7cd31a373ed31054abb423981856eb5fb119 @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_15690: 9e35defd02728ad7c06347830022506488668c21 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_12095: bc97f1ed54b4c60b1681c0f5e02ca07f9cfba1cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8107: 0362b0deec80daaecdfa3dd0676dcabb6f14bd9c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/index.html
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^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ CI.xeBAT: success for tests/xe_spin_batch: Add spin-timestamp-check (rev4)
2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
` (2 preceding siblings ...)
2024-11-13 20:07 ` ✓ Fi.CI.BAT: success for tests/xe_spin_batch: Add spin-timestamp-check (rev4) Patchwork
@ 2024-11-13 20:08 ` Patchwork
2024-11-13 20:18 ` ✗ GitLab.Pipeline: warning " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-11-13 20:08 UTC (permalink / raw)
To: Pravalika Gurram; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1689 bytes --]
== Series Details ==
Series: tests/xe_spin_batch: Add spin-timestamp-check (rev4)
URL : https://patchwork.freedesktop.org/series/140933/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_8107_BAT -> XEIGTPW_12095_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_12095_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- bat-adlp-7: [PASS][1] -> [FAIL][2] ([Intel XE#1861])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
[Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861
Build changes
-------------
* IGT: IGT_8107 -> IGTPW_12095
* Linux: xe-2221-169c7cd31a373ed31054abb423981856eb5fb119 -> xe-2222-9e35defd02728ad7c06347830022506488668c21
IGTPW_12095: bc97f1ed54b4c60b1681c0f5e02ca07f9cfba1cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8107: 0362b0deec80daaecdfa3dd0676dcabb6f14bd9c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2221-169c7cd31a373ed31054abb423981856eb5fb119: 169c7cd31a373ed31054abb423981856eb5fb119
xe-2222-9e35defd02728ad7c06347830022506488668c21: 9e35defd02728ad7c06347830022506488668c21
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/index.html
[-- Attachment #2: Type: text/html, Size: 2265 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ GitLab.Pipeline: warning for tests/xe_spin_batch: Add spin-timestamp-check (rev4)
2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
` (3 preceding siblings ...)
2024-11-13 20:08 ` ✓ CI.xeBAT: " Patchwork
@ 2024-11-13 20:18 ` Patchwork
2024-11-13 23:33 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-11-14 6:49 ` ✗ CI.xeFULL: " Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-11-13 20:18 UTC (permalink / raw)
To: Pravalika Gurram; +Cc: igt-dev
== Series Details ==
Series: tests/xe_spin_batch: Add spin-timestamp-check (rev4)
URL : https://patchwork.freedesktop.org/series/140933/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/1309803 for the overview.
build:tests-debian-meson-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/66556590):
$ /host/bin/curl -s -L --cacert /host/ca-certificates.crt --retry 4 -f --retry-delay 60 https://gitlab.freedesktop.org/freedesktop/helm-gitlab-infra/-/raw/main/runner-gating/runner-gating.sh | sh -s -- pre_get_sources_script
Checking if the user of the pipeline is allowed...
Checking if the job's project is part of a well-known group...
Thank you for contributing to freedesktop.org
Fetching changes...
Reinitialized existing Git repository in /builds/gfx-ci/igt-ci-tags/.git/
Checking out bc97f1ed as detached HEAD (ref is intel/IGTPW_12095)...
Removing build/
Removing scripts/__pycache__/
Skipping Git submodules setup
section_end:1731528846:get_sources
section_start:1731528846:step_script
Executing "step_script" stage of the job script
Using docker image sha256:7360075a71dacfc66f0b49b3271b9a459904dbe51c5760efac48fe52da27946c for registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-arm64:commit-bc97f1ed54b4c60b1681c0f5e02ca07f9cfba1cf with digest registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-arm64@sha256:df8438cd0e218646c3bdc2eb6abccb43c4e884bfd40a1a4dd0365f1f8031d21f ...
section_end:1731528861:step_script
section_start:1731528861:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1731528862:cleanup_file_variables
ERROR: Job failed (system failure): Error response from daemon: no such image: docker.io/library/sha256:7360075a71dacfc66f0b49b3271b9a459904dbe51c5760efac48fe52da27946c: image not known (docker.go:650:0s)
build:tests-debian-meson-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/66556589):
Checking if the job's project is part of a well-known group...
Thank you for contributing to freedesktop.org
Fetching changes...
Reinitialized existing Git repository in /builds/gfx-ci/igt-ci-tags/.git/
Checking out bc97f1ed as detached HEAD (ref is intel/IGTPW_12095)...
Removing build/
Removing lib/i915/perf-configs/__pycache__/
Removing lib/xe/oa-configs/__pycache__/
Removing scripts/__pycache__/
Skipping Git submodules setup
section_end:1731528838:get_sources
section_start:1731528838:step_script
Executing "step_script" stage of the job script
Using docker image sha256:4a4103f1a476d355d866b481ff96ac05a32a3a715cefcc1cbc1356a8959fb5f8 for registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-armhf:commit-bc97f1ed54b4c60b1681c0f5e02ca07f9cfba1cf with digest registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-armhf@sha256:3a0ffeb305cdc6ef081dde81d86afee76102e74f76c0f7bd5685fc2457ec707b ...
section_end:1731528847:step_script
section_start:1731528847:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1731528861:cleanup_file_variables
ERROR: Job failed (system failure): Error response from daemon: container create: creating container storage: parsing named reference "4a4103f1a476d355d866b481ff96ac05a32a3a715cefcc1cbc1356a8959fb5f8": invalid repository name (4a4103f1a476d355d866b481ff96ac05a32a3a715cefcc1cbc1356a8959fb5f8), cannot specify 64-byte hexadecimal strings (docker.go:650:1s)
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/1309803
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.IGT: failure for tests/xe_spin_batch: Add spin-timestamp-check (rev4)
2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
` (4 preceding siblings ...)
2024-11-13 20:18 ` ✗ GitLab.Pipeline: warning " Patchwork
@ 2024-11-13 23:33 ` Patchwork
2024-11-14 6:49 ` ✗ CI.xeFULL: " Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-11-13 23:33 UTC (permalink / raw)
To: Pravalika Gurram; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 100272 bytes --]
== Series Details ==
Series: tests/xe_spin_batch: Add spin-timestamp-check (rev4)
URL : https://patchwork.freedesktop.org/series/140933/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15690_full -> IGTPW_12095_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_12095_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_12095_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/index.html
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-glk
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_12095_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_flip@plain-flip-ts-check@d-hdmi-a3:
- shard-dg1: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@kms_flip@plain-flip-ts-check@d-hdmi-a3.html
Known issues
------------
Here are the changes found in IGTPW_12095_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8411])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-7/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@crc32:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#6230])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@api_intel_bb@crc32.html
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#8411]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@device_reset@cold-reset-bound:
- shard-tglu: NOTRUN -> [SKIP][6] ([i915#11078]) +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@device_reset@cold-reset-bound.html
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#11078])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-hang@bcs0:
- shard-dg1: NOTRUN -> [SKIP][8] ([i915#8414]) +7 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@drm_fdinfo@busy-hang@bcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8414]) +8 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8414])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-7/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#3281]) +11 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_basic@multigpu-create-close:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#7697])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@gem_basic@multigpu-create-close.html
- shard-tglu: NOTRUN -> [SKIP][13] ([i915#7697])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@gem_basic@multigpu-create-close.html
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#7697])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-5/igt@gem_basic@multigpu-create-close.html
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#7697])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@gem_basic@multigpu-create-close.html
* igt@gem_busy@close-race:
- shard-dg2: NOTRUN -> [FAIL][16] ([i915#12296] / [i915#12577])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@gem_busy@close-race.html
- shard-tglu-1: NOTRUN -> [FAIL][17] ([i915#12296] / [i915#12577])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_busy@close-race.html
* igt@gem_ccs@block-copy-compressed:
- shard-snb: NOTRUN -> [SKIP][18] +64 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-snb7/igt@gem_ccs@block-copy-compressed.html
- shard-dg1: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#9323]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-tglu-1: NOTRUN -> [SKIP][20] ([i915#3555] / [i915#9323])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#3555] / [i915#9323])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-rkl: NOTRUN -> [SKIP][22] ([i915#9323])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
- shard-tglu-1: NOTRUN -> [SKIP][23] ([i915#9323])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu-1: NOTRUN -> [SKIP][24] ([i915#7697])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: NOTRUN -> [ABORT][25] ([i915#9846])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-tglu-1: NOTRUN -> [SKIP][26] ([i915#6335])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_create@create-ext-cpu-access-sanity-check.html
- shard-mtlp: NOTRUN -> [SKIP][27] ([i915#6335]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-7/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_create@create-ext-set-pat:
- shard-tglu: NOTRUN -> [SKIP][28] ([i915#8562])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-8/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_engines@invalid-engines:
- shard-mtlp: [PASS][29] -> [FAIL][30] ([i915#12031])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-mtlp-7/igt@gem_ctx_engines@invalid-engines.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-1/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#8555]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@gem_ctx_persistence@heartbeat-many.html
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#8555])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@hostile:
- shard-dg2: NOTRUN -> [FAIL][33] ([i915#11980] / [i915#12580])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@gem_ctx_persistence@hostile.html
- shard-dg1: NOTRUN -> [FAIL][34] ([i915#11980] / [i915#12580])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@gem_ctx_persistence@hostile.html
- shard-mtlp: NOTRUN -> [FAIL][35] ([i915#11980] / [i915#12580])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-5/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@engines:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#280])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@mmap-args:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#280])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@gem_ctx_sseu@mmap-args.html
- shard-tglu-1: NOTRUN -> [SKIP][38] ([i915#280])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][39] ([i915#7975] / [i915#8213])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu-1: NOTRUN -> [FAIL][40] ([i915#6117])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-rkl: NOTRUN -> [SKIP][41] ([i915#4525]) +1 other test skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@capture-recoverable:
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#6344])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_capture@capture@vecs0-lmem0:
- shard-dg1: NOTRUN -> [FAIL][43] ([i915#11965] / [i915#12558]) +2 other tests fail
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-18/igt@gem_exec_capture@capture@vecs0-lmem0.html
* igt@gem_exec_fair@basic-pace-share:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#3539] / [i915#4852]) +3 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@gem_exec_fair@basic-pace-share.html
- shard-tglu: NOTRUN -> [FAIL][45] ([i915#2842]) +1 other test fail
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-7/igt@gem_exec_fair@basic-pace-share.html
* igt@gem_exec_fair@basic-pace-solo:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#3539]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-7/igt@gem_exec_fair@basic-pace-solo.html
- shard-rkl: NOTRUN -> [FAIL][47] ([i915#2842]) +1 other test fail
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [PASS][48] -> [FAIL][49] ([i915#2842]) +1 other test fail
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@submit3:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4812]) +2 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@gem_exec_fence@submit3.html
* igt@gem_exec_flush@basic-wb-set-default:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#3539] / [i915#4852])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@gem_exec_flush@basic-wb-set-default.html
* igt@gem_exec_params@secure-non-root:
- shard-dg2: NOTRUN -> [SKIP][52] +12 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_reloc@basic-active:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#3281]) +6 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-5/igt@gem_exec_reloc@basic-active.html
* igt@gem_exec_reloc@basic-cpu-read-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][54] ([i915#3281]) +4 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-8/igt@gem_exec_reloc@basic-cpu-read-noreloc.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-dg1: NOTRUN -> [SKIP][55] ([i915#3281]) +8 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_schedule@pi-common@rcs0:
- shard-mtlp: NOTRUN -> [FAIL][56] ([i915#12296]) +6 other tests fail
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-2/igt@gem_exec_schedule@pi-common@rcs0.html
* igt@gem_exec_schedule@pi-common@vcs0:
- shard-dg1: NOTRUN -> [FAIL][57] ([i915#12296]) +5 other tests fail
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@gem_exec_schedule@pi-common@vcs0.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg1: NOTRUN -> [SKIP][58] ([i915#4812])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_fence_thrash@bo-write-verify-y:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#4860]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@gem_fence_thrash@bo-write-verify-y.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#4860]) +3 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#4860])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_huc_copy@huc-copy:
- shard-tglu: NOTRUN -> [SKIP][62] ([i915#2190])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-tglu-1: NOTRUN -> [SKIP][63] ([i915#4613] / [i915#7582])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@basic:
- shard-tglu-1: NOTRUN -> [SKIP][64] ([i915#4613]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-tglu: NOTRUN -> [SKIP][65] ([i915#4613]) +4 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-8/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#4613]) +5 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify:
- shard-mtlp: NOTRUN -> [SKIP][67] ([i915#4613])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@gem_lmem_swapping@verify.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#12193]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_lmem_swapping@verify-random-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][69] ([i915#4565]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
* igt@gem_madvise@dontneed-before-exec:
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#3282]) +3 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-2/igt@gem_madvise@dontneed-before-exec.html
* igt@gem_media_fill@media-fill:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#8289])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@gem_media_fill@media-fill.html
* igt@gem_media_vme:
- shard-tglu: NOTRUN -> [SKIP][72] ([i915#284])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@gem_media_vme.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#4077]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-6/igt@gem_mmap_gtt@basic-write-read-distinct.html
* igt@gem_mmap_wc@copy:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#4083]) +5 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@gem_mmap_wc@copy.html
* igt@gem_mmap_wc@pf-nonblock:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#4083]) +2 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@gem_mmap_wc@pf-nonblock.html
- shard-mtlp: NOTRUN -> [SKIP][76] ([i915#4083])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-1/igt@gem_mmap_wc@pf-nonblock.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#3282]) +7 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#3282]) +4 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-tglu-1: NOTRUN -> [SKIP][79] ([i915#4270]) +2 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][80] ([i915#4270]) +5 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
- shard-dg1: NOTRUN -> [SKIP][81] ([i915#4270]) +3 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#4270]) +4 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-tglu: NOTRUN -> [SKIP][83] ([i915#4270]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-8/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#5190] / [i915#8428]) +5 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#8428])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_render_tiled_blits@basic:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#4079])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@gem_render_tiled_blits@basic.html
- shard-mtlp: NOTRUN -> [SKIP][87] ([i915#4079])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#4079]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-7/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#4885])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#3282]) +8 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@gem_tiled_partial_pwrite_pread@writes.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-tglu-1: NOTRUN -> [SKIP][91] ([i915#3297])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#3297]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@gem_userptr_blits@create-destroy-unsync.html
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#3297]) +1 other test skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-6/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-tglu: NOTRUN -> [SKIP][94] ([i915#3297] / [i915#3323])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#3297] / [i915#4880])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#3297]) +4 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@gem_userptr_blits@unsync-unmap-cycles.html
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#3297]) +4 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen7_exec_parse@chained-batch:
- shard-rkl: NOTRUN -> [SKIP][98] +28 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@gen7_exec_parse@chained-batch.html
* igt@gen9_exec_parse@basic-rejected:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#2856]) +2 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-8/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@bb-chained:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#2527]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-dg1: NOTRUN -> [SKIP][101] ([i915#2527]) +2 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglu: NOTRUN -> [SKIP][102] ([i915#2527] / [i915#2856]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#2856]) +5 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [PASS][104] -> [ABORT][105] ([i915#9820])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-tglu-2/igt@i915_module_load@reload-with-fault-injection.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#6412])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@i915_module_load@resize-bar.html
- shard-tglu: NOTRUN -> [SKIP][107] ([i915#6412])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-tglu-1: NOTRUN -> [SKIP][108] ([i915#8399])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-tglu: NOTRUN -> [SKIP][109] ([i915#8399])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-rkl: NOTRUN -> [SKIP][110] ([i915#6590]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@i915_pm_freq_mult@media-freq@gt0.html
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#6590]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@i915_pm_freq_mult@media-freq@gt0.html
- shard-tglu: NOTRUN -> [SKIP][112] ([i915#6590]) +1 other test skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_freq_mult@media-freq@gt1:
- shard-mtlp: NOTRUN -> [SKIP][113] ([i915#6590]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-2/igt@i915_pm_freq_mult@media-freq@gt1.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: [PASS][114] -> [FAIL][115] ([i915#12739] / [i915#3591])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [PASS][116] -> [FAIL][117] ([i915#12548] / [i915#3591]) +1 other test fail
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][118] ([i915#11681] / [i915#6621]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_sseu@full-enable:
- shard-tglu-1: NOTRUN -> [SKIP][119] ([i915#4387])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@i915_pm_sseu@full-enable.html
* igt@i915_power@sanity:
- shard-mtlp: [PASS][120] -> [SKIP][121] ([i915#7984])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-mtlp-8/igt@i915_power@sanity.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-1/igt@i915_power@sanity.html
* igt@i915_query@hwconfig_table:
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#6245])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@i915_query@hwconfig_table.html
* igt@i915_query@test-query-geometry-subslices:
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#5723])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-snb: [PASS][124] -> [ABORT][125] ([i915#11703])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-snb6/igt@i915_suspend@basic-s3-without-i915.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-snb4/igt@i915_suspend@basic-s3-without-i915.html
- shard-dg1: [PASS][126] -> [DMESG-WARN][127] ([i915#4391] / [i915#4423])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-16/igt@i915_suspend@basic-s3-without-i915.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@i915_suspend@basic-s3-without-i915.html
* igt@i915_suspend@fence-restore-untiled:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#4077]) +9 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@i915_suspend@fence-restore-untiled.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#7707])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#4212])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
- shard-dg1: NOTRUN -> [SKIP][131] ([i915#4212])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@bad-pitch-256:
- shard-dg1: [PASS][132] -> [DMESG-WARN][133] ([i915#4423])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-15/igt@kms_addfb_basic@bad-pitch-256.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_addfb_basic@bad-pitch-256.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu: NOTRUN -> [SKIP][134] ([i915#12454] / [i915#12712])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][135] ([i915#8709]) +3 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-tglu-1: NOTRUN -> [SKIP][136] ([i915#9531])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-tglu-1: NOTRUN -> [SKIP][137] ([i915#1769] / [i915#3555])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#1769] / [i915#3555])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#5286])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-16/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][140] ([i915#5286]) +4 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][141] ([i915#4538] / [i915#5286]) +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#5286]) +4 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglu-1: NOTRUN -> [SKIP][143] ([i915#5286]) +4 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#4538] / [i915#5190]) +13 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][145] ([i915#3638]) +1 other test skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#3638]) +2 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#5190]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#4538]) +3 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#10307] / [i915#10434] / [i915#6095]) +5 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#10307] / [i915#6095]) +175 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-4/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#6095]) +143 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-18/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][152] ([i915#6095]) +9 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-3/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-c-edp-1.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][153] ([i915#6095]) +94 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-7/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#12313]) +3 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
- shard-dg1: NOTRUN -> [SKIP][155] ([i915#12313]) +1 other test skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
- shard-tglu: NOTRUN -> [SKIP][156] ([i915#12313])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#12313])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-5/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][158] ([i915#6095]) +102 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][159] ([i915#6095]) +34 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#6095]) +17 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-b-dp-4.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][161] ([i915#12313])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#12313]) +1 other test skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs:
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#4423] / [i915#6095]) +1 other test skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-tglu: NOTRUN -> [SKIP][164] ([i915#3742])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_cdclk@mode-transition-all-outputs.html
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#11616] / [i915#7213])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#3742])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_cdclk@plane-scaling.html
- shard-dg1: NOTRUN -> [SKIP][167] ([i915#3742])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#4087]) +4 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-7/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#7828]) +11 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-tglu-1: NOTRUN -> [SKIP][170] ([i915#7828]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-mtlp: NOTRUN -> [SKIP][171] +5 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k:
- shard-tglu: NOTRUN -> [SKIP][172] ([i915#7828]) +7 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html
* igt@kms_chamelium_edid@hdmi-mode-timings:
- shard-mtlp: NOTRUN -> [SKIP][173] ([i915#7828]) +3 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-2/igt@kms_chamelium_edid@hdmi-mode-timings.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#7828]) +11 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-dg1: NOTRUN -> [SKIP][175] ([i915#7828]) +7 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_content_protection@content-type-change:
- shard-dg1: NOTRUN -> [SKIP][176] ([i915#9424])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#3116])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#3299])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_content_protection@dp-mst-type-0.html
- shard-mtlp: NOTRUN -> [SKIP][179] ([i915#3299])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-6/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-tglu: NOTRUN -> [SKIP][180] ([i915#3116] / [i915#3299])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_content_protection@dp-mst-type-1.html
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#3299])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#9424])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@kms_content_protection@lic-type-0.html
- shard-tglu-1: NOTRUN -> [SKIP][183] ([i915#6944] / [i915#9424])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#9424])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@kms_content_protection@mei-interface.html
- shard-tglu: NOTRUN -> [SKIP][185] ([i915#6944] / [i915#9424])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#7118])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#7118] / [i915#9424])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@kms_content_protection@uevent.html
- shard-dg1: NOTRUN -> [SKIP][188] ([i915#7116] / [i915#9424])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#8814])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-8/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-dg1: NOTRUN -> [SKIP][190] ([i915#11453] / [i915#3359]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-mtlp: NOTRUN -> [SKIP][191] ([i915#3555] / [i915#8814])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-5/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-tglu-1: NOTRUN -> [SKIP][192] ([i915#11453] / [i915#3359])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-tglu: NOTRUN -> [SKIP][193] ([i915#3555]) +4 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#3555]) +3 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-tglu: NOTRUN -> [SKIP][195] ([i915#11453] / [i915#3359]) +1 other test skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-8/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
- shard-mtlp: NOTRUN -> [SKIP][196] ([i915#11453] / [i915#3359])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#11453] / [i915#3359]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#11453] / [i915#3359]) +5 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][199] ([i915#9809]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-8/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#4103])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#4103] / [i915#4213])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- shard-tglu: NOTRUN -> [SKIP][202] ([i915#4103])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#5354]) +46 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-snb: [PASS][204] -> [FAIL][205] ([i915#2346])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-snb4/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-snb5/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#9067])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#9833])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@extended-mode-basic:
- shard-mtlp: NOTRUN -> [SKIP][208] ([i915#3555] / [i915#8827])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-7/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-tglu: NOTRUN -> [SKIP][209] ([i915#8588])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: NOTRUN -> [SKIP][210] ([i915#3555]) +6 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#1257])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-6/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#8812])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#3555] / [i915#3840]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@kms_dsc@dsc-basic.html
- shard-rkl: NOTRUN -> [SKIP][214] ([i915#3555] / [i915#3840]) +1 other test skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-rkl: NOTRUN -> [SKIP][215] ([i915#3840])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-formats:
- shard-tglu: NOTRUN -> [SKIP][216] ([i915#3555] / [i915#3840]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_dsc@dsc-with-formats.html
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#3555] / [i915#3840])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-2/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg1: NOTRUN -> [SKIP][218] ([i915#3555] / [i915#3840]) +2 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-tglu-1: NOTRUN -> [SKIP][219] ([i915#3840] / [i915#9053])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][220] ([i915#4854])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-4/igt@kms_feature_discovery@chamelium.html
- shard-dg1: NOTRUN -> [SKIP][221] ([i915#4854])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-2x:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#1839])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@kms_feature_discovery@display-2x.html
- shard-tglu-1: NOTRUN -> [SKIP][223] ([i915#1839])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_feature_discovery@display-2x.html
- shard-dg1: NOTRUN -> [SKIP][224] ([i915#1839])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-18/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-3x:
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#1839])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@display-4x:
- shard-tglu: NOTRUN -> [SKIP][226] ([i915#1839])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@psr2:
- shard-rkl: NOTRUN -> [SKIP][227] ([i915#658])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#3637]) +1 other test skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-6/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-tglu: NOTRUN -> [SKIP][229] ([i915#3637]) +7 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#9934]) +12 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#9934]) +6 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][232] ([i915#3637]) +3 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@blocking-wf_vblank@c-hdmi-a1:
- shard-tglu: [PASS][233] -> [FAIL][234] ([i915#2122]) +8 other tests fail
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-tglu-7/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
- shard-mtlp: [PASS][235] -> [FAIL][236] ([i915#2122]) +2 other tests fail
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-mtlp-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-ts-check:
- shard-dg2: NOTRUN -> [FAIL][237] ([i915#2122]) +5 other tests fail
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@kms_flip@plain-flip-ts-check.html
- shard-dg1: NOTRUN -> [FAIL][238] ([i915#12457] / [i915#12517] / [i915#12702] / [i915#2122])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@kms_flip@plain-flip-ts-check.html
- shard-tglu: NOTRUN -> [FAIL][239] ([i915#2122]) +1 other test fail
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_flip@plain-flip-ts-check.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a3:
- shard-dg1: NOTRUN -> [FAIL][240] ([i915#11989])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@kms_flip@plain-flip-ts-check@a-hdmi-a3.html
* igt@kms_flip@plain-flip-ts-check@b-vga1:
- shard-snb: [PASS][241] -> [FAIL][242] ([i915#2122]) +7 other tests fail
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-snb5/igt@kms_flip@plain-flip-ts-check@b-vga1.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-snb6/igt@kms_flip@plain-flip-ts-check@b-vga1.html
* igt@kms_flip@plain-flip-ts-check@c-hdmi-a3:
- shard-dg1: NOTRUN -> [FAIL][243] ([i915#12457]) +1 other test fail
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@kms_flip@plain-flip-ts-check@c-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][244] ([i915#2672] / [i915#3555])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][245] ([i915#2587] / [i915#2672]) +2 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
- shard-mtlp: NOTRUN -> [SKIP][246] ([i915#2672] / [i915#3555] / [i915#8813]) +1 other test skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
- shard-dg2: NOTRUN -> [SKIP][247] ([i915#2672] / [i915#3555]) +3 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][248] ([i915#2587] / [i915#2672]) +4 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][249] ([i915#2672]) +7 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][250] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][251] ([i915#2672]) +5 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- shard-tglu: NOTRUN -> [SKIP][253] ([i915#2672] / [i915#3555]) +5 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][254] ([i915#3555] / [i915#8813])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][255] ([i915#8810])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][256] ([i915#2587] / [i915#2672]) +5 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][257] ([i915#2672] / [i915#3555]) +7 other tests skip
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][258] ([i915#2672] / [i915#8813]) +1 other test skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][259] ([i915#3555] / [i915#8810] / [i915#8813])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][260] ([i915#3555] / [i915#8810])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][261] ([i915#2672] / [i915#3555]) +4 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: [PASS][262] -> [FAIL][263] ([i915#6880])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][264] ([i915#8708]) +22 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][265] ([i915#1825]) +9 other tests skip
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][266] +34 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [FAIL][267] ([i915#6880]) +1 other test fail
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][268] ([i915#5439]) +1 other test skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][269] ([i915#10055])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][270] ([i915#4423])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][271] ([i915#8708]) +14 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-dg2: NOTRUN -> [SKIP][272] ([i915#10433] / [i915#3458])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][273] ([i915#5439])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
- shard-tglu: NOTRUN -> [SKIP][274] ([i915#5439])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][275] ([i915#3458]) +15 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][276] ([i915#3458]) +15 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][277] ([i915#3023]) +36 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][278] ([i915#1825]) +56 other tests skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
- shard-tglu-1: NOTRUN -> [SKIP][279] +49 other tests skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-tglu: NOTRUN -> [SKIP][280] +80 other tests skip
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglu: NOTRUN -> [SKIP][281] ([i915#433])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-8/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@bpc-switch:
- shard-tglu-1: NOTRUN -> [SKIP][282] ([i915#3555] / [i915#8228])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-tglu: NOTRUN -> [SKIP][283] ([i915#3555] / [i915#8228])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg1: NOTRUN -> [SKIP][284] ([i915#12713])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][285] ([i915#3555] / [i915#8228]) +1 other test skip
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-8/igt@kms_hdr@invalid-metadata-sizes.html
- shard-dg1: NOTRUN -> [SKIP][286] ([i915#3555] / [i915#8228])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-swap:
- shard-dg2: [PASS][287] -> [SKIP][288] ([i915#3555] / [i915#8228])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-10/igt@kms_hdr@static-swap.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@kms_hdr@static-swap.html
* igt@kms_joiner@basic-big-joiner:
- shard-dg2: NOTRUN -> [SKIP][289] ([i915#10656])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-tglu: NOTRUN -> [SKIP][290] ([i915#12394])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-6/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-rkl: NOTRUN -> [SKIP][291] ([i915#12339])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][292] ([i915#12388])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@kms_joiner@invalid-modeset-force-big-joiner.html
- shard-tglu: NOTRUN -> [SKIP][293] ([i915#12388])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][294] ([i915#12394])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][295] ([i915#12339])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-dg1: NOTRUN -> [SKIP][296] ([i915#12339])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_plane_lowres@tiling-4:
- shard-mtlp: NOTRUN -> [SKIP][297] ([i915#10226] / [i915#11614] / [i915#3555] / [i915#8821])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@kms_plane_lowres@tiling-4.html
* igt@kms_plane_lowres@tiling-4@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][298] ([i915#11614] / [i915#3582]) +3 other tests skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@kms_plane_lowres@tiling-4@pipe-b-edp-1.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-dg2: NOTRUN -> [SKIP][299] ([i915#5354] / [i915#9423])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a:
- shard-dg1: NOTRUN -> [SKIP][300] ([i915#12247] / [i915#12504]) +3 other tests skip
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
- shard-rkl: NOTRUN -> [SKIP][301] ([i915#3555]) +10 other tests skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b:
- shard-rkl: NOTRUN -> [SKIP][302] ([i915#12247]) +15 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html
- shard-tglu-1: NOTRUN -> [SKIP][303] ([i915#12247]) +8 other tests skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-c:
- shard-tglu: NOTRUN -> [SKIP][304] ([i915#12247]) +4 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-c.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d:
- shard-dg1: NOTRUN -> [SKIP][305] ([i915#12247]) +5 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75:
- shard-mtlp: NOTRUN -> [SKIP][306] ([i915#12247] / [i915#3555] / [i915#6953])
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-7/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-b:
- shard-mtlp: NOTRUN -> [SKIP][307] ([i915#12247]) +8 other tests skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-7/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-b.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][308] ([i915#12247] / [i915#6953])
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
* igt@kms_pm_backlight@bad-brightness:
- shard-tglu-1: NOTRUN -> [SKIP][309] ([i915#9812])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@basic-brightness:
- shard-rkl: NOTRUN -> [SKIP][310] ([i915#5354])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-3/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-tglu: NOTRUN -> [SKIP][311] ([i915#9812])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2: NOTRUN -> [SKIP][312] ([i915#9685]) +3 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@kms_pm_dc@dc3co-vpb-simulation.html
- shard-rkl: NOTRUN -> [SKIP][313] ([i915#9685]) +1 other test skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_pm_dc@dc3co-vpb-simulation.html
- shard-tglu: NOTRUN -> [SKIP][314] ([i915#9685])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-rkl: NOTRUN -> [SKIP][315] ([i915#3828])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu-1: NOTRUN -> [FAIL][316] ([i915#9295])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_pm_dc@dc6-dpms.html
- shard-dg1: NOTRUN -> [SKIP][317] ([i915#3361])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [PASS][318] -> [SKIP][319] ([i915#4281])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-tglu-2/igt@kms_pm_dc@dc9-dpms.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-7/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: NOTRUN -> [SKIP][320] ([i915#9340])
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-6/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [PASS][321] -> [SKIP][322] ([i915#9519]) +1 other test skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-8/igt@kms_pm_rpm@dpms-lpsp.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@kms_pm_rpm@dpms-lpsp.html
- shard-rkl: [PASS][323] -> [SKIP][324] ([i915#9519]) +1 other test skip
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-rkl-4/igt@kms_pm_rpm@dpms-lpsp.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@fences:
- shard-dg1: NOTRUN -> [SKIP][325] ([i915#4077]) +9 other tests skip
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_pm_rpm@fences.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-mtlp: NOTRUN -> [SKIP][326] ([i915#9519])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-2/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: NOTRUN -> [SKIP][327] ([i915#9519]) +1 other test skip
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-tglu: NOTRUN -> [SKIP][328] ([i915#9519]) +1 other test skip
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg1: NOTRUN -> [SKIP][329] ([i915#6524])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@kms_prime@basic-crc-vgem.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-rkl: NOTRUN -> [SKIP][330] ([i915#6524]) +1 other test skip
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@kms_prime@basic-modeset-hybrid.html
- shard-tglu: NOTRUN -> [SKIP][331] ([i915#6524])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_prime@d3hot:
- shard-tglu-1: NOTRUN -> [SKIP][332] ([i915#6524]) +1 other test skip
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
- shard-tglu: NOTRUN -> [SKIP][333] ([i915#11520]) +6 other tests skip
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-9/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-dg2: NOTRUN -> [SKIP][334] ([i915#11520]) +10 other tests skip
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-5/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
- shard-snb: NOTRUN -> [SKIP][335] ([i915#11520])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-snb6/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][336] ([i915#9808])
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][337] ([i915#11520]) +12 other tests skip
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
- shard-tglu-1: NOTRUN -> [SKIP][338] ([i915#11520]) +1 other test skip
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-mtlp: NOTRUN -> [SKIP][339] ([i915#12316]) +3 other tests skip
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg1: NOTRUN -> [SKIP][340] ([i915#11520]) +6 other tests skip
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu: NOTRUN -> [SKIP][341] ([i915#9683])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-tglu-1: NOTRUN -> [SKIP][342] ([i915#9683])
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][343] ([i915#9683]) +1 other test skip
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@kms_psr2_su@page_flip-xrgb8888.html
- shard-dg1: NOTRUN -> [SKIP][344] ([i915#9683]) +1 other test skip
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-psr-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][345] ([i915#1072] / [i915#9732]) +29 other tests skip
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@kms_psr@fbc-psr-primary-mmap-gtt.html
* igt@kms_psr@pr-dpms:
- shard-tglu: NOTRUN -> [SKIP][346] ([i915#9732]) +22 other tests skip
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-7/igt@kms_psr@pr-dpms.html
* igt@kms_psr@pr-primary-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][347] ([i915#9688]) +9 other tests skip
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-6/igt@kms_psr@pr-primary-mmap-cpu.html
* igt@kms_psr@pr-suspend:
- shard-tglu-1: NOTRUN -> [SKIP][348] ([i915#9732]) +12 other tests skip
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_psr@pr-suspend.html
* igt@kms_psr@psr-sprite-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][349] ([i915#1072] / [i915#9732]) +19 other tests skip
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@kms_psr@psr-sprite-mmap-cpu.html
* igt@kms_psr@psr2-suspend:
- shard-rkl: NOTRUN -> [SKIP][350] ([i915#1072] / [i915#9732]) +34 other tests skip
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_psr@psr2-suspend.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg1: NOTRUN -> [SKIP][351] ([i915#9685])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2: NOTRUN -> [SKIP][352] ([i915#12755]) +1 other test skip
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg1: NOTRUN -> [SKIP][353] ([i915#4884])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-18/igt@kms_rotation_crc@exhaust-fences.html
- shard-dg2: NOTRUN -> [SKIP][354] ([i915#4235])
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][355] ([i915#5289]) +1 other test skip
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-tglu: NOTRUN -> [SKIP][356] ([i915#5289])
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_selftest@drm_framebuffer:
- shard-tglu: NOTRUN -> [ABORT][357] ([i915#12231]) +1 other test abort
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-2/igt@kms_selftest@drm_framebuffer.html
* igt@kms_setmode@basic:
- shard-tglu: NOTRUN -> [FAIL][358] ([i915#5465]) +2 other tests fail
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-6/igt@kms_setmode@basic.html
- shard-rkl: [PASS][359] -> [FAIL][360] ([i915#5465])
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-rkl-7/igt@kms_setmode@basic.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][361] ([i915#5465]) +1 other test fail
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@kms_setmode@basic@pipe-b-hdmi-a-2.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-tglu-1: NOTRUN -> [SKIP][362] ([i915#3555]) +5 other tests skip
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_sysfs_edid_timing:
- shard-dg1: NOTRUN -> [FAIL][363] ([IGT#2] / [i915#6493])
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-18/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-mtlp: NOTRUN -> [SKIP][364] ([i915#8623])
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu: NOTRUN -> [SKIP][365] ([i915#8623])
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-dg2: NOTRUN -> [SKIP][366] ([i915#8623])
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-mtlp: [PASS][367] -> [FAIL][368] ([i915#9196]) +1 other test fail
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-1/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_vrr@flip-basic:
- shard-mtlp: NOTRUN -> [SKIP][369] ([i915#3555] / [i915#8808])
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@kms_vrr@flip-basic.html
* igt@kms_vrr@negative-basic:
- shard-tglu: NOTRUN -> [SKIP][370] ([i915#3555] / [i915#9906])
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-5/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-rkl: NOTRUN -> [SKIP][371] ([i915#9906]) +1 other test skip
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-5/igt@kms_vrr@seamless-rr-switch-drrs.html
- shard-dg2: NOTRUN -> [SKIP][372] ([i915#9906])
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg1: NOTRUN -> [SKIP][373] ([i915#2437] / [i915#9412])
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-14/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-mtlp: NOTRUN -> [SKIP][374] ([i915#2437] / [i915#9412])
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-5/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][375] ([i915#2437] / [i915#9412]) +1 other test skip
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-tglu-1: NOTRUN -> [SKIP][376] ([i915#2437] / [i915#9412])
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg1: NOTRUN -> [SKIP][377] ([i915#2437])
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-18/igt@kms_writeback@writeback-invalid-parameters.html
- shard-mtlp: NOTRUN -> [SKIP][378] ([i915#2437])
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-6/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-rkl: NOTRUN -> [SKIP][379] ([i915#2437] / [i915#9412])
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-1/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@blocking@0-rcs0:
- shard-dg1: [PASS][380] -> [FAIL][381] ([i915#10538]) +1 other test fail
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-18/igt@perf@blocking@0-rcs0.html
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@perf@blocking@0-rcs0.html
* igt@perf@global-sseu-config-invalid:
- shard-dg2: NOTRUN -> [SKIP][382] ([i915#7387])
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@perf@global-sseu-config-invalid.html
* igt@perf@mi-rpc:
- shard-dg1: NOTRUN -> [SKIP][383] ([i915#2434])
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-18/igt@perf@mi-rpc.html
* igt@perf_pmu@all-busy-idle-check-all:
- shard-dg2: [PASS][384] -> [FAIL][385] ([i915#11943])
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-4/igt@perf_pmu@all-busy-idle-check-all.html
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@perf_pmu@all-busy-idle-check-all.html
- shard-dg1: [PASS][386] -> [FAIL][387] ([i915#11943])
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-14/igt@perf_pmu@all-busy-idle-check-all.html
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-16/igt@perf_pmu@all-busy-idle-check-all.html
- shard-mtlp: [PASS][388] -> [FAIL][389] ([i915#11943])
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-mtlp-2/igt@perf_pmu@all-busy-idle-check-all.html
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-4/igt@perf_pmu@all-busy-idle-check-all.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][390] ([i915#11823] / [i915#12555])
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][391] ([i915#8516])
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-2/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-tglu: NOTRUN -> [SKIP][392] ([i915#8516])
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-7/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_mmap@test_aperture_limit:
- shard-dg2: NOTRUN -> [WARN][393] ([i915#9351])
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@prime_mmap@test_aperture_limit.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: NOTRUN -> [CRASH][394] ([i915#9351])
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-gtt:
- shard-dg1: NOTRUN -> [SKIP][395] ([i915#3708] / [i915#4077])
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-15/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][396] ([i915#3708] / [i915#4077]) +1 other test skip
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-4/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2: NOTRUN -> [SKIP][397] ([i915#3708]) +1 other test skip
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@prime_vgem@fence-read-hang.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][398] ([i915#3708])
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-2/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][399] ([i915#9917]) +2 other tests skip
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-6/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-dg2: NOTRUN -> [SKIP][400] ([i915#9917]) +2 other tests skip
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-3/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-tglu: NOTRUN -> [SKIP][401] ([i915#9917])
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-4/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-tglu-1: NOTRUN -> [SKIP][402] ([i915#9917])
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each.html
- shard-dg1: NOTRUN -> [SKIP][403] ([i915#9917]) +1 other test skip
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-12/igt@sriov_basic@enable-vfs-bind-unbind-each.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg1: NOTRUN -> [SKIP][404] ([i915#4818])
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_ctx_freq@sysfs:
- shard-dg2: [FAIL][405] ([i915#9561]) -> [PASS][406] +1 other test pass
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-11/igt@gem_ctx_freq@sysfs.html
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-5/igt@gem_ctx_freq@sysfs.html
* igt@gem_eio@kms:
- shard-dg2: [FAIL][407] ([i915#5784]) -> [PASS][408]
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-2/igt@gem_eio@kms.html
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-6/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [FAIL][409] ([i915#2842]) -> [PASS][410]
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-rkl-5/igt@gem_exec_fair@basic-none@vecs0.html
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_suspend@basic-s0@lmem0:
- shard-dg2: [INCOMPLETE][411] ([i915#11441]) -> [PASS][412] +1 other test pass
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-3/igt@gem_exec_suspend@basic-s0@lmem0.html
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-1/igt@gem_exec_suspend@basic-s0@lmem0.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-dg2: [ABORT][413] ([i915#7975] / [i915#8213]) -> [PASS][414] +1 other test pass
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-4/igt@gem_exec_suspend@basic-s4-devices.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg1: [ABORT][415] ([i915#7975] / [i915#8213]) -> [PASS][416] +1 other test pass
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-13/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][417] ([i915#7790]) -> [PASS][418]
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-snb2/igt@i915_pm_rps@reset.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-snb4/igt@i915_pm_rps@reset.html
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180:
- shard-dg1: [DMESG-WARN][419] ([i915#4391] / [i915#4423]) -> [PASS][420]
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-19/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-19/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-dg1: [DMESG-WARN][421] ([i915#4423]) -> [PASS][422] +6 other tests pass
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg1-19/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg1-17/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-rkl: [ABORT][423] ([i915#10354]) -> [PASS][424]
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-rkl-3/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_color@deep-color:
- shard-dg2: [SKIP][425] ([i915#3555]) -> [PASS][426]
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-dg2-7/igt@kms_color@deep-color.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-dg2-10/igt@kms_color@deep-color.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-snb: [FAIL][427] ([i915#2122]) -> [PASS][428] +1 other test pass
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-snb6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-snb4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-rkl: [FAIL][429] ([i915#10826]) -> [PASS][430] +1 other test pass
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-rkl-3/igt@kms_flip@dpms-vs-vblank-race.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-rkl-6/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-mtlp: [INCOMPLETE][431] -> [PASS][432] +1 other test pass
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15690/shard-mtlp-3/igt@kms_flip@plain-flip-ts-check@a-edp1.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/shard-mtlp-2/igt@kms_flip@plain-flip-ts-check@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-snb: [SKIP][433] -> [PASS][434
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12095/index.html
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^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ CI.xeFULL: failure for tests/xe_spin_batch: Add spin-timestamp-check (rev4)
2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
` (5 preceding siblings ...)
2024-11-13 23:33 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-11-14 6:49 ` Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-11-14 6:49 UTC (permalink / raw)
To: Pravalika Gurram; +Cc: igt-dev
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== Series Details ==
Series: tests/xe_spin_batch: Add spin-timestamp-check (rev4)
URL : https://patchwork.freedesktop.org/series/140933/
State : failure
== Summary ==
CI Bug Log - changes from XEIGT_8107_full -> XEIGTPW_12095_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with XEIGTPW_12095_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in XEIGTPW_12095_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in XEIGTPW_12095_full:
### IGT changes ###
#### Possible regressions ####
* igt@core_getversion@all-cards:
- shard-dg2-set2: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@core_getversion@all-cards.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@core_getversion@all-cards.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-lnl: [PASS][3] -> [FAIL][4] +1 other test fail
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-1/igt@kms_psr@fbc-psr2-sprite-render.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-5/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@xe_exec_compute_mode@many-execqueues-userptr-invalidate:
- shard-bmg: [PASS][5] -> [INCOMPLETE][6] +3 other tests incomplete
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-8/igt@xe_exec_compute_mode@many-execqueues-userptr-invalidate.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-4/igt@xe_exec_compute_mode@many-execqueues-userptr-invalidate.html
#### Warnings ####
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
- shard-dg2-set2: [SKIP][7] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [TIMEOUT][9] ([Intel XE#1473]) -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html
New tests
---------
New tests have been introduced between XEIGT_8107_full and XEIGTPW_12095_full:
### New IGT tests (6) ###
* igt@xe_spin_batch@spin-timestamp-check:
- Statuses : 2 pass(s) 1 skip(s)
- Exec time: [0.0, 8.02] s
* igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_compute:
- Statuses : 2 pass(s)
- Exec time: [1.15] s
* igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_copy:
- Statuses : 2 pass(s)
- Exec time: [1.15] s
* igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_render:
- Statuses : 2 pass(s)
- Exec time: [1.13, 1.14] s
* igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_video_decode:
- Statuses : 2 pass(s)
- Exec time: [1.15, 2.27] s
* igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_video_enhance:
- Statuses : 2 pass(s)
- Exec time: [1.15, 2.30] s
Known issues
------------
Here are the changes found in XEIGTPW_12095_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@hotreplug-lateclose:
- shard-dg2-set2: [PASS][11] -> [SKIP][12] ([Intel XE#1885]) +1 other test skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@core_hotunplug@hotreplug-lateclose.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@core_hotunplug@hotreplug-lateclose.html
* igt@core_setmaster@master-drop-set-user:
- shard-dg2-set2: NOTRUN -> [FAIL][13] ([Intel XE#3339])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@core_setmaster@master-drop-set-user.html
* igt@fbdev@eof:
- shard-dg2-set2: [PASS][14] -> [SKIP][15] ([Intel XE#2134]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@fbdev@eof.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@fbdev@eof.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
- shard-lnl: [PASS][16] -> [FAIL][17] ([Intel XE#911]) +3 other tests fail
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
* igt@kms_async_flips@test-cursor@pipe-a-dp-2:
- shard-bmg: [PASS][18] -> [DMESG-WARN][19] ([Intel XE#877]) +2 other tests dmesg-warn
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-7/igt@kms_async_flips@test-cursor@pipe-a-dp-2.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-6/igt@kms_async_flips@test-cursor@pipe-a-dp-2.html
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180:
- shard-lnl: [PASS][20] -> [FAIL][21] ([Intel XE#1454]) +1 other test fail
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-1/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-1/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][22] ([Intel XE#316]) +2 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#1124]) +3 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#1124]) +5 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#610])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#367]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2314] / [Intel XE#2894])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#2191])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-2-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#367])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][30] ([Intel XE#787]) +178 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#2887]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-1/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#3432])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#455] / [Intel XE#787]) +36 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-dp-4.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][34] ([Intel XE#314]) +3 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][35] ([Intel XE#1152]) +3 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html
* igt@kms_chamelium_color@ctm-negative:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2325])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-3/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2252]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-2/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@dp-hpd-storm:
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#373]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_chamelium_hpd@dp-hpd-storm.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][39] ([Intel XE#1178])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#307]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#308])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#2321])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-7/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_edge_walk@128x128-left-edge:
- shard-lnl: [PASS][43] -> [FAIL][44] ([Intel XE#2577]) +1 other test fail
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-6/igt@kms_cursor_edge_walk@128x128-left-edge.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-4/igt@kms_cursor_edge_walk@128x128-left-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-dg2-set2: NOTRUN -> [SKIP][45] ([Intel XE#2423] / [i915#2575]) +21 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@torture-bo@all-pipes:
- shard-dg2-set2: NOTRUN -> [DMESG-WARN][46] ([Intel XE#3184])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_cursor_legacy@torture-bo@all-pipes.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
- shard-bmg: NOTRUN -> [FAIL][47] ([Intel XE#2141]) +2 other tests fail
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
* igt@kms_dp_aux_dev:
- shard-dg2-set2: [PASS][48] -> [SKIP][49] ([Intel XE#2423]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_dp_aux_dev.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#2244])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-4/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#776])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-8/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-dp2:
- shard-bmg: [PASS][52] -> [FAIL][53] ([Intel XE#2882]) +2 other tests fail
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-dp2.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-dp2.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1:
- shard-lnl: [PASS][54] -> [FAIL][55] ([Intel XE#886]) +1 other test fail
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-5/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-1/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-dp5:
- shard-dg2-set2: NOTRUN -> [FAIL][56] ([Intel XE#301]) +2 other tests fail
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@b-dp5.html
* igt@kms_flip@flip-vs-expired-vblank@d-dp5:
- shard-dg2-set2: NOTRUN -> [FAIL][57] ([Intel XE#3403])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@d-dp5.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
- shard-dg2-set2: [PASS][58] -> [SKIP][59] ([Intel XE#2136]) +29 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#2380]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-dg2-set2: NOTRUN -> [SKIP][61] ([Intel XE#455]) +10 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@basic:
- shard-dg2-set2: [PASS][62] -> [SKIP][63] ([Intel XE#2351])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@kms_frontbuffer_tracking@basic.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-bmg: NOTRUN -> [FAIL][64] ([Intel XE#2333]) +2 other tests fail
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [PASS][65] -> [SKIP][66] ([Intel XE#2136] / [Intel XE#2351]) +12 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][67] ([Intel XE#2311]) +8 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][68] ([Intel XE#651]) +8 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#2136]) +16 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][70] ([Intel XE#653]) +12 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#2313]) +9 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#2352])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_lease@lease-invalid-crtc:
- shard-dg2-set2: [PASS][73] -> [SKIP][74] ([Intel XE#2423] / [i915#2575]) +105 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_lease@lease-invalid-crtc.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_lease@lease-invalid-crtc.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#2501])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#356])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [FAIL][77] ([Intel XE#361])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d:
- shard-dg2-set2: NOTRUN -> [SKIP][78] ([Intel XE#2763] / [Intel XE#455]) +2 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#2763]) +8 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#870])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_rpm@cursor:
- shard-dg2-set2: NOTRUN -> [SKIP][81] ([Intel XE#2446]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_pm_rpm@cursor.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2-set2: [PASS][82] -> [SKIP][83] ([Intel XE#2446]) +3 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@legacy-planes:
- shard-bmg: [PASS][84] -> [INCOMPLETE][85] ([Intel XE#2864])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-8/igt@kms_pm_rpm@legacy-planes.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-7/igt@kms_pm_rpm@legacy-planes.html
* igt@kms_pm_rpm@universal-planes:
- shard-lnl: [PASS][86] -> [DMESG-WARN][87] ([Intel XE#2042]) +1 other test dmesg-warn
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-4/igt@kms_pm_rpm@universal-planes.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-5/igt@kms_pm_rpm@universal-planes.html
* igt@kms_pm_rpm@universal-planes@plane-50:
- shard-lnl: [PASS][88] -> [DMESG-WARN][89] ([Intel XE#3184]) +1 other test dmesg-warn
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-4/igt@kms_pm_rpm@universal-planes@plane-50.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-5/igt@kms_pm_rpm@universal-planes@plane-50.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#1489]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#1489]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-3/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@fbc-psr-sprite-render:
- shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#2850] / [Intel XE#929]) +4 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_psr@fbc-psr-sprite-render.html
* igt@kms_psr@psr-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#2136] / [Intel XE#2351]) +6 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_psr@psr-dpms.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-3/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-dg2-set2: [PASS][95] -> [INCOMPLETE][96] ([Intel XE#1195] / [Intel XE#2594])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-dg2-set2: NOTRUN -> [SKIP][97] ([Intel XE#1127])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2-set2: NOTRUN -> [SKIP][98] ([Intel XE#3414])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#330])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_tv_load_detect@load-detect.html
- shard-bmg: NOTRUN -> [SKIP][100] ([Intel XE#2450])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-7/igt@kms_tv_load_detect@load-detect.html
* igt@xe_eudebug@discovery-empty:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#2905]) +3 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-1/igt@xe_eudebug@discovery-empty.html
* igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram:
- shard-dg2-set2: NOTRUN -> [SKIP][102] ([Intel XE#2905]) +6 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram.html
* igt@xe_evict@evict-mixed-many-threads-large:
- shard-dg2-set2: NOTRUN -> [TIMEOUT][103] ([Intel XE#1473])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@xe_evict@evict-mixed-many-threads-large.html
* igt@xe_exec_balancer@twice-virtual-basic:
- shard-dg2-set2: [PASS][104] -> [SKIP][105] ([Intel XE#1130]) +179 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@xe_exec_balancer@twice-virtual-basic.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_exec_balancer@twice-virtual-basic.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
- shard-bmg: NOTRUN -> [SKIP][106] ([Intel XE#2322]) +2 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-8/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-userptr-invalidate-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][107] ([Intel XE#288]) +6 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@xe_exec_fault_mode@many-userptr-invalidate-imm.html
* igt@xe_module_load@many-reload:
- shard-bmg: [PASS][108] -> [FAIL][109] ([Intel XE#2136])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-4/igt@xe_module_load@many-reload.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-8/igt@xe_module_load@many-reload.html
* igt@xe_oa@invalid-oa-exponent:
- shard-dg2-set2: NOTRUN -> [SKIP][110] ([Intel XE#2541]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@xe_oa@invalid-oa-exponent.html
* igt@xe_pat@display-vs-wb-transient:
- shard-dg2-set2: NOTRUN -> [SKIP][111] ([Intel XE#1337])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@xe_pat@display-vs-wb-transient.html
* igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][112] ([Intel XE#1173])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html
* igt@xe_vm@large-binds-2147483648:
- shard-dg2-set2: NOTRUN -> [SKIP][113] ([Intel XE#1130]) +38 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_vm@large-binds-2147483648.html
#### Possible fixes ####
* igt@core_hotunplug@hotunplug-rescan:
- shard-dg2-set2: [SKIP][114] ([Intel XE#1885]) -> [PASS][115] +1 other test pass
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@core_hotunplug@hotunplug-rescan.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@core_hotunplug@hotunplug-rescan.html
* igt@fbdev@write:
- shard-dg2-set2: [SKIP][116] ([Intel XE#2134]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@fbdev@write.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@fbdev@write.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [SKIP][118] ([Intel XE#2136] / [Intel XE#2351]) -> [PASS][119] +14 other tests pass
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-lnl: [DMESG-WARN][120] -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-lnl: [FAIL][122] ([Intel XE#2958]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-2/igt@kms_fbcon_fbt@fbc-suspend.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-dp2-hdmi-a3:
- shard-bmg: [FAIL][124] -> [PASS][125] +1 other test pass
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-dp2-hdmi-a3.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-dp2-hdmi-a3.html
* igt@kms_flip@blocking-wf_vblank:
- shard-lnl: [FAIL][126] ([Intel XE#886]) -> [PASS][127] +4 other tests pass
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-2/igt@kms_flip@blocking-wf_vblank.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-2/igt@kms_flip@blocking-wf_vblank.html
* igt@kms_flip@busy-flip:
- shard-dg2-set2: [SKIP][128] ([Intel XE#2423] / [i915#2575]) -> [PASS][129] +110 other tests pass
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_flip@busy-flip.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_flip@busy-flip.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp2:
- shard-bmg: [FAIL][130] ([Intel XE#2882]) -> [PASS][131] +2 other tests pass
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-7/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp2.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-4/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6:
- shard-dg2-set2: [FAIL][132] -> [PASS][133] +1 other test pass
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html
* igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary:
- shard-dg2-set2: [SKIP][134] ([Intel XE#2136]) -> [PASS][135] +32 other tests pass
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
* igt@kms_plane_cursor@primary:
- shard-lnl: [FAIL][136] ([Intel XE#1471] / [Intel XE#1874]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-5/igt@kms_plane_cursor@primary.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-5/igt@kms_plane_cursor@primary.html
* igt@kms_plane_cursor@primary@pipe-a-edp-1-size-256:
- shard-lnl: [FAIL][138] ([Intel XE#1471]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-5/igt@kms_plane_cursor@primary@pipe-a-edp-1-size-256.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-5/igt@kms_plane_cursor@primary@pipe-a-edp-1-size-256.html
* igt@kms_pm_dc@dc5-dpms:
- shard-lnl: [FAIL][140] ([Intel XE#718]) -> [PASS][141] +1 other test pass
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-3/igt@kms_pm_dc@dc5-dpms.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-4/igt@kms_pm_dc@dc5-dpms.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2-set2: [SKIP][142] ([Intel XE#2446]) -> [PASS][143] +5 other tests pass
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_psr@psr2-sprite-blt:
- shard-lnl: [FAIL][144] -> [PASS][145] +3 other tests pass
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-8/igt@kms_psr@psr2-sprite-blt.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-5/igt@kms_psr@psr2-sprite-blt.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-lnl: [FAIL][146] ([Intel XE#899]) -> [PASS][147] +1 other test pass
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-8/igt@kms_universal_plane@cursor-fb-leak.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_vblank@accuracy-idle:
- shard-lnl: [FAIL][148] ([Intel XE#1523]) -> [PASS][149] +1 other test pass
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-4/igt@kms_vblank@accuracy-idle.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-3/igt@kms_vblank@accuracy-idle.html
* igt@testdisplay:
- shard-dg2-set2: [SKIP][150] ([Intel XE#2423]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@testdisplay.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@testdisplay.html
* igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue:
- shard-dg2-set2: [FAIL][152] ([Intel XE#2667]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
- shard-lnl: [FAIL][154] ([Intel XE#2667]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-5/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-5/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
* igt@xe_evict@evict-large-multi-vm-cm:
- shard-dg2-set2: [FAIL][156] ([Intel XE#1600]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@xe_evict@evict-large-multi-vm-cm.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@xe_evict@evict-large-multi-vm-cm.html
* igt@xe_exec_threads@threads-bal-mixed-shared-vm-userptr-invalidate:
- shard-dg2-set2: [DMESG-WARN][158] -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@xe_exec_threads@threads-bal-mixed-shared-vm-userptr-invalidate.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@xe_exec_threads@threads-bal-mixed-shared-vm-userptr-invalidate.html
* igt@xe_oa@mmio-triggered-reports:
- shard-bmg: [FAIL][160] ([Intel XE#2249]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-7/igt@xe_oa@mmio-triggered-reports.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-3/igt@xe_oa@mmio-triggered-reports.html
- shard-lnl: [FAIL][162] ([Intel XE#2249]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-2/igt@xe_oa@mmio-triggered-reports.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-2/igt@xe_oa@mmio-triggered-reports.html
* igt@xe_pm@s3-exec-after:
- shard-bmg: [ABORT][164] -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-bmg-1/igt@xe_pm@s3-exec-after.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-bmg-3/igt@xe_pm@s3-exec-after.html
* igt@xe_pm_residency@toggle-gt-c6:
- shard-lnl: [FAIL][166] ([Intel XE#958]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-lnl-3/igt@xe_pm_residency@toggle-gt-c6.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-lnl-1/igt@xe_pm_residency@toggle-gt-c6.html
* igt@xe_vm@mmap-style-bind-userptr-one-partial:
- shard-dg2-set2: [SKIP][168] ([Intel XE#1130]) -> [PASS][169] +184 other tests pass
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_vm@mmap-style-bind-userptr-one-partial.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@xe_vm@mmap-style-bind-userptr-one-partial.html
#### Warnings ####
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2-set2: [SKIP][170] ([Intel XE#873]) -> [SKIP][171] ([Intel XE#2423] / [i915#2575])
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_async_flips@invalid-async-flip.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-dg2-set2: [FAIL][172] ([Intel XE#1426]) -> [SKIP][173] ([Intel XE#2423] / [i915#2575])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_atomic_transition@plane-all-modeset-transition.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-dg2-set2: [SKIP][174] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][175] ([Intel XE#316])
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-dg2-set2: [SKIP][176] ([Intel XE#2136]) -> [SKIP][177] ([Intel XE#316]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_big_fb@linear-32bpp-rotate-270.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-dg2-set2: [SKIP][178] ([Intel XE#1124]) -> [SKIP][179] ([Intel XE#2136] / [Intel XE#2351]) +3 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-dg2-set2: [SKIP][180] ([Intel XE#1124]) -> [SKIP][181] ([Intel XE#2136]) +11 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-dg2-set2: [SKIP][182] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][183] ([Intel XE#1124]) +5 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2-set2: [SKIP][184] ([Intel XE#2136]) -> [SKIP][185] ([Intel XE#1124]) +7 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
- shard-dg2-set2: [SKIP][186] ([Intel XE#2423] / [i915#2575]) -> [SKIP][187] ([Intel XE#367]) +5 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-dg2-set2: [SKIP][188] ([Intel XE#2191]) -> [SKIP][189] ([Intel XE#2423] / [i915#2575])
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
- shard-dg2-set2: [SKIP][190] ([Intel XE#2423] / [i915#2575]) -> [SKIP][191] ([Intel XE#2191])
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-1920x1080p:
- shard-dg2-set2: [SKIP][192] ([Intel XE#367]) -> [SKIP][193] ([Intel XE#2423] / [i915#2575]) +4 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
- shard-dg2-set2: [SKIP][194] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][195] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs:
- shard-dg2-set2: [SKIP][196] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][197] ([Intel XE#2136] / [Intel XE#2351]) +3 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
- shard-dg2-set2: [SKIP][198] -> [SKIP][199] ([Intel XE#455] / [Intel XE#787])
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [FAIL][200] ([Intel XE#616]) -> [SKIP][201] ([Intel XE#2136])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-dg2-set2: [SKIP][202] ([Intel XE#2136]) -> [SKIP][203] ([Intel XE#2907]) +1 other test skip
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
- shard-dg2-set2: [SKIP][204] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][205] ([Intel XE#2136]) +9 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-dg2-set2: [SKIP][206] ([Intel XE#2907]) -> [SKIP][207] ([Intel XE#2136])
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][208] ([Intel XE#1195]) -> [INCOMPLETE][209] ([Intel XE#1195] / [Intel XE#1727])
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][210] ([Intel XE#1195]) -> [INCOMPLETE][211] ([Intel XE#1195] / [Intel XE#3113])
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
- shard-dg2-set2: [SKIP][212] ([Intel XE#2136]) -> [SKIP][213] ([Intel XE#455] / [Intel XE#787]) +10 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-dg2-set2: [SKIP][214] ([Intel XE#314]) -> [SKIP][215] ([Intel XE#2136] / [Intel XE#2351])
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_cdclk@mode-transition-all-outputs.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_audio@dp-audio:
- shard-dg2-set2: [SKIP][216] ([Intel XE#373]) -> [SKIP][217] ([Intel XE#2423] / [i915#2575]) +12 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_chamelium_audio@dp-audio.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-dg2-set2: [SKIP][218] ([Intel XE#306]) -> [SKIP][219] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_chamelium_color@ctm-limited-range.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_hpd@vga-hpd:
- shard-dg2-set2: [SKIP][220] ([Intel XE#2423] / [i915#2575]) -> [SKIP][221] ([Intel XE#373]) +16 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_chamelium_hpd@vga-hpd.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_chamelium_hpd@vga-hpd.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2-set2: [SKIP][222] ([Intel XE#2423] / [i915#2575]) -> [FAIL][223] ([Intel XE#1178])
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_content_protection@atomic-dpms.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2-set2: [SKIP][224] ([Intel XE#307]) -> [SKIP][225] ([Intel XE#2423] / [i915#2575])
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_content_protection@dp-mst-lic-type-1.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2-set2: [SKIP][226] ([Intel XE#2423] / [i915#2575]) -> [SKIP][227] ([Intel XE#307])
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_content_protection@dp-mst-type-1.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2-set2: [FAIL][228] ([Intel XE#1178]) -> [SKIP][229] ([Intel XE#2423] / [i915#2575]) +1 other test skip
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_content_protection@legacy.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-1:
- shard-dg2-set2: [SKIP][230] ([Intel XE#2423] / [i915#2575]) -> [SKIP][231] ([Intel XE#455]) +7 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_content_protection@lic-type-1.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_content_protection@lic-type-1.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2-set2: [SKIP][232] ([Intel XE#308]) -> [SKIP][233] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_cursor_crc@cursor-onscreen-512x512.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-dg2-set2: [SKIP][234] ([Intel XE#455]) -> [SKIP][235] ([Intel XE#2423] / [i915#2575]) +8 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-max-size.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg2-set2: [SKIP][236] ([Intel XE#323]) -> [SKIP][237] ([Intel XE#2423] / [i915#2575])
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2-set2: [SKIP][238] ([Intel XE#2423] / [i915#2575]) -> [SKIP][239] ([Intel XE#323]) +2 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@single-bo:
- shard-dg2-set2: [INCOMPLETE][240] ([Intel XE#1195] / [Intel XE#3226]) -> [SKIP][241] ([Intel XE#2423] / [i915#2575])
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_cursor_legacy@single-bo.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_cursor_legacy@single-bo.html
* igt@kms_cursor_legacy@torture-bo:
- shard-dg2-set2: [SKIP][242] ([Intel XE#2423] / [i915#2575]) -> [DMESG-WARN][243] ([Intel XE#3184])
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_cursor_legacy@torture-bo.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_cursor_legacy@torture-bo.html
* igt@kms_dsc@dsc-basic:
- shard-dg2-set2: [SKIP][244] ([Intel XE#455]) -> [SKIP][245] ([Intel XE#2351])
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_dsc@dsc-basic.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2-set2: [SKIP][246] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][247] ([Intel XE#455]) +1 other test skip
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_dsc@dsc-with-bpc-formats.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2-set2: [SKIP][248] ([Intel XE#1137]) -> [SKIP][249] ([Intel XE#2423] / [i915#2575])
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_feature_discovery@dp-mst.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-dg2-set2: [SKIP][250] ([Intel XE#2423] / [i915#2575]) -> [SKIP][251] ([Intel XE#1135]) +1 other test skip
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_feature_discovery@psr1.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2-set2: [FAIL][252] ([Intel XE#301]) -> [SKIP][253] ([Intel XE#2423] / [i915#2575]) +1 other test skip
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-dg2-set2: [ABORT][254] ([Intel XE#2625]) -> [SKIP][255] ([Intel XE#2423] / [i915#2575])
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_flip@flip-vs-suspend-interruptible.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
- shard-dg2-set2: [SKIP][256] ([Intel XE#455]) -> [SKIP][257] ([Intel XE#2136] / [Intel XE#2351])
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
- shard-dg2-set2: [SKIP][258] ([Intel XE#455]) -> [SKIP][259] ([Intel XE#2136]) +4 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-dg2-set2: [SKIP][260] ([Intel XE#2136]) -> [SKIP][261] ([Intel XE#455]) +5 other tests skip
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-dg2-set2: [SKIP][262] ([i915#5274]) -> [SKIP][263] ([Intel XE#2423] / [i915#2575])
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_force_connector_basic@prune-stale-modes.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
- shard-dg2-set2: [SKIP][264] ([Intel XE#2136]) -> [SKIP][265] ([Intel XE#651]) +27 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
- shard-dg2-set2: [SKIP][266] ([Intel XE#651]) -> [SKIP][267] ([Intel XE#2136] / [Intel XE#2351]) +12 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt:
- shard-dg2-set2: [SKIP][268] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][269] ([Intel XE#651]) +7 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt.html
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2-set2: [SKIP][270] ([Intel XE#651]) -> [SKIP][271] ([Intel XE#2136]) +24 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
- shard-dg2-set2: [SKIP][272] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][273] ([Intel XE#658])
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
- shard-dg2-set2: [SKIP][274] ([Intel XE#653]) -> [SKIP][275] ([Intel XE#2136]) +25 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2-set2: [SKIP][276] ([Intel XE#658]) -> [SKIP][277] ([Intel XE#2136] / [Intel XE#2351])
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-dg2-set2: [SKIP][278] ([Intel XE#2136]) -> [SKIP][279] ([Intel XE#1158])
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2-set2: [SKIP][280] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][281] ([Intel XE#653]) +11 other tests skip
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: [SKIP][282] ([Intel XE#653]) -> [SKIP][283] ([Intel XE#2136] / [Intel XE#2351]) +8 other tests skip
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-dg2-set2: [SKIP][284] ([Intel XE#2136]) -> [SKIP][285] ([Intel XE#653]) +25 other tests skip
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-slowdraw.html
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2-set2: [SKIP][286] ([Intel XE#2423] / [i915#2575]) -> [SKIP][287] ([Intel XE#605])
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_getfb@getfb-reject-ccs.html
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2-set2: [FAIL][288] ([Intel XE#3312] / [Intel XE#3404]) -> [SKIP][289] ([Intel XE#2423] / [i915#2575])
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_hdr@brightness-with-hdr.html
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-dg2-set2: [SKIP][290] ([Intel XE#346]) -> [SKIP][291] ([Intel XE#2136])
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_joiner@invalid-modeset-big-joiner.html
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-dg2-set2: [SKIP][292] ([Intel XE#2136]) -> [SKIP][293] ([Intel XE#2925])
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-dg2-set2: [SKIP][294] ([Intel XE#2136]) -> [SKIP][295] ([Intel XE#2927]) +1 other test skip
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_joiner@invalid-modeset-ultra-joiner.html
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2-set2: [SKIP][296] ([Intel XE#455]) -> [FAIL][297] ([Intel XE#361])
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_plane_scaling@intel-max-src-size.html
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
- shard-dg2-set2: [SKIP][298] ([Intel XE#2423] / [i915#2575]) -> [SKIP][299] ([Intel XE#2763] / [Intel XE#455]) +2 other tests skip
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
- shard-dg2-set2: [SKIP][300] ([Intel XE#2763] / [Intel XE#455]) -> [SKIP][301] ([Intel XE#2423] / [i915#2575]) +4 other tests skip
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-dg2-set2: [SKIP][302] ([Intel XE#870]) -> [SKIP][303] ([Intel XE#2136])
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_pm_backlight@fade-with-suspend.html
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2-set2: [SKIP][304] ([Intel XE#1122]) -> [SKIP][305] ([Intel XE#2136] / [Intel XE#2351])
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_pm_dc@dc3co-vpb-simulation.html
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-psr:
- shard-dg2-set2: [SKIP][306] ([Intel XE#2136]) -> [SKIP][307] ([Intel XE#1129])
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_pm_dc@dc5-psr.html
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2-set2: [SKIP][308] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][309] ([Intel XE#1129])
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_pm_dc@dc6-psr.html
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
- shard-dg2-set2: [SKIP][310] ([Intel XE#2136]) -> [SKIP][311] ([Intel XE#1489]) +10 other tests skip
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
- shard-dg2-set2: [SKIP][312] ([Intel XE#1489]) -> [SKIP][313] ([Intel XE#2136]) +8 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
[313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2-set2: [SKIP][314] ([Intel XE#2136]) -> [SKIP][315] ([Intel XE#1122]) +1 other test skip
[314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_psr2_su@page_flip-nv12.html
[315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr-no-drrs:
- shard-dg2-set2: [SKIP][316] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][317] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_psr@fbc-psr-no-drrs.html
[317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_psr@fbc-psr-no-drrs.html
* igt@kms_psr@fbc-psr2-cursor-blt:
- shard-dg2-set2: [SKIP][318] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][319] ([Intel XE#2136] / [Intel XE#2351]) +3 other tests skip
[318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_psr@fbc-psr2-cursor-blt.html
[319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_psr@fbc-psr2-cursor-blt.html
* igt@kms_psr@fbc-psr2-sprite-plane-move:
- shard-dg2-set2: [SKIP][320] ([Intel XE#2136]) -> [SKIP][321] ([Intel XE#2850] / [Intel XE#929]) +11 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-move.html
[321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-435/igt@kms_psr@fbc-psr2-sprite-plane-move.html
* igt@kms_psr@psr2-sprite-plane-move:
- shard-dg2-set2: [SKIP][322] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][323] ([Intel XE#2136]) +13 other tests skip
[322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@kms_psr@psr2-sprite-plane-move.html
[323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_psr@psr2-sprite-plane-move.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2-set2: [SKIP][324] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][325] ([Intel XE#2939])
[324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2-set2: [SKIP][326] ([Intel XE#2939]) -> [SKIP][327] ([Intel XE#2136])
[326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2-set2: [SKIP][328] ([Intel XE#2423] / [i915#2575]) -> [SKIP][329] ([Intel XE#3414]) +2 other tests skip
[328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_rotation_crc@bad-pixel-format.html
[329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg2-set2: [SKIP][330] ([Intel XE#1127]) -> [SKIP][331] ([Intel XE#2423] / [i915#2575])
[330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
[331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg2-set2: [SKIP][332] ([Intel XE#2423] / [i915#2575]) -> [SKIP][333] ([Intel XE#1127])
[332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
[333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2-set2: [SKIP][334] ([Intel XE#3414]) -> [SKIP][335] ([Intel XE#2423] / [i915#2575]) +1 other test skip
[334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-433/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
[335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][336] ([Intel XE#362]) -> [SKIP][337] ([Intel XE#1500])
[336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@lobf:
- shard-dg2-set2: [SKIP][338] ([Intel XE#2423] / [i915#2575]) -> [SKIP][339] ([Intel XE#2168])
[338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_vrr@lobf.html
[339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@kms_vrr@lobf.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2-set2: [SKIP][340] ([Intel XE#756]) -> [SKIP][341] ([Intel XE#2423] / [i915#2575])
[340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@kms_writeback@writeback-check-output.html
[341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg2-set2: [SKIP][342] ([Intel XE#2423] / [i915#2575]) -> [SKIP][343] ([Intel XE#756])
[342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@kms_writeback@writeback-invalid-parameters.html
[343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@kms_writeback@writeback-invalid-parameters.html
* igt@xe_copy_basic@mem-set-linear-0xfffe:
- shard-dg2-set2: [SKIP][344] ([Intel XE#1130]) -> [SKIP][345] ([Intel XE#1126]) +1 other test skip
[344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_copy_basic@mem-set-linear-0xfffe.html
[345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@xe_copy_basic@mem-set-linear-0xfffe.html
* igt@xe_eudebug@basic-vm-access-parameters:
- shard-dg2-set2: [SKIP][346] ([Intel XE#1130]) -> [SKIP][347] ([Intel XE#2905]) +13 other tests skip
[346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_eudebug@basic-vm-access-parameters.html
[347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@xe_eudebug@basic-vm-access-parameters.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate-race:
- shard-dg2-set2: [SKIP][348] ([Intel XE#288]) -> [SKIP][349] ([Intel XE#1130]) +27 other tests skip
[348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html
[349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
- shard-dg2-set2: [SKIP][350] ([Intel XE#1130]) -> [SKIP][351] ([Intel XE#288]) +35 other tests skip
[350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html
[351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html
* igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
- shard-dg2-set2: [SKIP][352] ([Intel XE#2360]) -> [SKIP][353] ([Intel XE#1130]) +1 other test skip
[352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
[353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-dg2-set2: [SKIP][354] ([Intel XE#1130]) -> [SKIP][355] ([Intel XE#2360])
[354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
[355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip:
- shard-dg2-set2: [SKIP][356] ([Intel XE#2905]) -> [SKIP][357] ([Intel XE#1130]) +9 other tests skip
[356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
[357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
* igt@xe_mmap@small-bar:
- shard-dg2-set2: [SKIP][358] ([Intel XE#1130]) -> [SKIP][359] ([Intel XE#512])
[358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_mmap@small-bar.html
[359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@xe_mmap@small-bar.html
* igt@xe_oa@invalid-create-userspace-config:
- shard-dg2-set2: [SKIP][360] ([Intel XE#2541]) -> [SKIP][361] ([Intel XE#1130]) +8 other tests skip
[360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@xe_oa@invalid-create-userspace-config.html
[361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_oa@invalid-create-userspace-config.html
* igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
- shard-dg2-set2: [SKIP][362] ([Intel XE#1130]) -> [SKIP][363] ([Intel XE#2541]) +7 other tests skip
[362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
[363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
* igt@xe_peer2peer@write:
- shard-dg2-set2: [SKIP][364] ([Intel XE#1061]) -> [FAIL][365] ([Intel XE#1173])
[364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_peer2peer@write.html
[365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-466/igt@xe_peer2peer@write.html
* igt@xe_pm@d3cold-basic-exec:
- shard-dg2-set2: [SKIP][366] ([Intel XE#1130]) -> [SKIP][367] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
[366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_pm@d3cold-basic-exec.html
[367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-463/igt@xe_pm@d3cold-basic-exec.html
* igt@xe_pm@d3cold-mocs:
- shard-dg2-set2: [SKIP][368] ([Intel XE#2284]) -> [SKIP][369] ([Intel XE#1130])
[368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@xe_pm@d3cold-mocs.html
[369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_pm@d3cold-mocs.html
* igt@xe_pm@s2idle-d3cold-basic-exec:
- shard-dg2-set2: [SKIP][370] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][371] ([Intel XE#1130]) +2 other tests skip
[370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@xe_pm@s2idle-d3cold-basic-exec.html
[371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_pm@s2idle-d3cold-basic-exec.html
* igt@xe_pm@vram-d3cold-threshold:
- shard-dg2-set2: [SKIP][372] ([Intel XE#1130]) -> [SKIP][373] ([Intel XE#579])
[372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_pm@vram-d3cold-threshold.html
[373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@xe_pm@vram-d3cold-threshold.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-dg2-set2: [SKIP][374] ([Intel XE#944]) -> [SKIP][375] ([Intel XE#1130]) +3 other tests skip
[374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-463/igt@xe_query@multigpu-query-invalid-cs-cycles.html
[375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_query@multigpu-query-topology:
- shard-dg2-set2: [SKIP][376] ([Intel XE#1130]) -> [SKIP][377] ([Intel XE#944]) +4 other tests skip
[376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_query@multigpu-query-topology.html
[377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-464/igt@xe_query@multigpu-query-topology.html
* igt@xe_sriov_flr@flr-vf1-clear:
- shard-dg2-set2: [SKIP][378] ([Intel XE#3342]) -> [SKIP][379] ([Intel XE#1130])
[378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-435/igt@xe_sriov_flr@flr-vf1-clear.html
[379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_sriov_flr@flr-vf1-clear.html
* igt@xe_tlb@basic-tlb:
- shard-dg2-set2: [FAIL][380] ([Intel XE#2922]) -> [SKIP][381] ([Intel XE#1130])
[380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-466/igt@xe_tlb@basic-tlb.html
[381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_tlb@basic-tlb.html
* igt@xe_wedged@basic-wedged:
- shard-dg2-set2: [SKIP][382] ([Intel XE#1130]) -> [DMESG-WARN][383] ([Intel XE#2919])
[382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-434/igt@xe_wedged@basic-wedged.html
[383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-433/igt@xe_wedged@basic-wedged.html
* igt@xe_wedged@wedged-at-any-timeout:
- shard-dg2-set2: [ABORT][384] ([Intel XE#3421]) -> [SKIP][385] ([Intel XE#1130])
[384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8107/shard-dg2-464/igt@xe_wedged@wedged-at-any-timeout.html
[385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/shard-dg2-434/igt@xe_wedged@wedged-at-any-timeout.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
[Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
[Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
[Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
[Intel XE#1152]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1152
[Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
[Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
[Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
[Intel XE#1454]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1454
[Intel XE#1471]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1471
[Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1523]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1523
[Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
[Intel XE#2042]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2042
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
[Intel XE#2141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2141
[Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
[Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
[Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
[Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
[Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
[Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2577]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2577
[Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
[Intel XE#2625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2625
[Intel XE#2667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2667
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2864]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2864
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2919]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2919
[Intel XE#2922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2922
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
[Intel XE#2958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2958
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3184]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3184
[Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3312
[Intel XE#3339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3339
[Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
[Intel XE#3403]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3403
[Intel XE#3404]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3404
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3421
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
[Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
[Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
[Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
[Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
[Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
Build changes
-------------
* IGT: IGT_8107 -> IGTPW_12095
* Linux: xe-2221-169c7cd31a373ed31054abb423981856eb5fb119 -> xe-2222-9e35defd02728ad7c06347830022506488668c21
IGTPW_12095: bc97f1ed54b4c60b1681c0f5e02ca07f9cfba1cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8107: 0362b0deec80daaecdfa3dd0676dcabb6f14bd9c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2221-169c7cd31a373ed31054abb423981856eb5fb119: 169c7cd31a373ed31054abb423981856eb5fb119
xe-2222-9e35defd02728ad7c06347830022506488668c21: 9e35defd02728ad7c06347830022506488668c21
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12095/index.html
[-- Attachment #2: Type: text/html, Size: 118395 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-13 17:52 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
@ 2024-11-28 8:24 ` Peter Senna Tschudin
2024-12-04 9:09 ` Zbigniew Kempczyński
1 sibling, 0 replies; 18+ messages in thread
From: Peter Senna Tschudin @ 2024-11-28 8:24 UTC (permalink / raw)
To: Pravalika Gurram, lucas.demarchi, igt-dev
I did compile and test using igt-runner and the following test-list
with and without the two patches in this series. I found no issues.
igt@xe_drm_fdinfo
igt@xe_spin_batch
igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff
igt@core_hotunplug@hotrebind
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt
igt@xe_prime_self_import@basic-with_one_bo
igt@xe_exec_basic@many-basic
igt@kms_mmap_write_crc@main
igt@kms_flip@2x-busy-flip
igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen
igt@kms_addfb_basic@invalid-set-prop-any
igt@xe_sysfs_scheduler@timeslice_duration_us-invalid
igt@kms_frontbuffer_tracking@fbcpsr-tiling-4
igt@kms_cursor_edge_walk@64x64-left-edge
igt@xe_module_load@reload-no-display
On 13.11.2024 18:52, Pravalika Gurram wrote:
> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
> to xe spin lib to avoid code redundancy.
>
> v2: use allocator based on developer preference.
> change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
> v3: Integrate spin_ctx to xe_cork
> use designated structure initialization for optional arg [Lucas]
>
> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
Tested-by: Peter Senna Tschudin <peter.senna@linux.intel.com>
> ---
> lib/xe/xe_spin.c | 116 +++++++++++++++++++++
> lib/xe/xe_spin.h | 40 ++++++--
> tests/intel/xe_drm_fdinfo.c | 200 +++++++-----------------------------
> 3 files changed, 183 insertions(+), 173 deletions(-)
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 3adacc3a8..41679d9c6 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -292,6 +292,122 @@ void xe_spin_free(int fd, struct igt_spin *spin)
> free(spin);
> }
>
> +struct xe_cork *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> + uint32_t vm, uint16_t width, uint16_t num_placements,
> + struct xe_cork_opts *opts)
> +{
> + struct xe_cork *ctx = calloc(1, sizeof(*ctx));
> +
> + igt_assert(width && num_placements &&
> + (width == 1 || num_placements == 1));
> + igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> +
> + ctx->class = hwe->engine_class;
> + ctx->width = width;
> + ctx->num_placements = num_placements;
> + ctx->vm = vm;
> +
> + ctx->exec.num_batch_buffer = width;
> + ctx->exec.num_syncs = 2;
> + ctx->exec.syncs = to_user_pointer(ctx->sync);
> +
> + ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[0].handle = syncobj_create(fd, 0);
> +
> + ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[1].handle = syncobj_create(fd, 0);
> +
> + ctx->bo_size = sizeof(struct xe_spin);
> + ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> + ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> + vram_if_possible(fd, hwe->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + if (opts->ahnd) {
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = intel_allocator_alloc_with_strategy(opts->ahnd,
> + ctx->bo, ctx->bo_size, 0,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
> + } else {
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> + }
> +
> + ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> +
> + igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> + hwe, 0, &ctx->exec_queue), 0);
> +
> + xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> + ctx->sync, 1);
> +
> + return ctx;
> +}
> +
> +void xe_spin_sync_start(int fd, struct xe_cork *ctx)
> +{
> + if (!ctx)
> + return;
> +
> + ctx->spin_opts.addr = ctx->addr[0];
> + ctx->spin_opts.write_timestamp = true;
> + ctx->spin_opts.preempt = true;
> + xe_spin_init(ctx->spin, &ctx->spin_opts);
> +
> + /* re-use sync[0] for exec */
> + ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> +
> + ctx->exec.exec_queue_id = ctx->exec_queue;
> +
> + if (ctx->width > 1)
> + ctx->exec.address = to_user_pointer(ctx->addr);
> + else
> + ctx->exec.address = ctx->addr[0];
> +
> + xe_exec(fd, &ctx->exec);
> +
> + xe_spin_wait_started(ctx->spin);
> + igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> +
> + igt_debug("%d: spinner started\n", ctx->class);
> +}
> +
> +void xe_spin_sync_end(int fd, struct xe_cork *ctx)
> +{
> + if (!ctx || ctx->ended)
> + return;
> +
> + xe_spin_end(ctx->spin);
> +
> + igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + ctx->ended = true;
> + igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
> + ctx->spin->timestamp);
> +}
> +
> +void xe_spin_ctx_destroy(int fd, struct xe_cork *ctx)
> +{
> + if (!ctx)
> + return;
> +
> + syncobj_destroy(fd, ctx->sync[0].handle);
> + syncobj_destroy(fd, ctx->sync[1].handle);
> + xe_exec_queue_destroy(fd, ctx->exec_queue);
> +
> + munmap(ctx->spin, ctx->bo_size);
> + gem_close(fd, ctx->bo);
> +
> + free(ctx);
> +}
> +
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork)
> {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index d65adb05c..21488b071 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -32,6 +32,10 @@ struct xe_spin_opts {
> bool write_timestamp;
> };
>
> +struct xe_cork_opts {
> + uint64_t ahnd;
> +};
> +
> /* Mapped GPU object */
> struct xe_spin {
> uint32_t batch[128];
> @@ -43,9 +47,35 @@ struct xe_spin {
> uint32_t timestamp;
> };
>
> +struct xe_cork {
> + struct xe_spin *spin;
> + int fd;
> + uint32_t vm;
> + uint32_t bo;
> + uint32_t exec_queue;
> + uint32_t syncobj;
> + uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> + struct drm_xe_sync sync[2];
> + struct drm_xe_exec exec;
> + size_t bo_size;
> + struct xe_spin_opts spin_opts;
> + bool ended;
> + uint16_t class;
> + uint16_t width;
> + uint16_t num_placements;
> +};
> +
> igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
> void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
> +struct xe_cork *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> + uint16_t width, uint16_t num_placements, struct xe_cork_opts *opts);
> +void xe_spin_ctx_destroy(int fd, struct xe_cork *ctx);
> +
> +#define xe_spin_ctx_init_opts(fd, hwe, vm, width, num_placements, ...) \
> + xe_spin_ctx_init(fd, hwe, vm, width, num_placements, \
> + &((struct xe_cork_opts){__VA_ARGS__}))
>
> #define xe_spin_init_opts(fd, ...) \
> xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
> @@ -55,15 +85,9 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> void xe_spin_wait_started(struct xe_spin *spin);
> void xe_spin_end(struct xe_spin *spin);
> void xe_spin_free(int fd, struct igt_spin *spin);
> +void xe_spin_sync_start(int fd, struct xe_cork *ctx);
> +void xe_spin_sync_end(int fd, struct xe_cork *ctx);
>
> -struct xe_cork {
> - struct xe_spin *spin;
> - int fd;
> - uint32_t vm;
> - uint32_t bo;
> - uint32_t exec_queue;
> - uint32_t syncobj;
> -};
>
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork);
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 5fd7c0416..d7d392000 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
> igt_require(info.num_engines);
> }
>
> -struct spin_ctx {
> - uint32_t vm;
> - uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> - struct drm_xe_sync sync[2];
> - struct drm_xe_exec exec;
> - uint32_t exec_queue;
> - size_t bo_size;
> - uint32_t bo;
> - struct xe_spin *spin;
> - struct xe_spin_opts spin_opts;
> - bool ended;
> - uint16_t class;
> - uint16_t width;
> - uint16_t num_placements;
> -};
> -
> -static struct spin_ctx *
> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> - uint16_t width, uint16_t num_placements)
> -{
> - struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> -
> - igt_assert(width && num_placements &&
> - (width == 1 || num_placements == 1));
> - igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> -
> - ctx->class = hwe->engine_class;
> - ctx->width = width;
> - ctx->num_placements = num_placements;
> - ctx->vm = vm;
> -
> - for (unsigned int i = 0; i < width; i++)
> - ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> -
> - ctx->exec.num_batch_buffer = width;
> - ctx->exec.num_syncs = 2;
> - ctx->exec.syncs = to_user_pointer(ctx->sync);
> -
> - ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[0].handle = syncobj_create(fd, 0);
> -
> - ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[1].handle = syncobj_create(fd, 0);
> -
> - ctx->bo_size = sizeof(struct xe_spin);
> - ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> - ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> - vram_if_possible(fd, hwe->gt_id),
> - DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> - ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> -
> - igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> - hwe, 0, &ctx->exec_queue), 0);
> -
> - xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> - ctx->sync, 1);
> -
> - return ctx;
> -}
> -
> -static void
> -spin_sync_start(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - ctx->spin_opts.addr = ctx->addr[0];
> - ctx->spin_opts.write_timestamp = true;
> - ctx->spin_opts.preempt = true;
> - xe_spin_init(ctx->spin, &ctx->spin_opts);
> -
> - /* re-use sync[0] for exec */
> - ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> -
> - ctx->exec.exec_queue_id = ctx->exec_queue;
> -
> - if (ctx->width > 1)
> - ctx->exec.address = to_user_pointer(ctx->addr);
> - else
> - ctx->exec.address = ctx->addr[0];
> -
> - xe_exec(fd, &ctx->exec);
> -
> - xe_spin_wait_started(ctx->spin);
> - igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> -
> - igt_debug("%s: spinner started\n", engine_map[ctx->class]);
> -}
> -
> -static void
> -spin_sync_end(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx || ctx->ended)
> - return;
> -
> - xe_spin_end(ctx->spin);
> -
> - igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> - xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->ended = true;
> - igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
> - ctx->spin->timestamp);
> -}
> -
> -static void
> -spin_ctx_destroy(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - syncobj_destroy(fd, ctx->sync[0].handle);
> - syncobj_destroy(fd, ctx->sync[1].handle);
> - xe_exec_queue_destroy(fd, ctx->exec_queue);
> -
> - munmap(ctx->spin, ctx->bo_size);
> - gem_close(fd, ctx->bo);
> -
> - free(ctx);
> -}
> -
> static void
> check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> int class, int width, enum expected_load expected_load)
> @@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> {
> struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> enum expected_load expected_load;
> uint32_t vm;
> int new_fd;
> @@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu1[0]);
> @@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu2[0]);
> if (flags & TEST_ISOLATION)
> @@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> close(new_fd);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> uint32_t vm;
>
> vm = xe_vm_create(fd, 0, 0);
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
>
> /* destroy queue before sampling again */
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> read_engine_cycles(fd, pceu2);
>
> @@ -610,18 +483,17 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> uint32_t vm;
> int class;
>
> vm = xe_vm_create(fd, 0, 0);
> -
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -631,8 +503,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> check_results(pceu1, pceu2, class, 1, expected_load);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -641,7 +513,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> + struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> struct drm_xe_engine_class_instance *_hwe;
> uint32_t vm;
> int class;
> @@ -654,15 +526,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>
> if (_class == hwe->engine_class || ctx[_class])
> continue;
> -
> - ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[_class]);
> + ctx[_class] = xe_spin_ctx_init_opts(fd, _hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[_class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -673,8 +544,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> continue;
>
> check_results(pceu1, pceu2, class, 1, expected_load);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -685,7 +556,7 @@ utilization_all_full_load(int fd)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> + struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> struct drm_xe_engine_class_instance *hwe;
> uint32_t vm;
> int class;
> @@ -697,15 +568,14 @@ utilization_all_full_load(int fd)
> class = hwe->engine_class;
> if (ctx[class])
> continue;
> -
> - ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[class]);
> + ctx[class] = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -713,8 +583,8 @@ utilization_all_full_load(int fd)
> continue;
>
> check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -741,7 +611,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
> struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> enum expected_load expected_load;
> int fd_spill, num_placements;
> uint32_t vm;
> @@ -767,8 +637,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, eci, vm, width, num_placements);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu[0]);
> @@ -777,7 +647,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu[1]);
> if (flags & TEST_ISOLATION)
> @@ -797,8 +667,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
> close(fd_spill);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> xe_vm_destroy(fd, vm);
> }
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check
2024-11-13 17:52 ` [PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
@ 2024-11-28 8:26 ` Peter Senna Tschudin
0 siblings, 0 replies; 18+ messages in thread
From: Peter Senna Tschudin @ 2024-11-28 8:26 UTC (permalink / raw)
To: Pravalika Gurram, lucas.demarchi, igt-dev; +Cc: Zbigniew Kempczyński
I did compile and test using igt-runner and the following test-list
with and without the two patches in this series. I found no issues.
igt@xe_drm_fdinfo
igt@xe_spin_batch
igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff
igt@core_hotunplug@hotrebind
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt
igt@xe_prime_self_import@basic-with_one_bo
igt@xe_exec_basic@many-basic
igt@kms_mmap_write_crc@main
igt@kms_flip@2x-busy-flip
igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen
igt@kms_addfb_basic@invalid-set-prop-any
igt@xe_sysfs_scheduler@timeslice_duration_us-invalid
igt@kms_frontbuffer_tracking@fbcpsr-tiling-4
igt@kms_cursor_edge_walk@64x64-left-edge
igt@xe_module_load@reload-no-display
On 13.11.2024 18:52, Pravalika Gurram wrote:
> check the ctx_timestamp register post gt reset for each engine.
>
> V2: move spinner code to lib avoid code redundancy
> use flags to maintain the readability
> use READ_ONCE to prevent compiler from optimizing it out [Lucas]
>
> V3: call allocator in run_spinner and pass to spinner ctx [Zbigniew]
> v4: Integrate spin_ctx to xe_cork [Lucas]
>
> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Tested-by: Peter Senna Tschudin <peter.senna@linux.intel.com>
> ---
> tests/intel/xe_spin_batch.c | 121 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 121 insertions(+)
>
> diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
> index 9314e229e..9a5cdb830 100644
> --- a/tests/intel/xe_spin_batch.c
> +++ b/tests/intel/xe_spin_batch.c
> @@ -309,6 +309,121 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
> put_ahnd(ahnd);
> }
>
> +static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
> + bool hang)
> +{
> + uint64_t ahnd, bb_size, bb_addr;
> + uint32_t vm, exec_queue, bb;
> +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
> + struct drm_xe_sync syncobj = {
> + .type = DRM_XE_SYNC_TYPE_USER_FENCE,
> + .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> + .timeline_value = USER_FENCE_VALUE,
> + };
> +
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 1,
> + .syncs = to_user_pointer(&syncobj),
> + };
> + struct {
> + uint32_t batch[16];
> + uint64_t pad;
> + uint32_t data;
> + uint64_t vm_sync;
> + uint64_t exec_sync;
> + } *data;
> + uint64_t batch_offset, batch_addr, sdi_offset, sdi_addr;
> + int64_t timeout = NSEC_PER_SEC;
> + int i, ret;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + vm = xe_vm_create(fd, 0, 0);
> + exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> + bb_size = xe_bb_size(fd, sizeof(*data));
> + bb = xe_bo_create(fd, vm, bb_size, vram_if_possible(fd, eci->gt_id), 0);
> + bb_addr = intel_allocator_alloc_with_strategy(ahnd, bb, bb_size, 0,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
> + data = xe_bo_map(fd, bb, bb_size);
> + syncobj.addr = to_user_pointer(&data->vm_sync);
> + xe_vm_bind_async(fd, vm, 0, bb, 0, bb_addr, bb_size, &syncobj, 1);
> + xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
> +
> + batch_offset = (char *)&data->batch - (char *)data;
> + batch_addr = bb_addr + batch_offset;
> + sdi_offset = (char *)&data->data - (char *)data;
> + sdi_addr = bb_addr + sdi_offset;
> +
> + i = 0;
> +
> + data->batch[i++] = MI_STORE_DWORD_IMM_GEN4;
> + data->batch[i++] = sdi_addr;
> + data->batch[i++] = sdi_addr >> 32;
> + data->batch[i++] = 0;
> + if (!hang)
> + data->batch[i++] = MI_BATCH_BUFFER_END;
> + igt_assert(i <= ARRAY_SIZE(data->batch));
> +
> + syncobj.addr = bb_addr + (char *)&data->exec_sync - (char *)data;
> + exec.exec_queue_id = exec_queue;
> + exec.address = batch_addr;
> + xe_exec(fd, &exec);
> + ret = __xe_wait_ufence(fd, &data->exec_sync, USER_FENCE_VALUE, 0, &timeout);
> + igt_assert(hang ? ret < 0 : ret == 0);
> +
> + munmap(data, bb_size);
> + gem_close(fd, bb);
> +
> + xe_exec_queue_destroy(fd, exec_queue);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
> +
> +static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> + struct xe_cork *ctx = NULL;
> + uint32_t vm;
> + uint32_t ts_1, ts_2;
> + uint64_t ahnd;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + ctx = xe_spin_ctx_init_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
> + xe_spin_sync_start(fd, ctx);
> +
> + /* Collect and check timestamps before stopping the spinner */
> + usleep(50000);
> + ts_1 = READ_ONCE(ctx->spin->timestamp);
> + usleep(50000);
> + ts_2 = READ_ONCE(ctx->spin->timestamp);
> + igt_assert_neq_u32(ts_1, ts_2);
> +
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> +
> + xe_vm_destroy(fd, vm);
> + put_ahnd(ahnd);
> +}
> +
> +#define TRUE 1
> +#define FALSE 0
> +/**
> + * SUBTEST: spin-timestamp-check
> + * Description: Intiate gt reset then check the timestamp register for each engine.
> + * Test category: functionality test
> + */
> +static void xe_spin_timestamp_check(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> + /*sanity check for exec submission*/
> + exec_store(fd, eci, FALSE);
> +
> + exec_store(fd, eci, TRUE);
> +
> + run_spinner(fd, eci);
> +}
> +
> igt_main
> {
> struct drm_xe_engine_class_instance *hwe;
> @@ -343,6 +458,12 @@ igt_main
> xe_for_each_engine_class(class)
> xe_spin_fixed_duration(fd, gt, class, SPIN_FIX_DURATION_PREEMPT);
>
> + igt_subtest_with_dynamic("spin-timestamp-check")
> + xe_for_each_engine(fd, hwe) {
> + igt_dynamic_f("engine-%s", xe_engine_class_string(hwe->engine_class))
> + xe_spin_timestamp_check(fd, hwe);
> + }
> +
> igt_fixture
> drm_close_driver(fd);
> }
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib
2024-11-13 17:52 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
2024-11-28 8:24 ` Peter Senna Tschudin
@ 2024-12-04 9:09 ` Zbigniew Kempczyński
1 sibling, 0 replies; 18+ messages in thread
From: Zbigniew Kempczyński @ 2024-12-04 9:09 UTC (permalink / raw)
To: Pravalika Gurram; +Cc: lucas.demarchi, igt-dev
On Wed, Nov 13, 2024 at 11:22:06PM +0530, Pravalika Gurram wrote:
> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
> to xe spin lib to avoid code redundancy.
>
> v2: use allocator based on developer preference.
> change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
> v3: Integrate spin_ctx to xe_cork
> use designated structure initialization for optional arg [Lucas]
>
> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
In the past I've also kept versioning in the commit message but now I
think better is to just keep it under three lines so finally it won't
be a part of the commit. I mean commit shouldn't be polluted with
history of the patch. If someone will be interested link to lore may
be added by b4 on merge time.
> ---
> lib/xe/xe_spin.c | 116 +++++++++++++++++++++
> lib/xe/xe_spin.h | 40 ++++++--
> tests/intel/xe_drm_fdinfo.c | 200 +++++++-----------------------------
> 3 files changed, 183 insertions(+), 173 deletions(-)
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 3adacc3a8..41679d9c6 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -292,6 +292,122 @@ void xe_spin_free(int fd, struct igt_spin *spin)
> free(spin);
> }
>
> +struct xe_cork *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> + uint32_t vm, uint16_t width, uint16_t num_placements,
> + struct xe_cork_opts *opts)
I think this should be prefixed by xe_cork_...() as you're returning
xe_cork structure. And likely I would rename this to xe_cork_create()
as you're allocating the memory inside the function.
I've roughly took a look to xe_vm.c xe_cork usage and it seems it might
be replaced by this code. Only some options should be passed in
xe_cork_opts (write_timestamp, preempt, ahnd).
> +{
> + struct xe_cork *ctx = calloc(1, sizeof(*ctx));
> +
> + igt_assert(width && num_placements &&
> + (width == 1 || num_placements == 1));
> + igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> +
> + ctx->class = hwe->engine_class;
> + ctx->width = width;
> + ctx->num_placements = num_placements;
> + ctx->vm = vm;
You should collect ahnd as well to remove offset from the allocator
on the spinner completion.
> +
> + ctx->exec.num_batch_buffer = width;
> + ctx->exec.num_syncs = 2;
> + ctx->exec.syncs = to_user_pointer(ctx->sync);
> +
> + ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[0].handle = syncobj_create(fd, 0);
> +
> + ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> + ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> + ctx->sync[1].handle = syncobj_create(fd, 0);
> +
> + ctx->bo_size = sizeof(struct xe_spin);
> + ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> + ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> + vram_if_possible(fd, hwe->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + if (opts->ahnd) {
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = intel_allocator_alloc_with_strategy(opts->ahnd,
> + ctx->bo, ctx->bo_size, 0,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
> + } else {
> + for (unsigned int i = 0; i < width; i++)
> + ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> + }
> +
> + ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> +
> + igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> + hwe, 0, &ctx->exec_queue), 0);
> +
> + xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> + ctx->sync, 1);
> +
> + return ctx;
> +}
> +
> +void xe_spin_sync_start(int fd, struct xe_cork *ctx)
xe_cork_sync_start() or xe_cork_start() if you'll be able to replace
xe_vm.c xe_cork current usage to use this code.
> +{
> + if (!ctx)
> + return;
> +
> + ctx->spin_opts.addr = ctx->addr[0];
> + ctx->spin_opts.write_timestamp = true;
> + ctx->spin_opts.preempt = true;
> + xe_spin_init(ctx->spin, &ctx->spin_opts);
> +
> + /* re-use sync[0] for exec */
> + ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> +
> + ctx->exec.exec_queue_id = ctx->exec_queue;
> +
> + if (ctx->width > 1)
> + ctx->exec.address = to_user_pointer(ctx->addr);
> + else
> + ctx->exec.address = ctx->addr[0];
> +
> + xe_exec(fd, &ctx->exec);
> +
> + xe_spin_wait_started(ctx->spin);
> + igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> +
> + igt_debug("%d: spinner started\n", ctx->class);
I would add .debug option to xe_cork_opts to allow user to print debug
if necessary.
> +}
> +
> +void xe_spin_sync_end(int fd, struct xe_cork *ctx)
Similar to above - xe_cork_sync_end() or xe_cork_end().
> +{
> + if (!ctx || ctx->ended)
> + return;
> +
> + xe_spin_end(ctx->spin);
> +
> + igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> + igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
You should remove address from the allocator if ahnd != 0.
> +
> + ctx->ended = true;
> + igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
> + ctx->spin->timestamp);
Print this only if user will use .debug option.
> +}
> +
> +void xe_spin_ctx_destroy(int fd, struct xe_cork *ctx)
xe_cork_destroy().
> +{
> + if (!ctx)
> + return;
> +
> + syncobj_destroy(fd, ctx->sync[0].handle);
> + syncobj_destroy(fd, ctx->sync[1].handle);
> + xe_exec_queue_destroy(fd, ctx->exec_queue);
> +
> + munmap(ctx->spin, ctx->bo_size);
> + gem_close(fd, ctx->bo);
> +
> + free(ctx);
> +}
> +
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork)
Think how to switch to above code and drop this.
--
Zbigniew
> {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index d65adb05c..21488b071 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -32,6 +32,10 @@ struct xe_spin_opts {
> bool write_timestamp;
> };
>
> +struct xe_cork_opts {
> + uint64_t ahnd;
> +};
> +
> /* Mapped GPU object */
> struct xe_spin {
> uint32_t batch[128];
> @@ -43,9 +47,35 @@ struct xe_spin {
> uint32_t timestamp;
> };
>
> +struct xe_cork {
> + struct xe_spin *spin;
> + int fd;
> + uint32_t vm;
> + uint32_t bo;
> + uint32_t exec_queue;
> + uint32_t syncobj;
> + uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> + struct drm_xe_sync sync[2];
> + struct drm_xe_exec exec;
> + size_t bo_size;
> + struct xe_spin_opts spin_opts;
> + bool ended;
> + uint16_t class;
> + uint16_t width;
> + uint16_t num_placements;
> +};
> +
> igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
> void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
> +struct xe_cork *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> + uint16_t width, uint16_t num_placements, struct xe_cork_opts *opts);
> +void xe_spin_ctx_destroy(int fd, struct xe_cork *ctx);
> +
> +#define xe_spin_ctx_init_opts(fd, hwe, vm, width, num_placements, ...) \
> + xe_spin_ctx_init(fd, hwe, vm, width, num_placements, \
> + &((struct xe_cork_opts){__VA_ARGS__}))
>
> #define xe_spin_init_opts(fd, ...) \
> xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
> @@ -55,15 +85,9 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> void xe_spin_wait_started(struct xe_spin *spin);
> void xe_spin_end(struct xe_spin *spin);
> void xe_spin_free(int fd, struct igt_spin *spin);
> +void xe_spin_sync_start(int fd, struct xe_cork *ctx);
> +void xe_spin_sync_end(int fd, struct xe_cork *ctx);
>
> -struct xe_cork {
> - struct xe_spin *spin;
> - int fd;
> - uint32_t vm;
> - uint32_t bo;
> - uint32_t exec_queue;
> - uint32_t syncobj;
> -};
>
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork);
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 5fd7c0416..d7d392000 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
> igt_require(info.num_engines);
> }
>
> -struct spin_ctx {
> - uint32_t vm;
> - uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> - struct drm_xe_sync sync[2];
> - struct drm_xe_exec exec;
> - uint32_t exec_queue;
> - size_t bo_size;
> - uint32_t bo;
> - struct xe_spin *spin;
> - struct xe_spin_opts spin_opts;
> - bool ended;
> - uint16_t class;
> - uint16_t width;
> - uint16_t num_placements;
> -};
> -
> -static struct spin_ctx *
> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> - uint16_t width, uint16_t num_placements)
> -{
> - struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> -
> - igt_assert(width && num_placements &&
> - (width == 1 || num_placements == 1));
> - igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> -
> - ctx->class = hwe->engine_class;
> - ctx->width = width;
> - ctx->num_placements = num_placements;
> - ctx->vm = vm;
> -
> - for (unsigned int i = 0; i < width; i++)
> - ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> -
> - ctx->exec.num_batch_buffer = width;
> - ctx->exec.num_syncs = 2;
> - ctx->exec.syncs = to_user_pointer(ctx->sync);
> -
> - ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[0].handle = syncobj_create(fd, 0);
> -
> - ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> - ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> - ctx->sync[1].handle = syncobj_create(fd, 0);
> -
> - ctx->bo_size = sizeof(struct xe_spin);
> - ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> - ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> - vram_if_possible(fd, hwe->gt_id),
> - DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> - ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> -
> - igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> - hwe, 0, &ctx->exec_queue), 0);
> -
> - xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> - ctx->sync, 1);
> -
> - return ctx;
> -}
> -
> -static void
> -spin_sync_start(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - ctx->spin_opts.addr = ctx->addr[0];
> - ctx->spin_opts.write_timestamp = true;
> - ctx->spin_opts.preempt = true;
> - xe_spin_init(ctx->spin, &ctx->spin_opts);
> -
> - /* re-use sync[0] for exec */
> - ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> -
> - ctx->exec.exec_queue_id = ctx->exec_queue;
> -
> - if (ctx->width > 1)
> - ctx->exec.address = to_user_pointer(ctx->addr);
> - else
> - ctx->exec.address = ctx->addr[0];
> -
> - xe_exec(fd, &ctx->exec);
> -
> - xe_spin_wait_started(ctx->spin);
> - igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> -
> - igt_debug("%s: spinner started\n", engine_map[ctx->class]);
> -}
> -
> -static void
> -spin_sync_end(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx || ctx->ended)
> - return;
> -
> - xe_spin_end(ctx->spin);
> -
> - igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> - xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> - igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> - ctx->ended = true;
> - igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
> - ctx->spin->timestamp);
> -}
> -
> -static void
> -spin_ctx_destroy(int fd, struct spin_ctx *ctx)
> -{
> - if (!ctx)
> - return;
> -
> - syncobj_destroy(fd, ctx->sync[0].handle);
> - syncobj_destroy(fd, ctx->sync[1].handle);
> - xe_exec_queue_destroy(fd, ctx->exec_queue);
> -
> - munmap(ctx->spin, ctx->bo_size);
> - gem_close(fd, ctx->bo);
> -
> - free(ctx);
> -}
> -
> static void
> check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> int class, int width, enum expected_load expected_load)
> @@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> {
> struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> enum expected_load expected_load;
> uint32_t vm;
> int new_fd;
> @@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu1[0]);
> @@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu2[0]);
> if (flags & TEST_ISOLATION)
> @@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> close(new_fd);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> uint32_t vm;
>
> vm = xe_vm_create(fd, 0, 0);
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
>
> /* destroy queue before sampling again */
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> read_engine_cycles(fd, pceu2);
>
> @@ -610,18 +483,17 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> uint32_t vm;
> int class;
>
> vm = xe_vm_create(fd, 0, 0);
> -
> - ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx);
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -631,8 +503,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> check_results(pceu1, pceu2, class, 1, expected_load);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
> xe_vm_destroy(fd, vm);
> }
>
> @@ -641,7 +513,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> + struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> struct drm_xe_engine_class_instance *_hwe;
> uint32_t vm;
> int class;
> @@ -654,15 +526,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>
> if (_class == hwe->engine_class || ctx[_class])
> continue;
> -
> - ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[_class]);
> + ctx[_class] = xe_spin_ctx_init_opts(fd, _hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[_class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -673,8 +544,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> continue;
>
> check_results(pceu1, pceu2, class, 1, expected_load);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -685,7 +556,7 @@ utilization_all_full_load(int fd)
> {
> struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> - struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> + struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> struct drm_xe_engine_class_instance *hwe;
> uint32_t vm;
> int class;
> @@ -697,15 +568,14 @@ utilization_all_full_load(int fd)
> class = hwe->engine_class;
> if (ctx[class])
> continue;
> -
> - ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> - spin_sync_start(fd, ctx[class]);
> + ctx[class] = xe_spin_ctx_init_opts(fd, hwe, vm, 1, 1);
> + xe_spin_sync_start(fd, ctx[class]);
> }
>
> read_engine_cycles(fd, pceu1);
> usleep(batch_duration_usec);
> xe_for_each_engine_class(class)
> - spin_sync_end(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> read_engine_cycles(fd, pceu2);
>
> xe_for_each_engine_class(class) {
> @@ -713,8 +583,8 @@ utilization_all_full_load(int fd)
> continue;
>
> check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> - spin_sync_end(fd, ctx[class]);
> - spin_ctx_destroy(fd, ctx[class]);
> + xe_spin_sync_end(fd, ctx[class]);
> + xe_spin_ctx_destroy(fd, ctx[class]);
> }
>
> xe_vm_destroy(fd, vm);
> @@ -741,7 +611,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
> struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
> - struct spin_ctx *ctx = NULL;
> + struct xe_cork *ctx = NULL;
> enum expected_load expected_load;
> int fd_spill, num_placements;
> uint32_t vm;
> @@ -767,8 +637,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> vm = xe_vm_create(fd, 0, 0);
> if (flags & TEST_BUSY) {
> - ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> - spin_sync_start(fd, ctx);
> + ctx = xe_spin_ctx_init_opts(fd, eci, vm, width, num_placements);
> + xe_spin_sync_start(fd, ctx);
> }
>
> read_engine_cycles(fd, pceu[0]);
> @@ -777,7 +647,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>
> usleep(batch_duration_usec);
> if (flags & TEST_TRAILING_IDLE)
> - spin_sync_end(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
>
> read_engine_cycles(fd, pceu[1]);
> if (flags & TEST_ISOLATION)
> @@ -797,8 +667,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
> close(fd_spill);
> }
>
> - spin_sync_end(fd, ctx);
> - spin_ctx_destroy(fd, ctx);
> + xe_spin_sync_end(fd, ctx);
> + xe_spin_ctx_destroy(fd, ctx);
>
> xe_vm_destroy(fd, vm);
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-12-04 9:09 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
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2024-11-13 17:52 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
2024-11-13 17:52 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
2024-11-28 8:24 ` Peter Senna Tschudin
2024-12-04 9:09 ` Zbigniew Kempczyński
2024-11-13 17:52 ` [PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
2024-11-28 8:26 ` Peter Senna Tschudin
2024-11-13 20:07 ` ✓ Fi.CI.BAT: success for tests/xe_spin_batch: Add spin-timestamp-check (rev4) Patchwork
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2024-11-08 7:44 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
2024-11-08 7:44 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
2024-11-08 9:01 ` Zbigniew Kempczyński
2024-11-08 15:38 ` Lucas De Marchi
2024-11-13 16:13 ` Gurram, Pravalika
2024-11-13 16:57 ` Lucas De Marchi
2024-11-07 14:33 [PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check Pravalika Gurram
2024-11-07 14:33 ` [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib Pravalika Gurram
2024-11-07 17:08 ` Zbigniew Kempczyński
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