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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: Mohammed Thasleem <mohammed.thasleem@intel.com>,
	<igt-dev@lists.freedesktop.org>
Cc: Mohammed Thasleem <mohammed.thasleem@intel.com>
Subject: Re: [PATCH i-g-t v2] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test
Date: Thu, 13 Mar 2025 10:00:27 -0300	[thread overview]
Message-ID: <174187082742.91144.4847624528128996107@intel.com> (raw)
In-Reply-To: <20250309100649.26528-1-mohammed.thasleem@intel.com>

Quoting Mohammed Thasleem (2025-03-09 07:06:49-03:00)
>Low power Pipe A is required to run the DC5 transaction for Gen12.
>For Gen12+ to Xe3, either Pipe A or Pipe B is needed for the DC5
>transaction using a low power pipe. Added skip logic and logging
>to enforce these requirements.
>
>v2: Updated subject title and discription.
>    Add Gen checks for low power pipe selection. (Santosh)
>
>Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
>---
> tests/intel/kms_pm_dc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
>diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
>index bbb29d7d9..c7fde2af7 100644
>--- a/tests/intel/kms_pm_dc.c
>+++ b/tests/intel/kms_pm_dc.c
>@@ -156,10 +156,15 @@ static void setup_output(data_t *data)
>         igt_display_t *display = &data->display;
>         igt_output_t *output;
>         enum pipe pipe;
>+        int disp_ver = intel_display_ver(data->devid);
> 
>         for_each_pipe_with_valid_output(display, pipe, output) {
>                 drmModeConnectorPtr c = output->config.connector;
> 
>+                igt_skip_on_f((disp_ver <= 12 && pipe != PIPE_A) ||

The commit says "for Gen12+ to Xe3", implying that version 12 would also
allow pipe B, but here we are only allowing pipe A for version 12.

Looking at the specs, it seems we started to have pipe B as low power
pipe starting with display version 13, so it seems the code above is
right and the commit message needs an update.

There is a catch though: discrete devices like DG2 and BMG have
only pipe A as low power pipe.

>+                              (disp_ver <= 30 && !(pipe == PIPE_B || pipe == PIPE_A)),

Why are we limiting this for display version <= 30? This would cause any
new display release (i.e. a new display release with version > 30) to be
ignored.

I think it would be best to use ">=" checks as we usually do for
if-ladders in kernel code.

As such, my suggestion is as below:

  if (IS_BATTLEMAGE(data->devid) || IS_DG2(data->devid))
    low_power_pipe_selected = pipe == PIPE_A;
  else if (display_ver >= 13)
    low_power_pipe_selected = pipe == PIPE_A || pipe == PIPE_B;
  else
    low_power_pipe_selected = pipe == PIPE_A;

  igt_skip_on_f(!low_power_pipe_selected, ...);

By a quick look, it seems we do not have support full display version
(major and rel) in IGT yet, so we need IS_BATTLEMAGE() and IS_DG2()
here. In the future, we should replace those with full version checks.

--
Gustavo Sousa

>+                               "Low power pipe was not selected for the DC5 transaction.\n");
>+
>                 if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
>                         continue;
> 
>-- 
>2.25.1
>

  parent reply	other threads:[~2025-03-13 13:00 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-26  6:52 [PATCH i-g-t] tests/intel/kms_pm_dc: Add log information to dc5 psr test Mohammed Thasleem
2025-02-27 13:39 ` ✓ Xe.CI.BAT: success for " Patchwork
2025-02-27 13:52 ` ✓ i915.CI.BAT: " Patchwork
2025-02-27 16:04 ` ✗ Xe.CI.Full: failure " Patchwork
2025-02-28  0:26 ` ✗ i915.CI.Full: " Patchwork
2025-03-09  8:04 ` [PATCH i-g-t v2] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 " Mohammed Thasleem
2025-03-09  8:34 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev2) Patchwork
2025-03-09  8:55 ` ✓ i915.CI.BAT: " Patchwork
2025-03-09 10:06 ` [PATCH i-g-t v2] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test Mohammed Thasleem
2025-03-13  6:23   ` Reddy Guddati, Santhosh
2025-03-13 13:00   ` Gustavo Sousa [this message]
2025-03-09 10:34 ` ✗ i915.CI.Full: failure for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev2) Patchwork
2025-03-09 10:50 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev3) Patchwork
2025-03-09 11:11 ` ✓ i915.CI.BAT: " Patchwork
2025-03-09 12:52 ` ✗ i915.CI.Full: failure " Patchwork
2025-03-10  5:00 ` ✗ Xe.CI.Full: failure for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev2) Patchwork
2025-03-10  6:56 ` ✗ Xe.CI.Full: failure for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev3) Patchwork
2025-03-12  1:26 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev4) Patchwork
2025-03-12  1:47 ` ✗ i915.CI.BAT: failure " Patchwork
2025-03-12 17:08 ` ✓ Xe.CI.Full: success " Patchwork
2025-03-21  9:21 ` [PATCH i-g-t v3] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test Mohammed Thasleem
2025-03-21 17:16   ` Gustavo Sousa
2025-03-21 14:21 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev5) Patchwork
2025-03-21 14:39 ` ✓ i915.CI.BAT: " Patchwork
2025-03-21 15:15 ` ✗ Xe.CI.Full: failure " Patchwork
2025-03-21 16:33 ` ✗ i915.CI.Full: " Patchwork
2025-03-21 17:52 ` [PATCH i-g-t v4] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test Mohammed Thasleem
2025-03-24 13:21   ` Kamil Konieczny
2025-03-21 21:15 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev6) Patchwork
2025-03-21 21:30 ` ✓ i915.CI.BAT: " Patchwork
2025-03-21 23:09 ` ✗ Xe.CI.Full: failure " Patchwork
2025-03-22  2:37 ` ✗ i915.CI.Full: " Patchwork

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