From: Gustavo Sousa <gustavo.sousa@intel.com>
To: Mohammed Thasleem <mohammed.thasleem@intel.com>,
<igt-dev@lists.freedesktop.org>
Cc: Mohammed Thasleem <mohammed.thasleem@intel.com>,
Santhosh Reddy Guddati <santhosh.reddy.guddati@intel.com>
Subject: Re: [PATCH i-g-t v3] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test
Date: Fri, 21 Mar 2025 14:16:56 -0300 [thread overview]
Message-ID: <174257741685.5638.16547042130408254624@intel.com> (raw)
In-Reply-To: <20250321092120.85206-1-mohammed.thasleem@intel.com>
Quoting Mohammed Thasleem (2025-03-21 06:21:20-03:00)
>Prior to Gen12, Pipe A is required to run the DC5 transaction,
>ensuring low power operation. In display versions greater than 12,
>either Pipe A or Pipe B can be used for the DC5 transaction,
>providing flexibility in pipe selection
>
>However, display version 20 specifically requires Pipe A.
>Additionally, for Battlemage and DG2 devices, only Pipe A is
>required due to specific hardware constraints. To enforce these
>conditions, skip logic and logging have been added, ensuring that
>tests are only executed when the appropriate pipes are selected.
>
>v2: Updated subject title and discription.
> Add Gen checks for low power pipe selection. (Santosh)
>v3: Add check for bmg and dg2 for Pipe A also other checks for Pipe A
> and B. (Gustavo)
>
>Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
>Reviewed-by: Santhosh Reddy Guddati <santhosh.reddy.guddati@intel.com>
>---
> tests/intel/kms_pm_dc.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
>diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
>index 50473321a..b23c13363 100644
>--- a/tests/intel/kms_pm_dc.c
>+++ b/tests/intel/kms_pm_dc.c
>@@ -148,10 +148,16 @@ static void setup_output(data_t *data)
> igt_display_t *display = &data->display;
> igt_output_t *output;
> enum pipe pipe;
>+ int disp_ver = intel_display_ver(data->devid);
>
> for_each_pipe_with_valid_output(display, pipe, output) {
> drmModeConnectorPtr c = output->config.connector;
>
>+ igt_skip_on_f(((IS_BATTLEMAGE(data->devid) || IS_DG2(data->devid)) && pipe != PIPE_A) ||
>+ (disp_ver <= 12 && pipe != PIPE_A) || (disp_ver == 20 && pipe != PIPE_A) ||
>+ (disp_ver > 12 && disp_ver != 20 && !(pipe == PIPE_A || pipe == PIPE_B)),
>+ "Low power pipe was not selected for the DC5 transaction.\n");
>+
This seems correct, so
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
.
That said, I believe that condition is complex and not very readable. I
still think an if-ladder would make things more readable. Example:
if (disp_ver >= 13) {
if (disp_ver == 20 || IS_BATTLEMAGE(data->devid) || IS_DG2(data->devid))
is_low_power = pipe == PIPE_A;
else
is_low_power = pipe == PIPE_A || pipe == PIPE_B;
} else {
is_low_power = pipe == PIPE_A;
}
igt_skip_on_f(!is_low_power, "Low power pipe was not selected for the DC5 transaction.\n");
--
Gustavo Sousa
> if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
> continue;
>
>--
>2.43.0
>
next prev parent reply other threads:[~2025-03-21 17:17 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-26 6:52 [PATCH i-g-t] tests/intel/kms_pm_dc: Add log information to dc5 psr test Mohammed Thasleem
2025-02-27 13:39 ` ✓ Xe.CI.BAT: success for " Patchwork
2025-02-27 13:52 ` ✓ i915.CI.BAT: " Patchwork
2025-02-27 16:04 ` ✗ Xe.CI.Full: failure " Patchwork
2025-02-28 0:26 ` ✗ i915.CI.Full: " Patchwork
2025-03-09 8:04 ` [PATCH i-g-t v2] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 " Mohammed Thasleem
2025-03-09 8:34 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev2) Patchwork
2025-03-09 8:55 ` ✓ i915.CI.BAT: " Patchwork
2025-03-09 10:06 ` [PATCH i-g-t v2] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test Mohammed Thasleem
2025-03-13 6:23 ` Reddy Guddati, Santhosh
2025-03-13 13:00 ` Gustavo Sousa
2025-03-09 10:34 ` ✗ i915.CI.Full: failure for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev2) Patchwork
2025-03-09 10:50 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev3) Patchwork
2025-03-09 11:11 ` ✓ i915.CI.BAT: " Patchwork
2025-03-09 12:52 ` ✗ i915.CI.Full: failure " Patchwork
2025-03-10 5:00 ` ✗ Xe.CI.Full: failure for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev2) Patchwork
2025-03-10 6:56 ` ✗ Xe.CI.Full: failure for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev3) Patchwork
2025-03-12 1:26 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev4) Patchwork
2025-03-12 1:47 ` ✗ i915.CI.BAT: failure " Patchwork
2025-03-12 17:08 ` ✓ Xe.CI.Full: success " Patchwork
2025-03-21 9:21 ` [PATCH i-g-t v3] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test Mohammed Thasleem
2025-03-21 17:16 ` Gustavo Sousa [this message]
2025-03-21 14:21 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev5) Patchwork
2025-03-21 14:39 ` ✓ i915.CI.BAT: " Patchwork
2025-03-21 15:15 ` ✗ Xe.CI.Full: failure " Patchwork
2025-03-21 16:33 ` ✗ i915.CI.Full: " Patchwork
2025-03-21 17:52 ` [PATCH i-g-t v4] tests/intel/kms_pm_dc: Add skip logic and logging for DC5 psr test Mohammed Thasleem
2025-03-24 13:21 ` Kamil Konieczny
2025-03-21 21:15 ` ✓ Xe.CI.BAT: success for tests/intel/kms_pm_dc: Add log information to dc5 psr test (rev6) Patchwork
2025-03-21 21:30 ` ✓ i915.CI.BAT: " Patchwork
2025-03-21 23:09 ` ✗ Xe.CI.Full: failure " Patchwork
2025-03-22 2:37 ` ✗ i915.CI.Full: " Patchwork
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