Re: [PATCH v3 13/19] drm-uapi/amdgpu: sync with drm-next

[vitaly prosyak <vprosyak@amd.com>]

On 2025-04-01 12:06, Kamil Konieczny wrote:
> Hi Sunil,
> On 2025-03-28 at 13:54:10 +0530, Sunil Khatri wrote:
>> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
>>
> Hi Kamil,
>
> I removed this line
>

Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")

> as I believe it's internal information. If there are no objections, I'd like to merge without it.
>
> I just saw your reply, but I'll wait until tomorrow.
>
Thanks, Vitaly
> I could not find this commit in drm-next nor drm-tip,
> please add also subject to hash, like
>
> Align with kernel commit cd5bbb2532f2 ("drm/xe/uapi: Add a device query to
> get EU stall sampling information").
>
> One more point, you could also consider adding all in one patch
> unless they come from different trees, then please indicate from which
> ones they come.
>
> Regards,
> Kamil
>> Adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in
>> AMDGPU_INFO_IOCTL to get the size and alignment of shadow
>> and csa objects from the FW setup. This information is
>> required for the userqueue consumers.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> ---
>>  include/drm-uapi/amdgpu_drm.h | 21 +++++++++++++++++++++
>>  1 file changed, 21 insertions(+)
>>
>> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
>> index fed39c9b4..8108c0c8a 100644
>> --- a/include/drm-uapi/amdgpu_drm.h
>> +++ b/include/drm-uapi/amdgpu_drm.h
>> @@ -1439,6 +1439,27 @@ struct drm_amdgpu_info_hw_ip {
>>  	__u32  ip_discovery_version;
>>  };
>>  
>> +/* GFX metadata BO sizes and alignment info (in bytes) */
>> +struct drm_amdgpu_info_uq_fw_areas_gfx {
>> +	/* shadow area size */
>> +	__u32 shadow_size;
>> +	/* shadow area base virtual mem alignment */
>> +	__u32 shadow_alignment;
>> +	/* context save area size */
>> +	__u32 csa_size;
>> +	/* context save area base virtual mem alignment */
>> +	__u32 csa_alignment;
>> +};
>> +
>> +/* IP specific metadata related information used in the
>> + * subquery AMDGPU_INFO_UQ_FW_AREAS
>> + */
>> +struct drm_amdgpu_info_uq_fw_areas {
>> +	union {
>> +		struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
>> +	};
>> +};
>> +
>>  struct drm_amdgpu_info_num_handles {
>>  	/** Max handles as supported by firmware for UVD */
>>  	__u32  uvd_max_handles;
>> -- 
>> 2.43.0
>>