From: Sunil Khatri <sunil.khatri@amd.com>
To: igt-dev@lists.freedesktop.org
Cc: "Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Vitaly Prosyak" <vitaly.prosyak@amd.com>,
"Sunil Khatri" <sunil.khatri@amd.com>
Subject: [PATCH v3 12/19] tests/amdgpu: Add amdgpu_cp_nops tests for UMQ
Date: Fri, 28 Mar 2025 13:54:09 +0530 [thread overview]
Message-ID: <20250328082416.1469810-12-sunil.khatri@amd.com> (raw)
In-Reply-To: <20250328082416.1469810-1-sunil.khatri@amd.com>
Add new tests to support amdgpu_cs_nops tests for UMQ
submission by modifying the existing cs_nops tests
to support UMQ.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
tests/amdgpu/amd_cs_nop.c | 77 +++++++++++++++++++++++++++++++--------
1 file changed, 61 insertions(+), 16 deletions(-)
diff --git a/tests/amdgpu/amd_cs_nop.c b/tests/amdgpu/amd_cs_nop.c
index 720b276df..96a15a029 100644
--- a/tests/amdgpu/amd_cs_nop.c
+++ b/tests/amdgpu/amd_cs_nop.c
@@ -12,6 +12,7 @@
#include "lib/amdgpu/amd_PM4.h"
#include "lib/amdgpu/amd_ip_blocks.h"
#include "lib/amdgpu/amd_memory.h"
+#include "lib/amdgpu/amd_user_queue.h"
static void amdgpu_cs_sync(amdgpu_context_handle context,
unsigned int ip_type,
@@ -41,7 +42,8 @@ static void nop_cs(amdgpu_device_handle device,
unsigned int ip_type,
unsigned int ring,
unsigned int timeout,
- unsigned int flags)
+ unsigned int flags,
+ bool user_queue)
{
const int ncpus = flags & FORK ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
amdgpu_bo_handle ib_result_handle;
@@ -51,19 +53,36 @@ static void nop_cs(amdgpu_device_handle device,
int i, r;
amdgpu_bo_list_handle bo_list;
amdgpu_va_handle va_handle;
+ struct amdgpu_ring_context *ring_context;
- r = amdgpu_bo_alloc_and_map(device, 4096, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
- &ib_result_handle, &ib_result_cpu,
- &ib_result_mc_address, &va_handle);
+ ring_context = calloc(1, sizeof(*ring_context));
+ igt_assert(ring_context);
+
+ if (user_queue)
+ amdgpu_user_queue_create(device, ring_context, ip_type);
+
+ r = amdgpu_bo_alloc_and_map_sync(device, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0, AMDGPU_VM_MTYPE_UC,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle,
+ ring_context->timeline_syncobj_handle,
+ ++ring_context->point, user_queue);
igt_assert_eq(r, 0);
+ if (user_queue) {
+ r = amdgpu_timeline_syncobj_wait(device, ring_context->timeline_syncobj_handle,
+ ring_context->point);
+ igt_assert_eq(r, 0);
+ }
+
ptr = ib_result_cpu;
for (i = 0; i < 16; ++i)
ptr[i] = GFX_COMPUTE_NOP;
- r = amdgpu_bo_list_create(device, 1, &ib_result_handle, NULL, &bo_list);
- igt_assert_eq(r, 0);
+ if (!user_queue) {
+ r = amdgpu_bo_list_create(device, 1, &ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+ }
igt_fork(child, ncpus) {
struct amdgpu_cs_request ibs_request;
@@ -86,16 +105,25 @@ static void nop_cs(amdgpu_device_handle device,
count = 0;
igt_nsec_elapsed(&tv);
igt_until_timeout(timeout) {
- r = amdgpu_cs_submit(context, 0, &ibs_request, 1);
- igt_assert_eq(r, 0);
- if (flags & SYNC)
- amdgpu_cs_sync(context, ip_type, ring,
- ibs_request.seq_no);
+ if (user_queue) {
+ ring_context->pm4_dw = ib_info.size;
+ amdgpu_user_queue_submit(device, ring_context, ip_type,
+ ib_info.ib_mc_address);
+ igt_assert_eq(r, 0);
+ } else {
+ r = amdgpu_cs_submit(context, 0, &ibs_request, 1);
+ igt_assert_eq(r, 0);
+ if (flags & SYNC)
+ amdgpu_cs_sync(context, ip_type, ring,
+ ibs_request.seq_no);
+ }
+
count++;
}
submit_ns = igt_nsec_elapsed(&tv);
+ if (!user_queue)
+ amdgpu_cs_sync(context, ip_type, ring, ibs_request.seq_no);
- amdgpu_cs_sync(context, ip_type, ring, ibs_request.seq_no);
sync_ns = igt_nsec_elapsed(&tv);
igt_info("%s.%d: %'lu cycles, submit %.2fus, sync %.2fus\n",
@@ -104,11 +132,14 @@ static void nop_cs(amdgpu_device_handle device,
}
igt_waitchildren();
- r = amdgpu_bo_list_destroy(bo_list);
- igt_assert_eq(r, 0);
+ if (!user_queue) {
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+ }
amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
ib_result_mc_address, 4096);
+ free(ring_context);
}
igt_main
@@ -156,7 +187,21 @@ igt_main
igt_subtest_with_dynamic_f("cs-nops-with-%s-%s0", p->name, e->name) {
if (arr_cap[e->ip_type]) {
igt_dynamic_f("cs-nop-with-%s-%s0", p->name, e->name)
- nop_cs(device, context, e->name, e->ip_type, 0, 20, p->flags);
+ nop_cs(device, context, e->name, e->ip_type, 0, 20,
+ p->flags, 0);
+ }
+ }
+ }
+ }
+
+ for (p = phase; p->name; p++) {
+ for (e = engines; e->name; e++) {
+ igt_describe("Stressful-and-multiple-cs-of-nop-operations-using-multiple-processes-with-the-same-GPU-context-UMQ");
+ igt_subtest_with_dynamic_f("cs-nops-with-%s-%s0-with-UQ-Submission", p->name, e->name) {
+ if (arr_cap[e->ip_type]) {
+ igt_dynamic_f("cs-nop-with-%s-%s0-with-UQ-Submission", p->name, e->name)
+ nop_cs(device, context, e->name, e->ip_type, 0, 20,
+ p->flags, 1);
}
}
}
--
2.43.0
next prev parent reply other threads:[~2025-03-28 8:24 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-28 8:23 [PATCH v3 01/19] drm-uapi/amdgpu: sync with drm-next Sunil Khatri
2025-03-28 8:23 ` [PATCH v3 02/19] " Sunil Khatri
2025-03-31 19:11 ` vitaly prosyak
2025-04-01 4:39 ` Khatri, Sunil
2025-04-01 4:50 ` vitaly prosyak
2025-04-01 5:46 ` Khatri, Sunil
2025-04-01 16:09 ` Kamil Konieczny
2025-03-28 8:24 ` [PATCH v3 03/19] lib/amdgpu: Add user mode queue support in ring context Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 04/19] lib/amdgpu: Add support of amd user queues Sunil Khatri
2025-04-01 4:21 ` vitaly prosyak
2025-04-01 4:41 ` Khatri, Sunil
2025-03-28 8:24 ` [PATCH v3 05/19] lib/amdgpu: add func amdgpu_bo_alloc_and_map_sync Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 06/19] tests/amdgpu: Add user queue support for gfx and compute Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 07/19] tests/amdgpu: Add UMQ submission tests " Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 08/19] tests/amdgpu: Add amdgpu_sync_dependency_test with UMQ Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 09/19] tests/amdgpu: use memory API's from amd_memory.h Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 10/19] lib/amdgpu: add macro for adding cmds in user queue Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 11/19] lib/amdgpu: use macro to add cmds in the user ring Sunil Khatri
2025-03-28 8:24 ` Sunil Khatri [this message]
2025-03-28 8:24 ` [PATCH v3 13/19] drm-uapi/amdgpu: sync with drm-next Sunil Khatri
2025-04-01 16:06 ` Kamil Konieczny
2025-04-01 23:52 ` vitaly prosyak
2025-04-02 10:51 ` Kamil Konieczny
2025-04-01 23:57 ` vitaly prosyak
2025-03-28 8:24 ` [PATCH v3 14/19] lib/amdgpu: use right API to get the correct size Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 15/19] lib/amdgpu: use a memory fence to serialize write Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 16/19] tests/amdgpu: disable check for IP presense with no kernel queue Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 17/19] lib/amdgpu: make the local functions as static Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 18/19] lib/amdgpu: enable UMQ function under macro Sunil Khatri
2025-03-28 8:24 ` [PATCH v3 19/19] tests/amdgpu: Disable the UMQ tests under a macro Sunil Khatri
2025-03-28 13:01 ` ✓ Xe.CI.BAT: success for series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next Patchwork
2025-03-28 13:12 ` ✗ i915.CI.BAT: failure " Patchwork
2025-03-29 0:43 ` ✗ Xe.CI.Full: " Patchwork
2025-04-01 23:46 ` [PATCH v3 01/19] " vitaly prosyak
2025-04-06 18:47 ` ✗ Xe.CI.Full: failure for series starting with [v3,01/19] " Patchwork
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