[igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Chris Wilson]

On Skylake, BB_OFFSET seems to be unstable. Since this is an
offset into the batch at the time of CS execution, it should be actively
written to as we read from the register so allow it a qword of
discrepancy (since the CS should be reading in qwords). This still
allows us to detect dirt across the rest of the register field, should
that be required.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_ctx_isolation.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 058cf3ec1..78a244382 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -96,7 +96,7 @@ static const struct named_register {
 	{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
 	{ "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
 	{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
-	{ "BB_OFFSET", GEN8, RCS0, 0x2158 },
+	{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
 	{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
 	{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
 	{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
-- 
2.20.1

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[igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Patchwork]

== Series Details ==

Series: i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET
URL   : https://patchwork.freedesktop.org/series/54807/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5368 -> IGTPW_2188
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with IGTPW_2188 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2188, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/54807/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2188:

### IGT changes ###

#### Warnings ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       SKIP -> PASS +33

  * igt@pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       PASS -> SKIP

  
Known issues
------------

  Here are the changes found in IGTPW_2188 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-cfl-8109u:       PASS -> INCOMPLETE [fdo#107187] / [fdo#108126]

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@i915_selftest@live_contexts:
    - fi-icl-u3:          NOTRUN -> DMESG-FAIL [fdo#108569]

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-skl-6700hq:      PASS -> DMESG-WARN [fdo#105998]

  * igt@pm_rpm@basic-rte:
    - fi-bsw-kefka:       PASS -> FAIL [fdo#108800]

  
#### Possible fixes ####

  * igt@pm_rpm@module-reload:
    - fi-icl-u2:          DMESG-WARN [fdo#108654] -> PASS

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107187]: https://bugs.freedesktop.org/show_bug.cgi?id=107187
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108126]: https://bugs.freedesktop.org/show_bug.cgi?id=108126
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
  [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800


Participating hosts (47 -> 43)
------------------------------

  Additional (2): fi-byt-j1900 fi-icl-u3 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

    * IGT: IGT_4756 -> IGTPW_2188

  CI_DRM_5368: 64bd30ea3ce0edd057a5b393569947a955472757 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2188: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2188/
  IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2188/
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[igt-dev] ✓ Fi.CI.IGT: success for i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Patchwork]

== Series Details ==

Series: i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET
URL   : https://patchwork.freedesktop.org/series/54807/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5368_full -> IGTPW_2188_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/54807/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_2188_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_suspend@shrink:
    - shard-apl:          NOTRUN -> DMESG-WARN [fdo#107886] / [fdo#109244]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
    - shard-kbl:          NOTRUN -> DMESG-WARN [fdo#107956] +1

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-snb:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_cursor_crc@cursor-256x256-dpms:
    - shard-glk:          PASS -> FAIL [fdo#103232] +4

  * igt@kms_cursor_crc@cursor-64x21-sliding:
    - shard-apl:          PASS -> FAIL [fdo#103232] +5

  * igt@kms_cursor_crc@cursor-64x64-sliding:
    - shard-kbl:          PASS -> FAIL [fdo#103232] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-apl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
    - shard-glk:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +4

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-kbl:          PASS -> FAIL [fdo#103166] +2

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
    - shard-apl:          PASS -> FAIL [fdo#103166] +4

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
    - shard-glk:          PASS -> FAIL [fdo#103166] +4

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#105604]

  * igt@kms_setmode@basic:
    - shard-snb:          NOTRUN -> FAIL [fdo#99912]

  * igt@kms_vblank@pipe-a-query-idle:
    - shard-snb:          PASS -> INCOMPLETE [fdo#105411]

  * igt@prime_vgem@busy-bsd:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927]

  
#### Possible fixes ####

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-apl:          FAIL [fdo#106641] -> PASS

  * igt@kms_busy@extended-pageflip-hang-newfb-render-b:
    - shard-apl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
    - shard-glk:          FAIL [fdo#108145] -> PASS

  * igt@kms_color@pipe-c-ctm-max:
    - shard-apl:          FAIL [fdo#108147] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-256x85-random:
    - shard-glk:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x85-sliding:
    - shard-apl:          FAIL [fdo#103232] -> PASS +2

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-glk:          FAIL [fdo#102887] / [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-apl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-glk:          FAIL [fdo#103167] -> PASS +4

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS +3

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
    - shard-apl:          FAIL [fdo#103166] -> PASS +3
    - shard-kbl:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          DMESG-WARN [fdo#105763] / [fdo#106538] -> PASS

  * igt@kms_vblank@pipe-b-query-busy-hang:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  * igt@pm_rpm@dpms-non-lpsp:
    - shard-kbl:          DMESG-WARN [fdo#103313] / [fdo#105345] -> PASS +1

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105345]: https://bugs.freedesktop.org/show_bug.cgi?id=105345
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#107469]: https://bugs.freedesktop.org/show_bug.cgi?id=107469
  [fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
  [fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
  [fdo#109241]: https://bugs.freedesktop.org/show_bug.cgi?id=109241
  [fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (7 -> 5)
------------------------------

  Missing    (2): shard-skl shard-iclb 


Build changes
-------------

    * IGT: IGT_4756 -> IGTPW_2188
    * Piglit: piglit_4509 -> None

  CI_DRM_5368: 64bd30ea3ce0edd057a5b393569947a955472757 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2188: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2188/
  IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2188/
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Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Antonio Argenziano]

On 07/01/19 04:41, Chris Wilson wrote:
> On Skylake, BB_OFFSET seems to be unstable. Since this is an
> offset into the batch at the time of CS execution, it should be actively
> written to as we read from the register so allow it a qword of
> discrepancy (since the CS should be reading in qwords). This still
> allows us to detect dirt across the rest of the register field, should
> that be required.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   tests/i915/gem_ctx_isolation.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 058cf3ec1..78a244382 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -96,7 +96,7 @@ static const struct named_register {
>   	{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
>   	{ "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
>   	{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> -	{ "BB_OFFSET", GEN8, RCS0, 0x2158 },
> +	{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },

The batch offset starts at bit 2. Do we observe changes in bit 0-1 as well?

Antonio

>   	{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
>   	{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
>   	{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> 
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Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Chris Wilson]

Quoting Antonio Argenziano (2019-01-10 21:24:56)
> 
> 
> On 07/01/19 04:41, Chris Wilson wrote:
> > On Skylake, BB_OFFSET seems to be unstable. Since this is an
> > offset into the batch at the time of CS execution, it should be actively
> > written to as we read from the register so allow it a qword of
> > discrepancy (since the CS should be reading in qwords). This still
> > allows us to detect dirt across the rest of the register field, should
> > that be required.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> >   tests/i915/gem_ctx_isolation.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index 058cf3ec1..78a244382 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -96,7 +96,7 @@ static const struct named_register {
> >       { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> >       { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> >       { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> > -     { "BB_OFFSET", GEN8, RCS0, 0x2158 },
> > +     { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
> 
> The batch offset starts at bit 2. Do we observe changes in bit 0-1 as well?

Not, it is just off by bit 2 (0x4). Bit 0 is also set when I don't
really expect it to be, I guess I really should just read what the
register is meant to be rather than guessing solely on the basis of its
name.
-Chris
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Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Chris Wilson]

Quoting Chris Wilson (2019-01-10 21:27:54)
> Quoting Antonio Argenziano (2019-01-10 21:24:56)
> > 
> > 
> > On 07/01/19 04:41, Chris Wilson wrote:
> > > On Skylake, BB_OFFSET seems to be unstable. Since this is an
> > > offset into the batch at the time of CS execution, it should be actively
> > > written to as we read from the register so allow it a qword of
> > > discrepancy (since the CS should be reading in qwords). This still
> > > allows us to detect dirt across the rest of the register field, should
> > > that be required.
> > > 
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > ---
> > >   tests/i915/gem_ctx_isolation.c | 2 +-
> > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > > index 058cf3ec1..78a244382 100644
> > > --- a/tests/i915/gem_ctx_isolation.c
> > > +++ b/tests/i915/gem_ctx_isolation.c
> > > @@ -96,7 +96,7 @@ static const struct named_register {
> > >       { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> > >       { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> > >       { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> > > -     { "BB_OFFSET", GEN8, RCS0, 0x2158 },
> > > +     { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
> > 
> > The batch offset starts at bit 2. Do we observe changes in bit 0-1 as well?
> 
> Not, it is just off by bit 2 (0x4). Bit 0 is also set when I don't
> really expect it to be, I guess I really should just read what the
> register is meant to be rather than guessing solely on the basis of its
> name.

Bit 2 flip flops between reference value and observed (test failure).

Bit 0 simply differs from my own expectations.
-Chris
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Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Antonio Argenziano]

On 10/01/19 13:29, Chris Wilson wrote:
> Quoting Chris Wilson (2019-01-10 21:27:54)
>> Quoting Antonio Argenziano (2019-01-10 21:24:56)
>>>
>>>
>>> On 07/01/19 04:41, Chris Wilson wrote:
>>>> On Skylake, BB_OFFSET seems to be unstable. Since this is an
>>>> offset into the batch at the time of CS execution, it should be actively
>>>> written to as we read from the register so allow it a qword of
>>>> discrepancy (since the CS should be reading in qwords). This still
>>>> allows us to detect dirt across the rest of the register field, should
>>>> that be required.
>>>>
>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>>> ---
>>>>    tests/i915/gem_ctx_isolation.c | 2 +-
>>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
>>>> index 058cf3ec1..78a244382 100644
>>>> --- a/tests/i915/gem_ctx_isolation.c
>>>> +++ b/tests/i915/gem_ctx_isolation.c
>>>> @@ -96,7 +96,7 @@ static const struct named_register {
>>>>        { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
>>>>        { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
>>>>        { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
>>>> -     { "BB_OFFSET", GEN8, RCS0, 0x2158 },
>>>> +     { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
>>>
>>> The batch offset starts at bit 2. Do we observe changes in bit 0-1 as well?
>>
>> Not, it is just off by bit 2 (0x4). Bit 0 is also set when I don't
>> really expect it to be, I guess I really should just read what the
>> register is meant to be rather than guessing solely on the basis of its
>> name.
> 
> Bit 2 flip flops between reference value and observed (test failure).
> 
> Bit 0 simply differs from my own expectations.

I guess if it gets overwritten we catch it even if we ignore the lowest 
3 bits but something weird would have happened if 0-1 change.

With or without modifying the mask,
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>

> -Chris
> 
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Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

[Chris Wilson]

Quoting Antonio Argenziano (2019-01-10 21:58:52)
> 
> 
> On 10/01/19 13:29, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-01-10 21:27:54)
> >> Quoting Antonio Argenziano (2019-01-10 21:24:56)
> >>>
> >>>
> >>> On 07/01/19 04:41, Chris Wilson wrote:
> >>>> On Skylake, BB_OFFSET seems to be unstable. Since this is an
> >>>> offset into the batch at the time of CS execution, it should be actively
> >>>> written to as we read from the register so allow it a qword of
> >>>> discrepancy (since the CS should be reading in qwords). This still
> >>>> allows us to detect dirt across the rest of the register field, should
> >>>> that be required.
> >>>>
> >>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >>>> ---
> >>>>    tests/i915/gem_ctx_isolation.c | 2 +-
> >>>>    1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> >>>> index 058cf3ec1..78a244382 100644
> >>>> --- a/tests/i915/gem_ctx_isolation.c
> >>>> +++ b/tests/i915/gem_ctx_isolation.c
> >>>> @@ -96,7 +96,7 @@ static const struct named_register {
> >>>>        { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> >>>>        { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> >>>>        { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> >>>> -     { "BB_OFFSET", GEN8, RCS0, 0x2158 },
> >>>> +     { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
> >>>
> >>> The batch offset starts at bit 2. Do we observe changes in bit 0-1 as well?
> >>
> >> Not, it is just off by bit 2 (0x4). Bit 0 is also set when I don't
> >> really expect it to be, I guess I really should just read what the
> >> register is meant to be rather than guessing solely on the basis of its
> >> name.
> > 
> > Bit 2 flip flops between reference value and observed (test failure).
> > 
> > Bit 0 simply differs from my own expectations.
> 
> I guess if it gets overwritten we catch it even if we ignore the lowest 
> 3 bits but something weird would have happened if 0-1 change.
> 
> With or without modifying the mask,
> Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>

Restricted the mask to .ignore_bits=0x4 so that we only ignore the bit
that is fluctuating in testing.

Thanks,
-Chris
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