* [igt-dev] [PATCH v11 1/6] include/drm-uapi: import i915_drm.h header file
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
@ 2019-03-12 17:17 ` Andi Shyti
2019-03-12 17:17 ` [igt-dev] [PATCH v11 2/6] lib/i915: add gem_engine_topology library Andi Shyti
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2019-03-12 17:17 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
This header file is imported in order to include the two new
ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM and DRM_IOCTL_I915_QUERY.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
include/drm-uapi/i915_drm.h | 404 +++++++++++++++++++++++++++++-------
1 file changed, 331 insertions(+), 73 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 43fb8ede2fe0..2bbad08eb9d2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+ __u64 next_extension;
+ __u64 name;
+};
+
/*
* MOCS indexes used for GPU surfaces, defining the cacheability of the
* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -99,9 +119,14 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
+ /* should be kept compact */
+
I915_ENGINE_CLASS_INVALID = -1
};
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0
+
/**
* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
*
@@ -319,6 +344,9 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_I915_QUERY 0x39
+#define DRM_I915_GEM_VM_CREATE 0x3a
+#define DRM_I915_GEM_VM_DESTROY 0x3b
+/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -367,6 +395,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -377,6 +406,8 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -476,6 +507,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
+#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_PARAM_HUC_STATUS 42
@@ -559,6 +591,14 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_MMAP_GTT_COHERENT 52
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+/* Must be kept compact -- no holes and well documented */
+
typedef struct drm_i915_getparam {
__s32 param;
/*
@@ -574,6 +614,7 @@ typedef struct drm_i915_getparam {
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
#define I915_SETPARAM_NUM_USED_FENCES 4
+/* Must be kept compact -- no holes */
typedef struct drm_i915_setparam {
int param;
@@ -972,7 +1013,7 @@ struct drm_i915_gem_execbuffer2 {
* struct drm_i915_gem_exec_fence *fences.
*/
__u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK (7<<0)
+#define I915_EXEC_RING_MASK (0x3f)
#define I915_EXEC_DEFAULT (0<<0)
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
@@ -1078,7 +1119,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_ARRAY (1<<19)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
+/*
+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_SUBMIT (1 << 20)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1120,32 +1170,34 @@ struct drm_i915_gem_busy {
* as busy may become idle before the ioctl is completed.
*
* Furthermore, if the object is busy, which engine is busy is only
- * provided as a guide. There are race conditions which prevent the
- * report of which engines are busy from being always accurate.
- * However, the converse is not true. If the object is idle, the
- * result of the ioctl, that all engines are idle, is accurate.
+ * provided as a guide and only indirectly by reporting its class
+ * (there may be more than one engine in each class). There are race
+ * conditions which prevent the report of which engines are busy from
+ * being always accurate. However, the converse is not true. If the
+ * object is idle, the result of the ioctl, that all engines are idle,
+ * is accurate.
*
* The returned dword is split into two fields to indicate both
- * the engines on which the object is being read, and the
- * engine on which it is currently being written (if any).
+ * the engine classess on which the object is being read, and the
+ * engine class on which it is currently being written (if any).
*
* The low word (bits 0:15) indicate if the object is being written
* to by any engine (there can only be one, as the GEM implicit
* synchronisation rules force writes to be serialised). Only the
- * engine for the last write is reported.
+ * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
+ * 1 not 0 etc) for the last write is reported.
*
- * The high word (bits 16:31) are a bitmask of which engines are
- * currently reading from the object. Multiple engines may be
+ * The high word (bits 16:31) are a bitmask of which engines classes
+ * are currently reading from the object. Multiple engines may be
* reading from the object simultaneously.
*
- * The value of each engine is the same as specified in the
- * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
- * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
- * the I915_EXEC_RENDER engine for execution, and so it is never
+ * The value of each engine class is the same as specified in the
+ * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
+ * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
* reported as active itself. Some hardware may have parallel
* execution engines, e.g. multiple media engines, which are
- * mapped to the same identifier in the EXECBUFFER2 ioctl and
- * so are not separately reported for busyness.
+ * mapped to the same class identifier and so are not separately
+ * reported for busyness.
*
* Caveat emptor:
* Only the boolean result of this query is reliable; that is whether
@@ -1412,65 +1464,18 @@ struct drm_i915_gem_wait {
};
struct drm_i915_gem_context_create {
- /* output: id of new context*/
- __u32 ctx_id;
+ __u32 ctx_id; /* output: id of new context*/
__u32 pad;
};
-struct drm_i915_gem_context_destroy {
- __u32 ctx_id;
- __u32 pad;
-};
-
-struct drm_i915_reg_read {
- /*
- * Register offset.
- * For 64bit wide registers where the upper 32bits don't immediately
- * follow the lower 32bits, the offset of the lower 32bits must
- * be specified
- */
- __u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
- __u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- * single instruction 8byte read, in order to workaround that pass
- * flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
- __u32 ctx_id;
+struct drm_i915_gem_context_create_ext {
+ __u32 ctx_id; /* output: id of new context*/
__u32 flags;
-
- /* All resets since boot/module reload, for all contexts */
- __u32 reset_count;
-
- /* Number of batches lost when active in GPU, for this context */
- __u32 batch_active;
-
- /* Number of batches lost pending for execution, for this context */
- __u32 batch_pending;
-
- __u32 pad;
-};
-
-struct drm_i915_gem_userptr {
- __u64 user_ptr;
- __u64 user_size;
- __u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
- /**
- * Returned handle for the object.
- *
- * Object handles are nonzero.
- */
- __u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+ (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
+ __u64 extensions;
};
struct drm_i915_gem_context_param {
@@ -1511,6 +1516,43 @@ struct drm_i915_gem_context_param {
* On creation, all new contexts are marked as recoverable.
*/
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
+
+ /*
+ * The id of the associated virtual memory address space (ppGTT) of
+ * this context. Can be retrieved and passed to another context
+ * (on the same fd) for both to use the same ppGTT and so share
+ * address layouts, and avoid reloading the page tables on context
+ * switches between themselves.
+ *
+ * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+ */
+#define I915_CONTEXT_PARAM_VM 0x9
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ * engine_class: I915_ENGINE_CLASS_INVALID,
+ * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ *
+ * Extensions:
+ * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
+ * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ */
+#define I915_CONTEXT_PARAM_ENGINES 0xa
+/* Must be kept compact -- no holes and well documented */
+
__u64 value;
};
@@ -1543,9 +1585,10 @@ struct drm_i915_gem_context_param_sseu {
__u16 engine_instance;
/*
- * Unused for now. Must be cleared to zero.
+ * Unknown flags must be cleared to zero.
*/
__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
@@ -1573,6 +1616,175 @@ struct drm_i915_gem_context_param_sseu {
__u32 rsvd;
};
+/*
+ * i915_context_engines_load_balance:
+ *
+ * Enable load balancing across this set of engines.
+ *
+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
+ * used will proxy the execbuffer request onto one of the set of engines
+ * in such a way as to distribute the load evenly across the set.
+ *
+ * The set of engines must be compatible (e.g. the same HW class) as they
+ * will share the same logical GPU context and ring.
+ *
+ * To intermix rendering with the virtual engine and direct rendering onto
+ * the backing engines (bypassing the load balancing proxy), the context must
+ * be defined to use a single timeline for all engines.
+ */
+struct i915_context_engines_load_balance {
+ struct i915_user_extension base;
+
+ __u16 engine_index;
+ __u16 mbz16; /* reserved for future use; must be zero */
+ __u32 flags; /* all undefined flags must be zero */
+
+ __u64 engines_mask; /* selection mask of engines[] */
+
+ __u64 mbz64[4]; /* reserved for future use; must be zero */
+};
+
+/*
+ * i915_context_engines_bond:
+ *
+ */
+struct i915_context_engines_bond {
+ struct i915_user_extension base;
+
+ __u16 engine_index;
+ __u16 mbz;
+
+ __u16 master_class;
+ __u16 master_instance;
+
+ __u64 sibling_mask;
+ __u64 flags; /* all undefined flags must be zero */
+};
+
+struct i915_context_param_engines {
+ __u64 extensions; /* linked chain of extension blocks, 0 terminates */
+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0
+#define I915_CONTEXT_ENGINES_EXT_BOND 1
+
+ struct {
+ __u16 engine_class; /* see enum drm_i915_gem_engine_class */
+ __u16 engine_instance;
+ } class_instance[0];
+} __attribute__((packed));
+
+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
+ __u64 extensions; \
+ struct { \
+ __u16 engine_class; \
+ __u16 engine_instance; \
+ } class_instance[N__]; \
+} __attribute__((packed)) name__
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+ struct i915_user_extension base;
+ struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_create_ext_clone {
+#define I915_CONTEXT_CREATE_EXT_CLONE 1
+ struct i915_user_extension base;
+ __u32 clone_id;
+ __u32 flags;
+#define I915_CONTEXT_CLONE_FLAGS (1u << 0)
+#define I915_CONTEXT_CLONE_SCHED (1u << 1)
+#define I915_CONTEXT_CLONE_SSEU (1u << 2)
+#define I915_CONTEXT_CLONE_TIMELINE (1u << 3)
+#define I915_CONTEXT_CLONE_VM (1u << 4)
+#define I915_CONTEXT_CLONE_ENGINES (1u << 5)
+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1)
+ __u64 rsvd;
+};
+
+struct drm_i915_gem_context_destroy {
+ __u32 ctx_id;
+ __u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+ __u64 extensions;
+ __u32 flags;
+ __u32 id;
+};
+
+struct drm_i915_reg_read {
+ /*
+ * Register offset.
+ * For 64bit wide registers where the upper 32bits don't immediately
+ * follow the lower 32bits, the offset of the lower 32bits must
+ * be specified
+ */
+ __u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+ __u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ * single instruction 8byte read, in order to workaround that pass
+ * flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+ __u32 ctx_id;
+ __u32 flags;
+
+ /* All resets since boot/module reload, for all contexts */
+ __u32 reset_count;
+
+ /* Number of batches lost when active in GPU, for this context */
+ __u32 batch_active;
+
+ /* Number of batches lost pending for execution, for this context */
+ __u32 batch_pending;
+
+ __u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+ __u64 user_ptr;
+ __u64 user_size;
+ __u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+};
+
enum drm_i915_oa_format {
I915_OA_FORMAT_A13 = 1, /* HSW only */
I915_OA_FORMAT_A29, /* HSW only */
@@ -1734,6 +1946,8 @@ struct drm_i915_perf_oa_config {
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
+#define DRM_I915_QUERY_ENGINE_INFO 2
+/* Must be kept compact -- no holes and well documented */
/*
* When set to zero by userspace, this is filled with the size of the
@@ -1831,6 +2045,50 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+ /** Engine class as in enum drm_i915_gem_engine_class. */
+ __u16 engine_class;
+
+ /** Engine instance number. */
+ __u16 engine_instance;
+
+ /** Reserved field. */
+ __u32 rsvd0;
+
+ /** Engine flags. */
+ __u64 flags;
+
+ /** Capabilities of this engine. */
+ __u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
+
+ /** Reserved fields. */
+ __u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+ /** Number of struct drm_i915_engine_info structs following. */
+ __u32 num_engines;
+
+ /** MBZ */
+ __u32 rsvd[3];
+
+ /** Marker for drm_i915_engine_info structures. */
+ struct drm_i915_engine_info engines[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [igt-dev] [PATCH v11 2/6] lib/i915: add gem_engine_topology library
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
2019-03-12 17:17 ` [igt-dev] [PATCH v11 1/6] include/drm-uapi: import i915_drm.h header file Andi Shyti
@ 2019-03-12 17:17 ` Andi Shyti
2019-03-13 7:41 ` Tvrtko Ursulin
2019-03-12 17:17 ` [igt-dev] [PATCH v11 3/6] lib/igt_gt: use for_each_engine2 to loop through engines Andi Shyti
` (5 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Andi Shyti @ 2019-03-12 17:17 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.
The library's three main access points are:
- get_active_engines()
- __gem_prepare_context_engines()
- igt_require_gem_engine_list()
The first two functions are similar, with the difference that the
'gem_set_context_get_engines()' sets the engine before returning
the engine list in a 'intel_execution_engine2' type array.
Another improtant difference is that the first function works
only with the getparam/setparam and query ioctls are implemented
and it return 'NULL' in the other case.
It can be also used to check whether the current kernel contains
the new API.
'__gem_prepare_context_engines()' function, at the first call
generates the array of active engines (either physical or
virtual) called 'intel_active_engines2'.
If the driver cannot be queried, the 'intel_active_engines2'
array points to the exisiting 'intel_execution_engines2' which
has been previously defined.
The value of the 'intel_active_engines2' will be used in further
calls to check whether the above mentioned ioctls are implemented
without the need to call getparam().
The 'igt_require_gem_engine_list()' causes the test to fail in
case the required ioctls are not implemented.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
Hi Tvrtko,
the only thing I left untouched here is the fixed SIZEOF_QUERY,
even though the query ioctl doesn't have any limitation on query
size. The reason is because we've been discussing with Chris
setting a fixed size to prioritise stack allocation over heap
allocation so that I changed it to the way is done now from the
way you recommended at the beginning (already).
Andi
lib/Makefile.sources | 2 +
lib/i915/gem_engine_topology.c | 193 +++++++++++++++++++++++++++++++++
lib/i915/gem_engine_topology.h | 33 ++++++
lib/igt_gt.c | 2 +-
lib/igt_gt.h | 2 +-
lib/meson.build | 1 +
6 files changed, 231 insertions(+), 2 deletions(-)
create mode 100644 lib/i915/gem_engine_topology.c
create mode 100644 lib/i915/gem_engine_topology.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981707..757bd7a17ebe 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list = \
i915/gem_ring.c \
i915/gem_mman.c \
i915/gem_mman.h \
+ i915/gem_engine_topology.c \
+ i915/gem_engine_topology.h \
i915_3d.h \
i915_reg.h \
i915_pciids.h \
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..6d6cb85b0a26
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "igt_gt.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+#define SIZEOF_CTX_PARAM offsetof(struct i915_context_param_engines, \
+ class_instance[I915_EXEC_RING_MASK + 1])
+#define SIZEOF_QUERY offsetof(struct drm_i915_query_engine_info, \
+ engines[I915_EXEC_RING_MASK + 1])
+
+static struct intel_execution_engine2 *intel_active_engines2;
+static bool ctx_is_set;
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+ int err = 0;
+
+ if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+ err = -errno;
+
+ errno = 0;
+ return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+ igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+ struct drm_i915_query_engine_info *query_engines)
+{
+ struct drm_i915_query_item item = { };
+ struct drm_i915_query query = { };
+
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ query.items_ptr = to_user_pointer(&item);
+ query.num_items = 1;
+ item.length = SIZEOF_QUERY;
+
+ item.data_ptr = to_user_pointer(query_engines);
+
+ gem_query(fd, &query);
+}
+
+static void set_ctx_param_engines(int fd, uint32_t ctx_id)
+{
+ struct i915_context_param_engines *ctx_engine;
+ struct drm_i915_gem_context_param ctx_param;
+ const struct intel_execution_engine2 *e2;
+ uint8_t buff[SIZEOF_CTX_PARAM] = { };
+ int i;
+
+ if (ctx_is_set)
+ return;
+
+ ctx_engine = (struct i915_context_param_engines *) buff;
+
+ ctx_param.ctx_id = ctx_id;
+ ctx_param.param = I915_CONTEXT_PARAM_ENGINES;
+
+ ctx_engine->extensions = 0;
+ for (i = 0, e2 = intel_active_engines2; e2->name; i++, e2++) {
+ ctx_engine->class_instance[i].engine_class = e2->class;
+ ctx_engine->class_instance[i].engine_instance = e2->instance;
+ }
+
+ ctx_param.size = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
+ ctx_param.value = to_user_pointer(ctx_engine);
+
+ gem_context_set_param(fd, &ctx_param);
+
+ ctx_is_set = true;
+}
+
+/*
+ * Initializes the list of engines.
+ *
+ * Returns:
+ *
+ * - 0 in case of success and the get/set_param ioctls are implemented
+ * - -ENODEV in case of success but I915_CONTEXT_PARAM_ENGINES is not
+ * implemented in DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM ioctl.
+ */
+static int init_engine_list(int fd)
+{
+ const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
+ struct drm_i915_query_engine_info *query_engine;
+ unsigned char query_buffer[SIZEOF_QUERY] = { };
+ struct drm_i915_gem_context_param ctx_param = {
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ };
+ int i;
+
+ /* the list is already initialized */
+ if (intel_active_engines2)
+ return 0;
+
+ /*
+ * We check first whether the I915_CONTEXT_PARAM_ENGINES parameter is
+ * supported by the running kernel. If not, __gem_context_get_param()
+ * will return -EINVAL which, at this point, is not necessarily a
+ * failure but it means that we need to fall beck to polling the engines
+ * directly from intel_execution_engines2[].
+ *
+ * We will return -ENODEV with the meaning of missing interface
+ */
+ if (__gem_context_get_param(fd, &ctx_param))
+ return -ENODEV;
+
+ query_engine = (struct drm_i915_query_engine_info *) query_buffer;
+ query_engines(fd, query_engine);
+
+ intel_active_engines2 = malloc((query_engine->num_engines + 1) *
+ sizeof(*intel_active_engines2));
+ igt_assert(intel_active_engines2);
+
+ for (i = 0; i < query_engine->num_engines; i++) {
+ char *name;
+ __u16 class = query_engine->engines[i].engine_class;
+ __u16 instance = query_engine->engines[i].engine_instance;
+
+ intel_active_engines2[i].class = class;
+ intel_active_engines2[i].instance = instance;
+
+ /* if we don't recognise the class, then we mark it as "unk" */
+ if (class >= ARRAY_SIZE(class_names))
+ igt_assert(asprintf(&name, "unk-%d:%d",
+ class, instance) > 0);
+ else
+ igt_assert(asprintf(&name, "%s%d",
+ class_names[class], instance) > 0);
+
+ intel_active_engines2[i].name = name;
+ }
+
+ /* NULL value sentinel */
+ intel_active_engines2[i].name = NULL;
+
+ return 0;
+}
+
+struct intel_execution_engine2 *get_active_engines(int fd)
+{
+ if (init_engine_list(fd))
+ return NULL;
+
+ return intel_active_engines2;
+}
+
+struct intel_execution_engine2 *__gem_prepare_context_engines(int fd,
+ uint32_t ctx_id)
+{
+ struct intel_execution_engine2 *active_engines = get_active_engines(fd);
+
+ if (!active_engines) {
+ igt_debug("using pre-allocated engine list\n");
+ return intel_execution_engines2;
+ }
+
+ set_ctx_param_engines(fd, ctx_id);
+
+ return intel_active_engines2;
+}
+
+void igt_require_gem_engine_list(int fd)
+{
+ igt_require(!init_engine_list(fd));
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..88e902610ad8
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+struct intel_execution_engine2 *get_active_engines(int fd);
+struct intel_execution_engine2 *__gem_prepare_context_engines(int fd,
+ uint32_t ctx_id);
+
+void igt_require_gem_engine_list(int fd);
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index c98a7553b7fe..54c71e5e7186 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -577,7 +577,7 @@ bool gem_can_store_dword(int fd, unsigned int engine)
return true;
}
-const struct intel_execution_engine2 intel_execution_engines2[] = {
+struct intel_execution_engine2 intel_execution_engines2[] = {
{ "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
{ "bcs0", I915_ENGINE_CLASS_COPY, 0 },
{ "vcs0", I915_ENGINE_CLASS_VIDEO, 0 },
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 54e95da98084..f4bd6c22a81a 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -91,7 +91,7 @@ bool gem_ring_has_physical_engine(int fd, unsigned int ring);
bool gem_can_store_dword(int fd, unsigned int engine);
-extern const struct intel_execution_engine2 {
+extern struct intel_execution_engine2 {
const char *name;
int class;
int instance;
diff --git a/lib/meson.build b/lib/meson.build
index 0eb5585d72b9..3cc52f97c8bf 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
'i915/gem_submission.c',
'i915/gem_ring.c',
'i915/gem_mman.c',
+ 'i915/gem_engine_topology.c',
'igt_color_encoding.c',
'igt_debugfs.c',
'igt_device.c',
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [igt-dev] [PATCH v11 2/6] lib/i915: add gem_engine_topology library
2019-03-12 17:17 ` [igt-dev] [PATCH v11 2/6] lib/i915: add gem_engine_topology library Andi Shyti
@ 2019-03-13 7:41 ` Tvrtko Ursulin
2019-03-13 8:44 ` Andi Shyti
0 siblings, 1 reply; 11+ messages in thread
From: Tvrtko Ursulin @ 2019-03-13 7:41 UTC (permalink / raw)
To: Andi Shyti, IGT dev; +Cc: Andi Shyti
On 12/03/2019 17:17, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
>
> The library's three main access points are:
>
> - get_active_engines()
> - __gem_prepare_context_engines()
> - igt_require_gem_engine_list()
>
> The first two functions are similar, with the difference that the
> 'gem_set_context_get_engines()' sets the engine before returning
> the engine list in a 'intel_execution_engine2' type array.
> Another improtant difference is that the first function works
> only with the getparam/setparam and query ioctls are implemented
> and it return 'NULL' in the other case.
> It can be also used to check whether the current kernel contains
> the new API.
>
> '__gem_prepare_context_engines()' function, at the first call
> generates the array of active engines (either physical or
> virtual) called 'intel_active_engines2'.
> If the driver cannot be queried, the 'intel_active_engines2'
> array points to the exisiting 'intel_execution_engines2' which
> has been previously defined.
>
> The value of the 'intel_active_engines2' will be used in further
> calls to check whether the above mentioned ioctls are implemented
> without the need to call getparam().
>
> The 'igt_require_gem_engine_list()' causes the test to fail in
> case the required ioctls are not implemented.
>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
> Hi Tvrtko,
>
> the only thing I left untouched here is the fixed SIZEOF_QUERY,
> even though the query ioctl doesn't have any limitation on query
> size. The reason is because we've been discussing with Chris
> setting a fixed size to prioritise stack allocation over heap
> allocation so that I changed it to the way is done now from the
> way you recommended at the beginning (already).
>
> Andi
>
> lib/Makefile.sources | 2 +
> lib/i915/gem_engine_topology.c | 193 +++++++++++++++++++++++++++++++++
> lib/i915/gem_engine_topology.h | 33 ++++++
> lib/igt_gt.c | 2 +-
> lib/igt_gt.h | 2 +-
> lib/meson.build | 1 +
> 6 files changed, 231 insertions(+), 2 deletions(-)
> create mode 100644 lib/i915/gem_engine_topology.c
> create mode 100644 lib/i915/gem_engine_topology.h
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list = \
> i915/gem_ring.c \
> i915/gem_mman.c \
> i915/gem_mman.h \
> + i915/gem_engine_topology.c \
> + i915/gem_engine_topology.h \
> i915_3d.h \
> i915_reg.h \
> i915_pciids.h \
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..6d6cb85b0a26
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,193 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "igt_gt.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM offsetof(struct i915_context_param_engines, \
> + class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY offsetof(struct drm_i915_query_engine_info, \
> + engines[I915_EXEC_RING_MASK + 1])
> +
> +static struct intel_execution_engine2 *intel_active_engines2;
> +static bool ctx_is_set;
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> + int err = 0;
> +
> + if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> + err = -errno;
> +
> + errno = 0;
> + return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> + igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> + struct drm_i915_query_engine_info *query_engines)
> +{
> + struct drm_i915_query_item item = { };
> + struct drm_i915_query query = { };
> +
> + item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> + query.items_ptr = to_user_pointer(&item);
> + query.num_items = 1;
> + item.length = SIZEOF_QUERY;
> +
> + item.data_ptr = to_user_pointer(query_engines);
> +
> + gem_query(fd, &query);
> +}
> +
> +static void set_ctx_param_engines(int fd, uint32_t ctx_id)
> +{
> + struct i915_context_param_engines *ctx_engine;
> + struct drm_i915_gem_context_param ctx_param;
> + const struct intel_execution_engine2 *e2;
> + uint8_t buff[SIZEOF_CTX_PARAM] = { };
> + int i;
> +
> + if (ctx_is_set)
> + return;
A global ctx_is_set bool doesn't work with passed in ctx_id I think!?
But more importantly.. could you try and make the iterator work of the
local ctx.get_engines() query? Only configuring the ctx map to include
all engines if not already set.
Chris had a suggestion in the previous posting to use an iterator struct
which I think has merit since it hides the explicit index var/param.
(155179296327.27405.14019468668411244512@skylake-alporthouse-com)
And then I'd drop the for_each_engine2 and just convert
for_each_engine_class_instance straight away. Only one test uses it so
shouldn't be too hard (perf_pmu).
This will I think require adding the gem_set_eb_engine helper and
possibly adding some helpers to allow usage with spin batches.
We want to get a better view of usability in future IGT code and I think
the series needs to be complete in this respect.
Regards,
Tvrtko
> +
> + ctx_engine = (struct i915_context_param_engines *) buff;
> +
> + ctx_param.ctx_id = ctx_id;
> + ctx_param.param = I915_CONTEXT_PARAM_ENGINES;
> +
> + ctx_engine->extensions = 0;
> + for (i = 0, e2 = intel_active_engines2; e2->name; i++, e2++) {
> + ctx_engine->class_instance[i].engine_class = e2->class;
> + ctx_engine->class_instance[i].engine_instance = e2->instance;
> + }
> +
> + ctx_param.size = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
> + ctx_param.value = to_user_pointer(ctx_engine);
> +
> + gem_context_set_param(fd, &ctx_param);
> +
> + ctx_is_set = true;
> +}
> +
> +/*
> + * Initializes the list of engines.
> + *
> + * Returns:
> + *
> + * - 0 in case of success and the get/set_param ioctls are implemented
> + * - -ENODEV in case of success but I915_CONTEXT_PARAM_ENGINES is not
> + * implemented in DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM ioctl.
> + */
> +static int init_engine_list(int fd)
> +{
> + const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
> + struct drm_i915_query_engine_info *query_engine;
> + unsigned char query_buffer[SIZEOF_QUERY] = { };
> + struct drm_i915_gem_context_param ctx_param = {
> + .param = I915_CONTEXT_PARAM_ENGINES,
> + };
> + int i;
> +
> + /* the list is already initialized */
> + if (intel_active_engines2)
> + return 0;
> +
> + /*
> + * We check first whether the I915_CONTEXT_PARAM_ENGINES parameter is
> + * supported by the running kernel. If not, __gem_context_get_param()
> + * will return -EINVAL which, at this point, is not necessarily a
> + * failure but it means that we need to fall beck to polling the engines
> + * directly from intel_execution_engines2[].
> + *
> + * We will return -ENODEV with the meaning of missing interface
> + */
> + if (__gem_context_get_param(fd, &ctx_param))
> + return -ENODEV;
> +
> + query_engine = (struct drm_i915_query_engine_info *) query_buffer;
> + query_engines(fd, query_engine);
> +
> + intel_active_engines2 = malloc((query_engine->num_engines + 1) *
> + sizeof(*intel_active_engines2));
> + igt_assert(intel_active_engines2);
> +
> + for (i = 0; i < query_engine->num_engines; i++) {
> + char *name;
> + __u16 class = query_engine->engines[i].engine_class;
> + __u16 instance = query_engine->engines[i].engine_instance;
> +
> + intel_active_engines2[i].class = class;
> + intel_active_engines2[i].instance = instance;
> +
> + /* if we don't recognise the class, then we mark it as "unk" */
> + if (class >= ARRAY_SIZE(class_names))
> + igt_assert(asprintf(&name, "unk-%d:%d",
> + class, instance) > 0);
> + else
> + igt_assert(asprintf(&name, "%s%d",
> + class_names[class], instance) > 0);
> +
> + intel_active_engines2[i].name = name;
> + }
> +
> + /* NULL value sentinel */
> + intel_active_engines2[i].name = NULL;
> +
> + return 0;
> +}
> +
> +struct intel_execution_engine2 *get_active_engines(int fd)
> +{
> + if (init_engine_list(fd))
> + return NULL;
> +
> + return intel_active_engines2;
> +}
> +
> +struct intel_execution_engine2 *__gem_prepare_context_engines(int fd,
> + uint32_t ctx_id)
> +{
> + struct intel_execution_engine2 *active_engines = get_active_engines(fd);
> +
> + if (!active_engines) {
> + igt_debug("using pre-allocated engine list\n");
> + return intel_execution_engines2;
> + }
> +
> + set_ctx_param_engines(fd, ctx_id);
> +
> + return intel_active_engines2;
> +}
> +
> +void igt_require_gem_engine_list(int fd)
> +{
> + igt_require(!init_engine_list(fd));
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..88e902610ad8
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +struct intel_execution_engine2 *get_active_engines(int fd);
> +struct intel_execution_engine2 *__gem_prepare_context_engines(int fd,
> + uint32_t ctx_id);
> +
> +void igt_require_gem_engine_list(int fd);
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index c98a7553b7fe..54c71e5e7186 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -577,7 +577,7 @@ bool gem_can_store_dword(int fd, unsigned int engine)
> return true;
> }
>
> -const struct intel_execution_engine2 intel_execution_engines2[] = {
> +struct intel_execution_engine2 intel_execution_engines2[] = {
> { "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
> { "bcs0", I915_ENGINE_CLASS_COPY, 0 },
> { "vcs0", I915_ENGINE_CLASS_VIDEO, 0 },
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 54e95da98084..f4bd6c22a81a 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -91,7 +91,7 @@ bool gem_ring_has_physical_engine(int fd, unsigned int ring);
>
> bool gem_can_store_dword(int fd, unsigned int engine);
>
> -extern const struct intel_execution_engine2 {
> +extern struct intel_execution_engine2 {
> const char *name;
> int class;
> int instance;
> diff --git a/lib/meson.build b/lib/meson.build
> index 0eb5585d72b9..3cc52f97c8bf 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
> 'i915/gem_submission.c',
> 'i915/gem_ring.c',
> 'i915/gem_mman.c',
> + 'i915/gem_engine_topology.c',
> 'igt_color_encoding.c',
> 'igt_debugfs.c',
> 'igt_device.c',
>
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [igt-dev] [PATCH v11 2/6] lib/i915: add gem_engine_topology library
2019-03-13 7:41 ` Tvrtko Ursulin
@ 2019-03-13 8:44 ` Andi Shyti
0 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2019-03-13 8:44 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti
Hi Tvrtko,
> > +static void set_ctx_param_engines(int fd, uint32_t ctx_id)
> > +{
> > + struct i915_context_param_engines *ctx_engine;
> > + struct drm_i915_gem_context_param ctx_param;
> > + const struct intel_execution_engine2 *e2;
> > + uint8_t buff[SIZEOF_CTX_PARAM] = { };
> > + int i;
> > +
> > + if (ctx_is_set)
> > + return;
>
> A global ctx_is_set bool doesn't work with passed in ctx_id I think!?
>
> But more importantly.. could you try and make the iterator work of the local
> ctx.get_engines() query? Only configuring the ctx map to include all engines
> if not already set.
>
> Chris had a suggestion in the previous posting to use an iterator struct
> which I think has merit since it hides the explicit index var/param.
> (155179296327.27405.14019468668411244512@skylake-alporthouse-com)
>
> And then I'd drop the for_each_engine2 and just convert
> for_each_engine_class_instance straight away. Only one test uses it so
> shouldn't be too hard (perf_pmu).
>
> This will I think require adding the gem_set_eb_engine helper and possibly
> adding some helpers to allow usage with spin batches.
>
> We want to get a better view of usability in future IGT code and I think the
> series needs to be complete in this respect.
Yes, I understand the advantage of Chris proposal and the
ugliness of a globa ctx_is_set, but I thought we were going
throught this path in a second phase, given that for now "future
proof" (at least for me) is something with a different dimension
(I also wanted to keep the changes as smaller as possible, but it
turned out to be the wrong time to do so :) ).
Anyway, since you are pushing for this, I take this path.
Because I am now going to drastically change the logic, I would
also remove the 'init_engine_list()' and query the engine at any
'intel_engine_iter()' call with the double query (one for size
and one for the query itself).
... and it would be a completely different patchset :)
Andi
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH v11 3/6] lib/igt_gt: use for_each_engine2 to loop through engines
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
2019-03-12 17:17 ` [igt-dev] [PATCH v11 1/6] include/drm-uapi: import i915_drm.h header file Andi Shyti
2019-03-12 17:17 ` [igt-dev] [PATCH v11 2/6] lib/i915: add gem_engine_topology library Andi Shyti
@ 2019-03-12 17:17 ` Andi Shyti
2019-03-12 17:17 ` [igt-dev] [PATCH v11 4/6] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2019-03-12 17:17 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
'for_each_engine2()' defines a loop through the gpu engines.
It can work with both active and pre-defined engines.
In case we are looping through active engines (i.e. the running
kernel has the query and get/setparam ioctls), the
intel_active_engines2 points to an array that contains only the
list engines dynamically allocated after having interrogated the
driver.
While, if we are looping through pre-defined engines,
intel_active_engines2 points to the 'intel_execution_engines2'
array and works exactly as for_each_engine() but using the
new 'struct intel_execution_engine2' data type.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
Hi Tvrtko,
after this series goes in, I will cleanup the other for_each...
like the one you recommended, "for_each_engine_class_instance()".
(BTW, I was anaware of it :) ).
Andi
lib/igt_gt.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index f4bd6c22a81a..39768b5148ef 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -30,6 +30,8 @@
#include "i915_drm.h"
+#include "i915/gem_engine_topology.h"
+
void igt_require_hang_ring(int fd, int ring);
typedef struct igt_hang {
@@ -86,6 +88,12 @@ extern const struct intel_execution_engine {
e__++) \
for_if (gem_ring_has_physical_engine(fd__, flags__ = e__->exec_id | e__->flags))
+#define for_each_engine2(fd, ctx) \
+ for (struct intel_execution_engine2 *e2__ = \
+ __gem_prepare_context_engines(fd, ctx); e2__->name; e2__++) \
+ for_if (get_active_engines(fd) || \
+ gem_has_engine(fd, e2__->class, e2__->instance))
+
bool gem_ring_is_physical_engine(int fd, unsigned int ring);
bool gem_ring_has_physical_engine(int fd, unsigned int ring);
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [igt-dev] [PATCH v11 4/6] lib: ioctl_wrappers: reach engines by index as well
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
` (2 preceding siblings ...)
2019-03-12 17:17 ` [igt-dev] [PATCH v11 3/6] lib/igt_gt: use for_each_engine2 to loop through engines Andi Shyti
@ 2019-03-12 17:17 ` Andi Shyti
2019-03-12 17:17 ` [igt-dev] [PATCH v11 5/6] lib: move gem_context_has_engine from ioctl_wrappers to gem_context Andi Shyti
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2019-03-12 17:17 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
With the new engine query method engines are reachable through
an index and context they are combined with.
The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
requires the index that the engine is mapped within the driver.
The previous 'gem_has_ring()' function becomes a wrapper to the new
'gem_context_has_engine()'.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
lib/ioctl_wrappers.c | 4 +++-
lib/ioctl_wrappers.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 39920f8707d2..a2597e282704 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1252,7 +1252,7 @@ void igt_require_gem(int fd)
igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
}
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
{
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec;
@@ -1268,6 +1268,8 @@ bool gem_has_ring(int fd, unsigned ring)
execbuf.buffers_ptr = to_user_pointer(&exec);
execbuf.buffer_count = 1;
execbuf.flags = ring;
+ execbuf.rsvd1 = ctx;
+
return __gem_execbuf(fd, &execbuf) == -ENOENT;
}
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index f0be26080da6..935043617eb1 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,11 +142,13 @@ bool gem_has_exec_fence(int fd);
/* check functions which auto-skip tests by calling igt_skip() */
void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx);
void gem_require_ring(int fd, unsigned ring);
bool gem_has_mocs_registers(int fd);
void gem_require_mocs_registers(int fd);
+#define gem_has_ring(f, r) gem_context_has_engine(f, r, 0)
+
/* prime */
struct local_dma_buf_sync {
uint64_t flags;
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [igt-dev] [PATCH v11 5/6] lib: move gem_context_has_engine from ioctl_wrappers to gem_context
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
` (3 preceding siblings ...)
2019-03-12 17:17 ` [igt-dev] [PATCH v11 4/6] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
@ 2019-03-12 17:17 ` Andi Shyti
2019-03-12 17:17 ` [igt-dev] [PATCH v11 6/6] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test Andi Shyti
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2019-03-12 17:17 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
Function 'gem_has_ring()' has been renamed to
'gem_context_has_engine()' which acts more on an engine in
context domain. Move it to the gem_context library where it is
more appropriate.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
lib/i915/gem_context.c | 21 +++++++++++++++++++++
lib/i915/gem_context.h | 2 ++
lib/ioctl_wrappers.c | 21 ---------------------
lib/ioctl_wrappers.h | 1 -
4 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 16004685e920..5e2e31e91384 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
{
igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
}
+
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx)
+{
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 exec;
+
+ /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+ if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
+ if (engine & (3 << 13) && !gem_has_bsd2(fd))
+ return false;
+ }
+
+ memset(&exec, 0, sizeof(exec));
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&exec);
+ execbuf.buffer_count = 1;
+ execbuf.flags = engine;
+ execbuf.rsvd1 = ctx;
+
+ return __gem_execbuf(fd, &execbuf) == -ENOENT;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6b26..dd64ebf17fbd 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
void gem_context_set_priority(int fd, uint32_t ctx, int prio);
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
+
#endif /* GEM_CONTEXT_H */
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index a2597e282704..280fdd624529 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1252,27 +1252,6 @@ void igt_require_gem(int fd)
igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
}
-bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
-{
- struct drm_i915_gem_execbuffer2 execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
- if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
- if (ring & (3 << 13) && !gem_has_bsd2(fd))
- return false;
- }
-
- memset(&exec, 0, sizeof(exec));
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(&exec);
- execbuf.buffer_count = 1;
- execbuf.flags = ring;
- execbuf.rsvd1 = ctx;
-
- return __gem_execbuf(fd, &execbuf) == -ENOENT;
-}
-
/**
* gem_require_ring:
* @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 935043617eb1..1ebad10f28b0 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,7 +142,6 @@ bool gem_has_exec_fence(int fd);
/* check functions which auto-skip tests by calling igt_skip() */
void gem_require_caching(int fd);
-bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx);
void gem_require_ring(int fd, unsigned ring);
bool gem_has_mocs_registers(int fd);
void gem_require_mocs_registers(int fd);
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [igt-dev] [PATCH v11 6/6] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
` (4 preceding siblings ...)
2019-03-12 17:17 ` [igt-dev] [PATCH v11 5/6] lib: move gem_context_has_engine from ioctl_wrappers to gem_context Andi Shyti
@ 2019-03-12 17:17 ` Andi Shyti
2019-03-13 12:53 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
2019-03-13 16:03 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2019-03-12 17:17 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
The "exec-ctx" is a demo subtest inserted in the gem_exec_basic
test. The main goal is to reach the engines by using
the new uapi interfacing with igt_require_gem_engine_list().
The "exec-ctx" subtest simply gets the list of engines, binds
them to a context and executes a buffer. This is done through a
new "for_each_engine2" loop which iterates through the
engines.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
Hi Tvrtko,
I will add the gem_set_execbuf_engine() once this patchset goes
in.
Thanks for the suggestion,
Andi
tests/i915/gem_exec_basic.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..5d955179c2a5 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -135,6 +135,18 @@ igt_main
gtt(fd, e->exec_id | e->flags);
}
+ igt_subtest("exec-ctx") {
+ uint32_t ctx_id;
+ int index_map = 0;
+
+ ctx_id = gem_context_create(fd);
+ for_each_engine2(fd, ctx_id)
+ igt_assert(gem_context_has_engine(fd, ++index_map,
+ ctx_id));
+
+ gem_context_destroy(fd, ctx_id);
+ }
+
igt_fixture {
igt_stop_hang_detector();
close(fd);
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
` (5 preceding siblings ...)
2019-03-12 17:17 ` [igt-dev] [PATCH v11 6/6] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test Andi Shyti
@ 2019-03-13 12:53 ` Patchwork
2019-03-13 16:03 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-03-13 12:53 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev
== Series Details ==
Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/57891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5737 -> IGTPW_2599
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57891/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_2599 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@gtt-bsd2:
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57
* igt@gem_exec_basic@readonly-bsd1:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57
- fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-allowed:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: NOTRUN -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2
* igt@kms_chamelium@hdmi-edid-read:
- fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]
- fi-icl-u2: NOTRUN -> FAIL [fdo#103167]
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +20
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110028]: https://bugs.freedesktop.org/show_bug.cgi?id=110028
Participating hosts (41 -> 38)
------------------------------
Additional (6): fi-hsw-peppy fi-icl-u2 fi-snb-2520m fi-gdg-551 fi-icl-y fi-byt-clapper
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770 fi-pnv-d510 fi-bdw-samus
Build changes
-------------
* IGT: IGT_4883 -> IGTPW_2599
CI_DRM_5737: d5bb7d77aa77996702426496078a597f30bead58 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2599: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2599/
IGT_4883: b25e06d6ddf2e42044cd9c93b613cbc7339a8c33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_exec_basic@exec-ctx
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2599/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread* [igt-dev] ✓ Fi.CI.IGT: success for new engine discovery interface
2019-03-12 17:17 [igt-dev] [PATCH v11 0/6] new engine discovery interface Andi Shyti
` (6 preceding siblings ...)
2019-03-13 12:53 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
@ 2019-03-13 16:03 ` Patchwork
7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-03-13 16:03 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev
== Series Details ==
Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/57891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5737_full -> IGTPW_2599_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with IGTPW_2599_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_2599_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57891/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_2599_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_exec_basic@exec-ctx} (NEW):
- shard-kbl: NOTRUN -> FAIL
#### Warnings ####
* igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> FAIL
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@pixel-format-pipe-b-planes}:
- shard-kbl: PASS -> FAIL
New tests
---------
New tests have been introduced between CI_DRM_5737_full and IGTPW_2599_full:
### New IGT tests (1) ###
* igt@gem_exec_basic@exec-ctx:
- Statuses : 1 fail(s) 3 pass(s)
- Exec time: [0.0, 0.05] s
Known issues
------------
Here are the changes found in IGTPW_2599_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_param@invalid-param-set:
- shard-snb: NOTRUN -> FAIL [fdo#109674]
* igt@i915_pm_rpm@dpms-lpsp:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +32
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-kbl: PASS -> DMESG-WARN [fdo#107956]
- shard-snb: PASS -> DMESG-WARN [fdo#107956]
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_color@pipe-a-degamma:
- shard-glk: NOTRUN -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +106
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-glk: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232] +2
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-kbl: PASS -> FAIL [fdo#103232] +2
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: PASS -> FAIL [fdo#109350]
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: PASS -> FAIL [fdo#103355]
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +14
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-kbl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167] +6
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +11
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_psr@basic:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +4
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_universal_plane@cursor-fb-leak-pipe-d:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8
* igt@kms_vblank@pipe-b-ts-continuation-modeset-hang:
- shard-apl: PASS -> FAIL [fdo#104894]
* igt@runner@aborted:
- shard-apl: NOTRUN -> ( 8 FAIL ) [fdo#109373]
#### Possible fixes ####
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP [fdo#109271] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-hsw: DMESG-WARN [fdo#107956] -> PASS +2
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS +1
- shard-snb: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-kbl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: FAIL [fdo#105767] -> PASS
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* {igt@kms_plane@plane-position-covered-pipe-b-planes}:
- shard-apl: FAIL [fdo#110038] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_universal_plane@universal-plane-pipe-a-functional:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS +1
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: FAIL [fdo#104894] -> PASS +1
- shard-kbl: FAIL [fdo#104894] -> PASS
* igt@perf@rc6-disable:
- shard-kbl: FAIL [fdo#103179] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103179]: https://bugs.freedesktop.org/show_bug.cgi?id=103179
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
[fdo#110033]: https://bugs.freedesktop.org/show_bug.cgi?id=110033
[fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
[fdo#110038]: https://bugs.freedesktop.org/show_bug.cgi?id=110038
Participating hosts (10 -> 5)
------------------------------
Missing (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u
Build changes
-------------
* IGT: IGT_4883 -> IGTPW_2599
* Piglit: piglit_4509 -> None
CI_DRM_5737: d5bb7d77aa77996702426496078a597f30bead58 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2599: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2599/
IGT_4883: b25e06d6ddf2e42044cd9c93b613cbc7339a8c33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2599/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread