From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH i-g-t 23/25] gem_wsim: Consolidate engine assignments into helpers
Date: Fri, 17 May 2019 12:25:24 +0100 [thread overview]
Message-ID: <20190517112526.6738-24-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20190517112526.6738-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
This will allow applying the discovered engine configuration from a single
place.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
benchmarks/gem_wsim.c | 145 +++++++++++++++++++++++++-----------------
1 file changed, 87 insertions(+), 58 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index af042d71c1d3..d43e7c767801 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -365,6 +365,61 @@ static int str_to_engine(const char *str)
return -1;
}
+static unsigned int num_engines_in_class(enum intel_engine_id class)
+{
+ igt_assert(class == VCS);
+
+ return 2;
+}
+
+static void
+fill_engines_class(struct i915_engine_class_instance *ci,
+ enum intel_engine_id class)
+{
+ igt_assert(class == VCS);
+
+ ci[0].engine_class = I915_ENGINE_CLASS_VIDEO;
+ ci[0].engine_instance = 0;
+
+ ci[1].engine_class = I915_ENGINE_CLASS_VIDEO;
+ ci[1].engine_instance = 1;
+}
+
+static void
+fill_engines_id_class(enum intel_engine_id *list,
+ enum intel_engine_id class)
+{
+ igt_assert(class == VCS);
+
+ list[0] = VCS1;
+ list[1] = VCS2;
+}
+
+static struct i915_engine_class_instance
+get_engine(enum intel_engine_id engine)
+{
+ struct i915_engine_class_instance ci;
+
+ switch (engine) {
+ case RCS:
+ ci.engine_class = I915_ENGINE_CLASS_RENDER;
+ ci.engine_instance = 0;
+ break;
+ case VCS1:
+ ci.engine_class = I915_ENGINE_CLASS_VIDEO;
+ ci.engine_instance = 0;
+ break;
+ case VCS2:
+ ci.engine_class = I915_ENGINE_CLASS_VIDEO;
+ ci.engine_instance = 1;
+ break;
+ default:
+ igt_assert(0);
+ };
+
+ return ci;
+}
+
static int parse_engine_map(struct w_step *step, const char *_str)
{
char *token, *tctx = NULL, *tstart = (char *)_str;
@@ -386,18 +441,16 @@ static int parse_engine_map(struct w_step *step, const char *_str)
engine != RCS)
return -1; /* TODO */
- add = engine == VCS ? 2 : 1;
+ add = engine == VCS ? num_engines_in_class(VCS) : 1;
step->engine_map_count += add;
step->engine_map = realloc(step->engine_map,
step->engine_map_count *
sizeof(step->engine_map[0]));
- if (engine != VCS) {
- step->engine_map[step->engine_map_count - 1] = engine;
- } else {
- step->engine_map[step->engine_map_count - 2] = VCS1;
- step->engine_map[step->engine_map_count - 1] = VCS2;
- }
+ if (engine != VCS)
+ step->engine_map[step->engine_map_count - add] = engine;
+ else
+ fill_engines_id_class(&step->engine_map[step->engine_map_count - add], VCS);
}
return 0;
@@ -1472,19 +1525,9 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
load_balance.num_siblings =
ctx->engine_map_count;
- for (j = 0; j < ctx->engine_map_count; j++) {
- if (ctx->engine_map[j] == RCS) {
- load_balance.engines[j].engine_class =
- I915_ENGINE_CLASS_RENDER;
- load_balance.engines[j].engine_instance =
- 0; /* FIXME */
- } else {
- load_balance.engines[j].engine_class =
- I915_ENGINE_CLASS_VIDEO; /* FIXME */
- load_balance.engines[j].engine_instance =
- ctx->engine_map[j] - VCS1; /* FIXME */
- }
- }
+ for (j = 0; j < ctx->engine_map_count; j++)
+ load_balance.engines[j] =
+ get_engine(ctx->engine_map[j]);
} else {
set_engines.extensions = 0;
}
@@ -1495,18 +1538,9 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
set_engines.engines[0].engine_instance =
I915_ENGINE_CLASS_INVALID_NONE;
- for (j = 1; j <= ctx->engine_map_count; j++) {
- if (ctx->engine_map[j - 1] == RCS) {
- set_engines.engines[j].engine_class =
- I915_ENGINE_CLASS_RENDER;
- set_engines.engines[j].engine_instance = 0; /* FIXME */
- } else {
- set_engines.engines[j].engine_class =
- I915_ENGINE_CLASS_VIDEO; /* FIXME */
- set_engines.engines[j].engine_instance =
- ctx->engine_map[j - 1] - VCS1; /* FIXME */
- }
- }
+ for (j = 1; j <= ctx->engine_map_count; j++)
+ set_engines.engines[j] =
+ get_engine(ctx->engine_map[j - 1]);
for (j = 0; j < ctx->bond_count; j++) {
unsigned long mask = ctx->bonds[j].mask;
@@ -1529,10 +1563,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
p->base.name = I915_CONTEXT_ENGINES_EXT_BOND;
p->virtual_index = 0;
- p->master.engine_class =
- I915_ENGINE_CLASS_VIDEO;
- p->master.engine_instance =
- ctx->bonds[j].master - VCS1;
+ p->master = get_engine(ctx->bonds[j].master);
for (b = 0, e = 0; mask; e++, mask >>= 1) {
unsigned int idx;
@@ -1550,28 +1581,11 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
gem_context_set_param(fd, ¶m);
} else if (ctx->wants_balance) {
- I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(load_balance, 2) = {
- .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
- .num_siblings = 2,
- .engines = {
- { .engine_class = I915_ENGINE_CLASS_VIDEO,
- .engine_instance = 0 },
- { .engine_class = I915_ENGINE_CLASS_VIDEO,
- .engine_instance = 1 },
- },
- };
- I915_DEFINE_CONTEXT_PARAM_ENGINES(set_engines, 3) = {
- .extensions = to_user_pointer(&load_balance),
- .engines = {
- { .engine_class = I915_ENGINE_CLASS_INVALID,
- .engine_instance = I915_ENGINE_CLASS_INVALID_NONE },
- { .engine_class = I915_ENGINE_CLASS_VIDEO,
- .engine_instance = 0 },
- { .engine_class = I915_ENGINE_CLASS_VIDEO,
- .engine_instance = 1 },
- },
- };
-
+ const unsigned int count = num_engines_in_class(VCS);
+ I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(load_balance,
+ count);
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(set_engines,
+ count + 1);
struct drm_i915_gem_context_param param = {
.ctx_id = ctx_id,
.param = I915_CONTEXT_PARAM_ENGINES,
@@ -1579,6 +1593,21 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
.value = to_user_pointer(&set_engines),
};
+ set_engines.extensions = to_user_pointer(&load_balance);
+
+ set_engines.engines[0].engine_class =
+ I915_ENGINE_CLASS_INVALID;
+ set_engines.engines[0].engine_instance =
+ I915_ENGINE_CLASS_INVALID_NONE;
+ fill_engines_class(&set_engines.engines[1], VCS);
+
+ memset(&load_balance, 0, sizeof(load_balance));
+ load_balance.base.name =
+ I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
+ load_balance.num_siblings = count;
+
+ fill_engines_class(&load_balance.engines[0], VCS);
+
gem_context_set_param(fd, ¶m);
}
--
2.20.1
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next prev parent reply other threads:[~2019-05-17 11:25 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-17 11:25 [igt-dev] [PATCH i-g-t 00/25] Media scalability tooling Tvrtko Ursulin
2019-05-17 11:25 ` [Intel-gfx] [PATCH i-g-t 01/25] scripts/trace.pl: Fix after intel_engine_notify removal Tvrtko Ursulin
2019-05-17 11:25 ` [Intel-gfx] [PATCH i-g-t 02/25] trace.pl: Ignore signaling on non i915 fences Tvrtko Ursulin
2019-05-17 19:20 ` [igt-dev] " Chris Wilson
2019-05-20 10:30 ` Tvrtko Ursulin
2019-05-20 12:04 ` [igt-dev] [PATCH v2 " Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 03/25] headers: bump Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 04/25] trace.pl: Virtual engine support Tvrtko Ursulin
2019-05-17 19:23 ` Chris Wilson
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 05/25] trace.pl: Virtual engine preemption support Tvrtko Ursulin
2019-05-17 19:24 ` Chris Wilson
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 06/25] wsim/media-bench: i915 balancing Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 07/25] gem_wsim: Use IGT uapi headers Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 08/25] gem_wsim: Factor out common error handling Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 09/25] gem_wsim: More wsim_err Tvrtko Ursulin
2019-05-17 11:25 ` [Intel-gfx] [PATCH i-g-t 10/25] gem_wsim: Submit fence support Tvrtko Ursulin
2019-05-17 11:25 ` [Intel-gfx] [PATCH i-g-t 11/25] gem_wsim: Extract str to engine lookup Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 12/25] gem_wsim: Engine map support Tvrtko Ursulin
2019-05-17 19:35 ` Chris Wilson
2019-05-20 10:49 ` Tvrtko Ursulin
2019-05-20 10:59 ` Chris Wilson
2019-05-20 11:10 ` Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 13/25] gem_wsim: Save some lines by changing to implicit NULL checking Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 14/25] gem_wsim: Compact int command parsing with a macro Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 15/25] gem_wsim: Engine map load balance command Tvrtko Ursulin
2019-05-17 11:38 ` Chris Wilson
2019-05-17 11:52 ` Tvrtko Ursulin
2019-05-17 13:19 ` Chris Wilson
2019-05-17 19:36 ` Chris Wilson
2019-05-20 10:27 ` Tvrtko Ursulin
2019-05-17 11:25 ` [Intel-gfx] [PATCH i-g-t 16/25] gem_wsim: Engine bond command Tvrtko Ursulin
2019-05-17 19:41 ` [igt-dev] " Chris Wilson
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 17/25] gem_wsim: Some more example workloads Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 18/25] gem_wsim: Infinite batch support Tvrtko Ursulin
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 19/25] gem_wsim: Command line switch for specifying low slice count workloads Tvrtko Ursulin
2019-05-17 19:43 ` Chris Wilson
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 20/25] gem_wsim: Per context SSEU control Tvrtko Ursulin
2019-05-17 19:44 ` Chris Wilson
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 21/25] gem_wsim: Allow RCS virtual engine with " Tvrtko Ursulin
2019-05-17 19:45 ` Chris Wilson
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 22/25] tests/i915_query: Engine discovery tests Tvrtko Ursulin
2019-05-17 11:25 ` Tvrtko Ursulin [this message]
2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines Tvrtko Ursulin
2019-05-17 11:39 ` Andi Shyti
2019-05-17 11:51 ` Tvrtko Ursulin
2019-05-17 11:55 ` Andi Shyti
2019-05-17 19:50 ` Chris Wilson
2019-05-17 12:10 ` Andi Shyti
2019-05-17 12:19 ` Tvrtko Ursulin
2019-05-17 13:02 ` Andi Shyti
2019-05-17 13:05 ` Tvrtko Ursulin
2019-05-17 11:25 ` [Intel-gfx] [PATCH i-g-t 25/25] gem_wsim: Support Icelake parts Tvrtko Ursulin
2019-05-17 19:51 ` [igt-dev] " Chris Wilson
2019-05-17 12:18 ` [igt-dev] ✓ Fi.CI.BAT: success for Media scalability tooling (rev3) Patchwork
2019-05-17 17:33 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2019-05-20 13:30 ` [igt-dev] ✓ Fi.CI.BAT: success for Media scalability tooling (rev4) Patchwork
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