* [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
@ 2019-06-24 14:31 Dingchen Zhang
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_debugfs: add AMDGPU pipe crc sources Dingchen Zhang
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Dingchen Zhang @ 2019-06-24 14:31 UTC (permalink / raw)
To: igt-dev
Need framebuffer CRC to validate AMDGPU bypass mode.
For each color component less than 16-bits, padding zero bits,
loop to update CRC for each RGB compoment in the framebuffer.
The algorithm is based on DP spec v1.4.
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
Change-Id: Ifc2076df6c9b2156db23cae7ad968c61f404d0e4
Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
---
lib/igt_fb.c | 195 +++++++++++++++++++++++++++++++++++++++++++++++++++
lib/igt_fb.h | 2 +
2 files changed, 197 insertions(+)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 9d4f905e..2ac943c0 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -65,6 +65,7 @@
*/
#define PIXMAN_invalid 0
+#define CRC_INIT_16 0x0000
#if CAIRO_VERSION < CAIRO_VERSION_ENCODE(1, 17, 2)
/*
@@ -903,6 +904,200 @@ int igt_create_bo_with_dimensions(int fd, int width, int height,
return fb.gem_handle;
}
+#define get_u16_bit(x, n) ((x & (1 << n)) >> n )
+#define set_u16_bit(x, n, val) ((x & ~(1 << n)) | (val << n))
+/*
+ * update_crc16_dp:
+ * @crc_old: old 16-bit CRC value to be updated
+ * @d: input 16-bit data on which to calculate 16-bit CRC
+ *
+ * CRC algorithm implementation described in DP 1.4 spec Appendix J
+ * the 16-bit CRC IBM is applied, with the following polynomial:
+ *
+ * f(x) = x ^ 16 + x ^ 15 + x ^ 2 + 1
+ *
+ * the MSB is shifted in first, for any color format that is less than 16 bits
+ * per component, the LSB is zero-padded.
+ *
+ * The following implementation is based on the hardware parallel 16-bit CRC
+ * generation and ported to C code.
+ *
+ * Reference: VESA DisplayPort Standard v1.4, appendix J
+ *
+ * Returns:
+ * updated 16-bit CRC value.
+ */
+static uint16_t update_crc16_dp(uint16_t crc_old, uint16_t d)
+{
+ uint16_t crc_new = 0; /* 16-bit CRC output */
+
+ /* internal use */
+ uint16_t b = crc_old;
+ uint8_t val;
+
+ /* b[15] */
+ val = get_u16_bit(b, 0) ^ get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^
+ get_u16_bit(b, 3) ^ get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^
+ get_u16_bit(b, 6) ^ get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^
+ get_u16_bit(b, 9) ^ get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^
+ get_u16_bit(b, 12) ^ get_u16_bit(b, 14) ^ get_u16_bit(b, 15) ^
+ get_u16_bit(d, 0) ^ get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^
+ get_u16_bit(d, 3) ^ get_u16_bit(d, 4) ^ get_u16_bit(d, 5) ^
+ get_u16_bit(d, 6) ^ get_u16_bit(d, 7) ^ get_u16_bit(d, 8) ^
+ get_u16_bit(d, 9) ^ get_u16_bit(d, 10) ^ get_u16_bit(d, 11) ^
+ get_u16_bit(d, 12) ^ get_u16_bit(d, 14) ^ get_u16_bit(d, 15);
+ crc_new = set_u16_bit(crc_new, 15, val);
+
+ /* b[14] */
+ val = get_u16_bit(b, 12) ^ get_u16_bit(b, 13) ^
+ get_u16_bit(d, 12) ^ get_u16_bit(d, 13);
+ crc_new = set_u16_bit(crc_new, 14, val);
+
+ /* b[13] */
+ val = get_u16_bit(b, 11) ^ get_u16_bit(b, 12) ^
+ get_u16_bit(d, 11) ^ get_u16_bit(d, 12);
+ crc_new = set_u16_bit(crc_new, 13, val);
+
+ /* b[12] */
+ val = get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^
+ get_u16_bit(d, 10) ^ get_u16_bit(d, 11);
+ crc_new = set_u16_bit(crc_new, 12, val);
+
+ /* b[11] */
+ val = get_u16_bit(b, 9) ^ get_u16_bit(b, 10) ^
+ get_u16_bit(d, 9) ^ get_u16_bit(d, 10);
+ crc_new = set_u16_bit(crc_new, 11, val);
+
+ /* b[10] */
+ val = get_u16_bit(b, 8) ^ get_u16_bit(b, 9) ^
+ get_u16_bit(d, 8) ^ get_u16_bit(d, 9);
+ crc_new = set_u16_bit(crc_new, 10, val);
+
+ /* b[9] */
+ val = get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^
+ get_u16_bit(d, 7) ^ get_u16_bit(d, 8);
+ crc_new = set_u16_bit(crc_new, 9, val);
+
+ /* b[8] */
+ val = get_u16_bit(b, 6) ^ get_u16_bit(b, 7) ^
+ get_u16_bit(d, 6) ^ get_u16_bit(d, 7);
+ crc_new = set_u16_bit(crc_new, 8, val);
+
+ /* b[7] */
+ val = get_u16_bit(b, 5) ^ get_u16_bit(b, 6) ^
+ get_u16_bit(d, 5) ^ get_u16_bit(d, 6);
+ crc_new = set_u16_bit(crc_new, 7, val);
+
+ /* b[6] */
+ val = get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^
+ get_u16_bit(d, 4) ^ get_u16_bit(d, 5);
+ crc_new = set_u16_bit(crc_new, 6, val);
+
+ /* b[5] */
+ val = get_u16_bit(b, 3) ^ get_u16_bit(b, 4) ^
+ get_u16_bit(d, 3) ^ get_u16_bit(d, 4);
+ crc_new = set_u16_bit(crc_new, 5, val);
+
+ /* b[4] */
+ val = get_u16_bit(b, 2) ^ get_u16_bit(b, 3) ^
+ get_u16_bit(d, 2) ^ get_u16_bit(d, 3);
+ crc_new = set_u16_bit(crc_new, 4, val);
+
+ /* b[3] */
+ val = get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^ get_u16_bit(b, 15) ^
+ get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^ get_u16_bit(d, 15);
+ crc_new = set_u16_bit(crc_new, 3, val);
+
+ /* b[2] */
+ val = get_u16_bit(b, 0) ^ get_u16_bit(b, 1) ^ get_u16_bit(b, 14) ^
+ get_u16_bit(d, 0) ^ get_u16_bit(d, 1) ^ get_u16_bit(d, 14);
+ crc_new = set_u16_bit(crc_new, 2, val);
+
+ /* b[1] */
+ val = get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^ get_u16_bit(b, 3) ^
+ get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^ get_u16_bit(b, 6) ^
+ get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^ get_u16_bit(b, 9) ^
+ get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^ get_u16_bit(b, 12) ^
+ get_u16_bit(b, 13) ^ get_u16_bit(b, 14) ^
+ get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^ get_u16_bit(d, 3) ^
+ get_u16_bit(d, 4) ^ get_u16_bit(d, 5) ^ get_u16_bit(d, 6) ^
+ get_u16_bit(d, 7) ^ get_u16_bit(d, 8) ^ get_u16_bit(d, 9) ^
+ get_u16_bit(d, 10) ^ get_u16_bit(d, 11) ^ get_u16_bit(d, 12) ^
+ get_u16_bit(d, 13) ^ get_u16_bit(d, 14);
+ crc_new = set_u16_bit(crc_new, 1, val);
+
+ /* b[0] */
+ val = get_u16_bit(b, 0) ^ get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^
+ get_u16_bit(b, 3) ^ get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^
+ get_u16_bit(b, 6) ^ get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^
+ get_u16_bit(b, 9) ^ get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^
+ get_u16_bit(b, 12) ^ get_u16_bit(b, 13) ^ get_u16_bit(b, 15) ^
+ get_u16_bit(d, 0) ^ get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^
+ get_u16_bit(d, 3) ^ get_u16_bit(d, 4) ^ get_u16_bit(d, 5) ^
+ get_u16_bit(d, 6) ^ get_u16_bit(d, 7) ^ get_u16_bit(d, 8) ^
+ get_u16_bit(d, 9) ^ get_u16_bit(d, 10) ^ get_u16_bit(d, 11) ^
+ get_u16_bit(d, 12) ^ get_u16_bit(d, 13) ^ get_u16_bit(d, 15);
+ crc_new = set_u16_bit(crc_new, 0, val);
+
+ return crc_new;
+}
+
+/**
+ * igt_fb_calc_crc:
+ * @fb: pointer to an #igt_fb structure
+ * @crc: pointer to an #igt_crc_t structure
+ *
+ * This function calculate the 16-bit frame CRC of RGB components over all
+ * the active pixels.
+ */
+void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc)
+{
+ int x, y, i;
+ void *ptr;
+ uint8_t *data;
+ uint16_t din;
+
+ igt_assert(fb && crc);
+
+ ptr = igt_fb_map_buffer(fb->fd, fb);
+ igt_assert(ptr);
+
+ /* set for later CRC comparison */
+ crc->has_valid_frame = true;
+ crc->frame = 0;
+ crc->n_words = 3;
+ crc->crc[0] = CRC_INIT_16; /* R */
+ crc->crc[1] = CRC_INIT_16; /* G */
+ crc->crc[2] = CRC_INIT_16; /* B */
+
+ data = ptr + fb->offsets[0];
+ for (y = 0; y < fb->height; ++y) {
+ for (x = 0; x < fb->width; ++x) {
+ switch (fb->drm_format) {
+ case DRM_FORMAT_XRGB8888:
+ i = x * 4 + y * fb->strides[0];
+
+ din = data[i + 2] << 8; /* padding-zeros */
+ crc->crc[0] = update_crc16_dp(crc->crc[0], din);
+
+ /* Green-component */
+ din = data[i + 1] << 8;
+ crc->crc[1] = update_crc16_dp(crc->crc[1], din);
+
+ /* Blue-component */
+ din = data[i] << 8;
+ crc->crc[2] = update_crc16_dp(crc->crc[2], din);
+ break;
+ default:
+ igt_assert_f(0, "DRM Format Invalid");
+ break;
+ }
+ }
+ }
+
+ igt_fb_unmap_buffer(fb, ptr);
+}
+
/**
* igt_paint_color:
* @cr: cairo drawing context
diff --git a/lib/igt_fb.h b/lib/igt_fb.h
index adefebe1..be786911 100644
--- a/lib/igt_fb.h
+++ b/lib/igt_fb.h
@@ -37,6 +37,7 @@
#include <i915_drm.h>
#include "igt_color_encoding.h"
+#include "igt_debugfs.h"
/*
* Internal format to denote a buffer compatible with pixman's
@@ -158,6 +159,7 @@ int igt_create_bo_with_dimensions(int fd, int width, int height, uint32_t format
uint64_t modifier, unsigned stride,
uint64_t *size_ret, unsigned *stride_ret,
bool *is_dumb);
+void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc);
uint64_t igt_fb_mod_to_tiling(uint64_t modifier);
uint64_t igt_fb_tiling_to_mod(uint64_t tiling);
--
2.17.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t 2/4] lib/igt_debugfs: add AMDGPU pipe crc sources
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
@ 2019-06-24 14:31 ` Dingchen Zhang
2019-06-25 16:23 ` Kazlauskas, Nicholas
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 3/4] lib/igt_debugfs: add function to set pipe crc source name Dingchen Zhang
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Dingchen Zhang @ 2019-06-24 14:31 UTC (permalink / raw)
To: igt-dev
Need different pipe CRC sources to validate AMDGPU
digital bypass mode.
Added available AMDGPU pipe crc sources in igt_debugfs.h
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
Change-Id: Ia6c9ccb7a904ec8a490e519425c006ae2ea95a9b
Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
---
lib/igt_debugfs.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index 52520b3c..b49dd2b6 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -83,6 +83,9 @@ typedef struct {
} igt_crc_t;
#define INTEL_PIPE_CRC_SOURCE_AUTO "auto"
+#define AMDGPU_PIPE_CRC_SOURCE_AUTO "auto"
+#define AMDGPU_PIPE_CRC_SOURCE_CRTC "crtc"
+#define AMDGPU_PIPE_CRC_SOURCE_DPRX "dprx"
void igt_assert_crc_equal(const igt_crc_t *a, const igt_crc_t *b);
bool igt_check_crc_equal(const igt_crc_t *a, const igt_crc_t *b);
--
2.17.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t 3/4] lib/igt_debugfs: add function to set pipe crc source name.
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_debugfs: add AMDGPU pipe crc sources Dingchen Zhang
@ 2019-06-24 14:31 ` Dingchen Zhang
2019-06-25 16:26 ` Kazlauskas, Nicholas
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 4/4] tests/amdgpu: add 8bpc bypass mode test Dingchen Zhang
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Dingchen Zhang @ 2019-06-24 14:31 UTC (permalink / raw)
To: igt-dev
need to get CRC from different pipe crc source.
frees the existed pipe crc source and replace it with the new.
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
Change-Id: I41edae38f6c11525722295e975e77e497344ea71
Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
---
lib/igt_debugfs.c | 15 +++++++++++++++
lib/igt_debugfs.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 82ce1834..6dd7c537 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -994,6 +994,21 @@ void igt_pipe_crc_collect_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc)
igt_pipe_crc_stop(pipe_crc);
}
+/**
+ * igt_pipe_crc_set_source:
+ * @pipe_crc: pipe CRC object
+ * @src: pipe CRC source name
+ *
+ * The functions frees the current existed pipe CRC source name and replace
+ * it with the new given name 'source'
+ */
+void igt_pipe_crc_set_source(igt_pipe_crc_t *pipe_crc, const char *src)
+{
+ free(pipe_crc->source);
+ pipe_crc->source = strdup(src);
+ igt_assert(pipe_crc->source);
+}
+
/**
* igt_reset_fifo_underrun_reporting:
* @drm_fd: drm device file descriptor
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index b49dd2b6..640ec248 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -108,6 +108,7 @@ void igt_pipe_crc_get_single(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc);
void igt_pipe_crc_get_current(int drm_fd, igt_pipe_crc_t *pipe_crc, igt_crc_t *crc);
void igt_pipe_crc_collect_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc);
+void igt_pipe_crc_set_source(igt_pipe_crc_t *pipe_crc, const char *src);
void igt_hpd_storm_set_threshold(int fd, unsigned int threshold);
void igt_hpd_storm_reset(int fd);
--
2.17.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t 4/4] tests/amdgpu: add 8bpc bypass mode test.
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_debugfs: add AMDGPU pipe crc sources Dingchen Zhang
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 3/4] lib/igt_debugfs: add function to set pipe crc source name Dingchen Zhang
@ 2019-06-24 14:31 ` Dingchen Zhang
2019-06-25 16:29 ` Kazlauskas, Nicholas
2019-06-24 15:48 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Dingchen Zhang @ 2019-06-24 14:31 UTC (permalink / raw)
To: igt-dev
To validate the AMDGPU bypass mode feature.
Generate DP test patterns, program the pipe and check if
the CRCs of framebuffer and DP receiver match.
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
Change-Id: I5748f10188351399bb25c4fbacfd16ac66850877
Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
---
tests/amdgpu/amd_bypass.c | 383 ++++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 384 insertions(+)
create mode 100644 tests/amdgpu/amd_bypass.c
diff --git a/tests/amdgpu/amd_bypass.c b/tests/amdgpu/amd_bypass.c
new file mode 100644
index 00000000..17a67422
--- /dev/null
+++ b/tests/amdgpu/amd_bypass.c
@@ -0,0 +1,383 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: AMD
+ */
+#include "drm.h"
+#include "drmtest.h"
+#include "igt.h"
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include "signal.h"
+
+/*
+ * internal use
+ * Common test data
+ * */
+typedef struct {
+ int drm_fd;
+ int width;
+ int height;
+ enum pipe pipe_id;
+ igt_display_t display;
+ igt_plane_t *primary;
+ igt_output_t *output;
+ igt_pipe_t *pipe;
+ igt_pipe_crc_t *pipe_crc;
+ igt_crc_t crc_fb;
+ igt_crc_t crc_dprx;
+ drmModeModeInfo *mode;
+} data_t;
+
+enum pattern {
+ TEST_PATTERN_DP_COLOR_RAMP,
+ TEST_PATTERN_DP_BLACK_WHITE_VERT_LINES,
+ TEST_PATTERN_DP_BLACK_WHITE_HORZ_LINES,
+ TEST_PATTERN_DP_COLOR_SQUARES_VESA,
+ /* please don't add pattern after the below line */
+ TEST_PATTERN_MAX,
+};
+
+const char *ptnstr[TEST_PATTERN_MAX] = {
+ "DP Color Ramp",
+ "DP Vertical Lines",
+ "DP Horizontal Lines",
+ "DP Color Squares VESA"
+};
+
+/* Common test setup. */
+static void test_init(data_t *data)
+{
+ igt_display_t *display = &data->display;
+
+ /* It doesn't matter which pipe we choose on amdpgu. */
+ data->pipe_id = PIPE_A;
+ data->pipe = &data->display.pipes[data->pipe_id];
+
+ igt_display_reset(display);
+
+ data->output = igt_get_single_output_for_pipe(display, data->pipe_id);
+ igt_assert(data->output);
+
+ data->mode = igt_output_get_mode(data->output);
+ igt_assert(data->mode);
+
+ data->primary =
+ igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
+
+ data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe_id,
+ AMDGPU_PIPE_CRC_SOURCE_AUTO);
+ igt_pipe_crc_set_source(data->pipe_crc, AMDGPU_PIPE_CRC_SOURCE_DPRX);
+
+ igt_output_set_pipe(data->output, data->pipe_id);
+
+ data->width = data->mode->hdisplay;
+ data->height = data->mode->vdisplay;
+}
+
+/* Common test cleanup. */
+static void test_fini(data_t *data)
+{
+ igt_pipe_crc_free(data->pipe_crc);
+ igt_display_reset(&data->display);
+}
+
+/*
+ * draw the DP color ramp test pattern
+ * Reference: DP Link CTS 1.2 Core r1.1, sec. 3.1.5.1
+ */
+static void draw_dp_test_pattern_color_ramp(igt_fb_t *fb)
+{
+ const int h = 64; /* test pattern rectangle height */
+ const int block_h = h * 4; /* block height of R-G-B-White rectangles */
+ void *ptr_fb;
+ uint8_t *data;
+ int x,y;
+ int i;
+ uint8_t val;
+
+ /*
+ * 64-by-256 pixels per rectangle
+ * R-G-B-White rectangle in order in vertical
+ * duplicate in horizontal
+ */
+ ptr_fb = igt_fb_map_buffer(fb->fd, fb);
+ igt_assert(ptr_fb);
+ data = ptr_fb + fb->offsets[0];
+
+ for (y = 0; y < fb->height; ++y) {
+ for (x = 0, val = 0; x < fb->width; ++x, ++val) {
+ switch (fb->drm_format) {
+ case DRM_FORMAT_XRGB8888:
+ i = x * 4 + y * fb->strides[0];
+
+ /* vertical R-G-B-White rec */
+ if ((y % block_h) < h) { /* Red */
+ data[i + 2] = val;
+ data[i + 1] = 0;
+ data[i + 0] = 0;
+ } else if ((y % block_h) < 2 * h) { /* Green */
+ data[i + 2] = 0;
+ data[i + 1] = val;
+ data[i + 0] = 0;
+ } else if ((y % block_h) < 3 * h) { /* Blue */
+ data[i + 2] = 0;
+ data[i + 1] = 0;
+ data[i + 0] = val;
+ } else { /* White */
+ data[i + 2] = val;
+ data[i + 1] = val;
+ data[i + 0] = val;
+ }
+ break;
+ default:
+ igt_assert_f(0, "DRM Format Invalid");
+ break;
+ }
+ }
+ }
+
+ igt_fb_unmap_buffer(fb, ptr_fb);
+}
+
+/*
+ * draw the DP vertical lines test pattern
+ * * Reference: DP Link CTS 1.2 Core r1.1, sec. 3.1.5.2
+ */
+static void draw_dp_test_pattern_vert_lines(igt_fb_t *fb)
+{
+ void *ptr_fb;
+ uint8_t *data;
+ int x, y;
+ int i;
+
+ /* alternating black and white lines, 1 pixel wide */
+ ptr_fb = igt_fb_map_buffer(fb->fd, fb);
+ igt_assert(ptr_fb);
+ data = ptr_fb + fb->offsets[0];
+
+ for (y = 0; y < fb->height; ++y) {
+ for (x = 0; x < fb->width; ++x) {
+ switch (fb->drm_format) {
+ case DRM_FORMAT_XRGB8888:
+ i = x * 4 + y * fb->strides[0];
+
+ if ((x & 1) == 0) {
+ data[i + 2] = 0xff; /* R */
+ data[i + 1] = 0xff; /* G */
+ data[i + 0] = 0xff; /* B */
+ }
+ else {
+ data[i + 2] = 0;
+ data[i + 1] = 0;
+ data[i + 0] = 0;
+ }
+ break;
+ default:
+ igt_assert_f(0, "DRM Format Invalid");
+ break;
+ }
+ }
+ }
+
+ igt_fb_unmap_buffer(fb, ptr_fb);
+}
+
+/* draw the DP horizontal lines test pattern */
+static void draw_dp_test_pattern_horz_lines(igt_fb_t *fb)
+{
+ void *ptr_fb;
+ uint8_t *data;
+ int x, y;
+ int i;
+
+ /* alternating black and white horizontal lines, 1 pixel high */
+ ptr_fb = igt_fb_map_buffer(fb->fd, fb);
+ igt_assert(ptr_fb);
+ data = ptr_fb + fb->offsets[0];
+
+ for (y = 0; y < fb->height; ++y) {
+ for (x = 0; x < fb->width; ++x) {
+ switch (fb->drm_format) {
+ case DRM_FORMAT_XRGB8888:
+ i = x * 4 + y * fb->strides[0];
+
+ if ((y & 1) == 0) {
+ data[i + 2] = 0xff; /* R */
+ data[i + 1] = 0xff; /* G */
+ data[i + 0] = 0xff; /* B */
+ }
+ else {
+ data[i + 2] = 0;
+ data[i + 1] = 0;
+ data[i + 0] = 0;
+ }
+ break;
+ default:
+ igt_assert_f(0, "DRM Format Invalid");
+ break;
+ }
+ }
+ }
+
+ igt_fb_unmap_buffer(fb, ptr_fb);
+}
+
+/*
+ * draw the DP color squares VESA test pattern
+ * Reference: DP Link CTS 1.2 Core r1.1, sec. 3.1.5.3
+ */
+static void draw_dp_test_pattern_color_squares_vesa(igt_fb_t *fb)
+{
+ const int h = 64; /* test pattern square height/width */
+ const int block_h = h * 2; /* block height of the repetition pattern */
+ const int block_w = h * 8; /* block width of the repetition pattern */
+ const uint8_t rgb[3][2][8] = {
+ {/* Red table of the pattern squares */
+ {255, 255, 0, 0, 255, 255, 0, 0},
+ {0, 255, 255, 0, 0, 255, 255, 0},
+ },
+ {/* Green table */
+ {255, 255, 255, 255, 0, 0, 0, 0},
+ {0, 0, 0, 255, 255, 255, 255, 0},
+ },
+ {/* Blue table */
+ {255, 0, 255, 0, 255, 0, 255, 0},
+ {255, 0, 255, 0, 255, 0, 255, 0},
+ },
+ };
+
+ void *ptr_fb;
+ uint8_t *data;
+ int x, y;
+ int i, j, k;
+
+ ptr_fb = igt_fb_map_buffer(fb->fd, fb);
+ igt_assert(ptr_fb);
+ data = ptr_fb + fb->offsets[0];
+
+ for (y = 0; y < fb->height; ++y) {
+ for (x = 0; x < fb->width; ++x) {
+ switch (fb->drm_format) {
+ case DRM_FORMAT_XRGB8888:
+ i = x * 4 + y * fb->strides[0];
+ j = (y % block_h) / h;
+ k = (x % block_w) / h;
+
+ data[i + 2] = rgb[0][j][k]; /* R */
+ data[i + 1] = rgb[1][j][k]; /* G */
+ data[i + 0] = rgb[2][j][k]; /* B */
+ break;
+ default:
+ igt_assert_f(0, "DRM Format Invalid");
+ break;
+ }
+ }
+ }
+
+ igt_fb_unmap_buffer(fb, ptr_fb);
+}
+
+/* generate test pattern and fills a FB */
+static void generate_test_pattern(igt_fb_t *fb, data_t *data, enum pattern ptn)
+{
+ igt_assert(fb->fd && (ptn < TEST_PATTERN_MAX));
+
+ if (ptn == TEST_PATTERN_DP_COLOR_RAMP) {
+ draw_dp_test_pattern_color_ramp(fb);
+ } else if (ptn == TEST_PATTERN_DP_BLACK_WHITE_VERT_LINES) {
+ draw_dp_test_pattern_vert_lines(fb);
+ } else if (ptn == TEST_PATTERN_DP_BLACK_WHITE_HORZ_LINES) {
+ draw_dp_test_pattern_horz_lines(fb);
+ } else if (ptn == TEST_PATTERN_DP_COLOR_SQUARES_VESA) {
+ draw_dp_test_pattern_color_squares_vesa(fb);
+ }
+}
+
+static void bypass_8bpc_test(data_t *data)
+{
+ igt_display_t *display = &data->display;
+ igt_fb_t fb;
+ enum pattern ptn;
+
+ test_init(data);
+
+ igt_create_fb(data->drm_fd, data->width, data->height,
+ DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE, &fb);
+
+ /*
+ * Settings:
+ * no degamma
+ * no regamma
+ * no CTM
+ */
+ igt_pipe_obj_replace_prop_blob(data->pipe, IGT_CRTC_DEGAMMA_LUT, NULL, 0);
+ igt_pipe_obj_replace_prop_blob(data->pipe, IGT_CRTC_GAMMA_LUT, NULL, 0);
+ igt_pipe_obj_replace_prop_blob(data->pipe, IGT_CRTC_CTM, NULL, 0);
+
+ igt_plane_set_fb(data->primary, &fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ /* traverse all the test pattern to validate 8bpc bypass mode */
+ for (ptn = TEST_PATTERN_DP_COLOR_RAMP; ptn < TEST_PATTERN_MAX; ++ptn) {
+ igt_debug("Test Pattern: %s\n", ptnstr[ptn]);
+
+ generate_test_pattern(&fb, data, ptn);
+
+ /* Grab FB and DPRX CRCs and compare */
+ igt_fb_calc_crc(&fb, &data->crc_fb);
+ igt_pipe_crc_collect_crc(data->pipe_crc, &data->crc_dprx);
+
+ igt_assert_crc_equal(&data->crc_fb, &data->crc_dprx);
+ }
+
+ igt_plane_set_fb(data->primary, NULL);
+ test_fini(data);
+ igt_remove_fb(data->drm_fd, &fb);
+}
+
+igt_main
+{
+ data_t data;
+ memset(&data, 0, sizeof(data));
+
+ igt_skip_on_simulation();
+
+ igt_fixture {
+ data.drm_fd = drm_open_driver_master(DRIVER_AMDGPU);
+ if (data.drm_fd == -1)
+ igt_skip("Not an amdgpu driver.\n");
+ igt_require_pipe_crc(data.drm_fd);
+
+ kmstest_set_vt_graphics_mode();
+
+ igt_display_require(&data.display, data.drm_fd);
+ igt_require(data.display.is_atomic);
+ igt_display_require_output(&data.display);
+ }
+
+ igt_subtest("8bpc-bypass-mode")
+ bypass_8bpc_test(&data);
+
+ igt_fixture {
+ igt_display_fini(&data.display);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 42086374..b7982291 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -4,6 +4,7 @@ amdgpu_deps = test_deps
if libdrm_amdgpu.found()
amdgpu_progs += [ 'amd_abm',
'amd_basic',
+ 'amd_bypass',
'amd_color',
'amd_cs_nop',
'amd_prime',
--
2.17.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
` (2 preceding siblings ...)
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 4/4] tests/amdgpu: add 8bpc bypass mode test Dingchen Zhang
@ 2019-06-24 15:48 ` Patchwork
2019-06-24 19:05 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-06-24 15:48 UTC (permalink / raw)
To: Dingchen Zhang; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
URL : https://patchwork.freedesktop.org/series/62649/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6334 -> IGTPW_3192
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/62649/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_3192 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([fdo#108511])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
- fi-skl-lmem: [PASS][5] -> [INCOMPLETE][6] ([fdo#107807])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_basic@create-fd-close:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/fi-icl-u3/igt@gem_basic@create-fd-close.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/fi-icl-u3/igt@gem_basic@create-fd-close.html
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][11] ([fdo#107713] / [fdo#109100]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/fi-icl-u3/igt@gem_ctx_create@basic-files.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/fi-icl-u3/igt@gem_ctx_create@basic-files.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (50 -> 41)
------------------------------
Additional (1): fi-byt-j1900
Missing (10): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* IGT: IGT_5065 -> IGTPW_3192
CI_DRM_6334: 86d1a866f35634912d7699f1eb4d04a2007df18e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3192: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/
IGT_5065: f454000b5ba221b19d696a27415fe5824d743284 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@amdgpu/amd_bypass@8bpc-bypass-mode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
` (3 preceding siblings ...)
2019-06-24 15:48 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Patchwork
@ 2019-06-24 19:05 ` Patchwork
2019-06-25 6:54 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
2019-06-25 16:20 ` [igt-dev] [PATCH i-g-t 1/4] " Kazlauskas, Nicholas
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-06-24 19:05 UTC (permalink / raw)
To: Dingchen Zhang; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
URL : https://patchwork.freedesktop.org/series/62649/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6334_full -> IGTPW_3192_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_3192_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3192_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/62649/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3192_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@reset-stress:
- shard-kbl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl2/igt@gem_eio@reset-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl7/igt@gem_eio@reset-stress.html
Known issues
------------
Here are the changes found in IGTPW_3192_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#110913 ]) +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl4/igt@gem_eio@in-flight-contexts-10ms.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl4/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_reloc@basic-gtt-active:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) +6 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl7/igt@gem_exec_reloc@basic-gtt-active.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl2/igt@gem_exec_reloc@basic-gtt-active.html
* igt@gem_partial_pwrite_pread@reads:
- shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#110789] / [fdo#110913 ]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw5/igt@gem_partial_pwrite_pread@reads.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw7/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#110789] / [fdo#110913 ]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb4/igt@gem_persistent_relocs@forked-thrashing.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb2/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_softpin@evict-active-interruptible:
- shard-glk: [PASS][13] -> [DMESG-WARN][14] ([fdo#110913 ]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk8/igt@gem_softpin@evict-active-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk3/igt@gem_softpin@evict-active-interruptible.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([fdo#110913 ]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb6/igt@gem_tiled_partial_pwrite_pread@writes.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb7/igt@gem_tiled_partial_pwrite_pread@writes.html
* igt@gem_tiled_wc:
- shard-glk: [PASS][17] -> [INCOMPLETE][18] ([fdo#103359] / [k.org#198133])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk9/igt@gem_tiled_wc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk7/igt@gem_tiled_wc.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([fdo#110913 ])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw8/igt@gem_userptr_blits@sync-unmap-cycles.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw4/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb5/igt@i915_pm_rc6_residency@rc6-accuracy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb7/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-hsw: [PASS][23] -> [SKIP][24] ([fdo#109271]) +9 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-c-forked-move:
- shard-hsw: [PASS][25] -> [INCOMPLETE][26] ([fdo#103540])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw4/igt@kms_cursor_legacy@pipe-c-forked-move.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw8/igt@kms_cursor_legacy@pipe-c-forked-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][27] -> [FAIL][28] ([fdo#103167]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][29] -> [FAIL][30] ([fdo#103166])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][31] -> [FAIL][32] ([fdo#108341])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb2/igt@kms_psr@no_drrs.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][35] -> [FAIL][36] ([fdo#99912])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl4/igt@kms_setmode@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl1/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#100047])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb7/igt@kms_sysfs_edid_timing.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb2/igt@kms_sysfs_edid_timing.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][39] ([fdo#110854]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb3/igt@gem_exec_balancer@smoke.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb1/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-apl: [DMESG-WARN][41] ([fdo#110913 ]) -> [PASS][42] +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl6/igt@gem_exec_reloc@basic-write-gtt-active.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl3/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_mmap_gtt@hang:
- shard-kbl: [DMESG-WARN][43] ([fdo#110913 ]) -> [PASS][44] +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl6/igt@gem_mmap_gtt@hang.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl3/igt@gem_mmap_gtt@hang.html
- shard-snb: [INCOMPLETE][45] ([fdo#105411]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb5/igt@gem_mmap_gtt@hang.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb6/igt@gem_mmap_gtt@hang.html
- shard-iclb: [DMESG-WARN][47] ([fdo#110913 ]) -> [PASS][48] +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb2/igt@gem_mmap_gtt@hang.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb5/igt@gem_mmap_gtt@hang.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-hsw: [DMESG-WARN][49] ([fdo#110789] / [fdo#110913 ]) -> [PASS][50] +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw6/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_softpin@softpin:
- shard-snb: [DMESG-WARN][51] ([fdo#110789] / [fdo#110913 ]) -> [PASS][52] +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb6/igt@gem_softpin@softpin.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb2/igt@gem_softpin@softpin.html
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: [FAIL][53] ([fdo#108686]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb7/igt@gem_tiled_swapping@non-threaded.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb6/igt@gem_tiled_swapping@non-threaded.html
- shard-glk: [DMESG-WARN][55] ([fdo#108686]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk3/igt@gem_tiled_swapping@non-threaded.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk9/igt@gem_tiled_swapping@non-threaded.html
- shard-apl: [DMESG-WARN][57] ([fdo#108686]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl6/igt@gem_tiled_swapping@non-threaded.html
- shard-snb: [DMESG-WARN][59] -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb6/igt@gem_tiled_swapping@non-threaded.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb1/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-glk: [DMESG-WARN][61] ([fdo#110913 ]) -> [PASS][62] +5 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
- shard-snb: [DMESG-WARN][63] ([fdo#110913 ]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
- shard-hsw: [DMESG-WARN][65] ([fdo#110913 ]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [INCOMPLETE][67] ([fdo#107713] / [fdo#108569] / [fdo#110331]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb8/igt@i915_selftest@live_hangcheck.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb7/igt@i915_selftest@live_hangcheck.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-iclb: [FAIL][71] ([fdo#108134]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb1/igt@kms_flip_tiling@flip-to-x-tiled.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb3/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-hsw: [SKIP][73] ([fdo#109271]) -> [PASS][74] +23 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render:
- shard-glk: [FAIL][75] ([fdo#103167]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][77] ([fdo#103167]) -> [PASS][78] +5 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][79] ([fdo#109441]) -> [PASS][80] +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb5/igt@kms_psr@psr2_no_drrs.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][81] ([fdo#99912]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl2/igt@kms_setmode@basic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-query-busy-hang:
- shard-snb: [SKIP][83] ([fdo#109271]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb4/igt@kms_vblank@pipe-b-query-busy-hang.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb5/igt@kms_vblank@pipe-b-query-busy-hang.html
#### Warnings ####
* igt@kms_atomic_transition@4x-modeset-transitions:
- shard-snb: [SKIP][85] ([fdo#109271]) -> [SKIP][86] ([fdo#109271] / [fdo#109278])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb4/igt@kms_atomic_transition@4x-modeset-transitions.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb1/igt@kms_atomic_transition@4x-modeset-transitions.html
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110331]: https://bugs.freedesktop.org/show_bug.cgi?id=110331
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 6)
------------------------------
Missing (4): pig-skl-6260u shard-skl pig-hsw-4770r pig-glk-j5005
Build changes
-------------
* IGT: IGT_5065 -> IGTPW_3192
* Piglit: piglit_4509 -> None
CI_DRM_6334: 86d1a866f35634912d7699f1eb4d04a2007df18e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3192: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/
IGT_5065: f454000b5ba221b19d696a27415fe5824d743284 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
` (4 preceding siblings ...)
2019-06-24 19:05 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-06-25 6:54 ` Patchwork
2019-06-25 16:20 ` [igt-dev] [PATCH i-g-t 1/4] " Kazlauskas, Nicholas
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-06-25 6:54 UTC (permalink / raw)
To: Dingchen Zhang; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
URL : https://patchwork.freedesktop.org/series/62649/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6334_full -> IGTPW_3192_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/62649/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_3192_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#110913 ]) +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl4/igt@gem_eio@in-flight-contexts-10ms.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl4/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@reset-stress:
- shard-kbl: [PASS][5] -> [FAIL][6] ([fdo#109661])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl2/igt@gem_eio@reset-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl7/igt@gem_eio@reset-stress.html
* igt@gem_exec_reloc@basic-gtt-active:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) +6 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl7/igt@gem_exec_reloc@basic-gtt-active.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl2/igt@gem_exec_reloc@basic-gtt-active.html
* igt@gem_partial_pwrite_pread@reads:
- shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#110789] / [fdo#110913 ]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw5/igt@gem_partial_pwrite_pread@reads.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw7/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#110789] / [fdo#110913 ]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb4/igt@gem_persistent_relocs@forked-thrashing.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb2/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_softpin@evict-active-interruptible:
- shard-glk: [PASS][13] -> [DMESG-WARN][14] ([fdo#110913 ]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk8/igt@gem_softpin@evict-active-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk3/igt@gem_softpin@evict-active-interruptible.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([fdo#110913 ]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb6/igt@gem_tiled_partial_pwrite_pread@writes.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb7/igt@gem_tiled_partial_pwrite_pread@writes.html
* igt@gem_tiled_wc:
- shard-glk: [PASS][17] -> [INCOMPLETE][18] ([fdo#103359] / [k.org#198133])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk9/igt@gem_tiled_wc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk7/igt@gem_tiled_wc.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([fdo#110913 ])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw8/igt@gem_userptr_blits@sync-unmap-cycles.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw4/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb5/igt@i915_pm_rc6_residency@rc6-accuracy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb7/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-hsw: [PASS][23] -> [SKIP][24] ([fdo#109271]) +9 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-c-forked-move:
- shard-hsw: [PASS][25] -> [INCOMPLETE][26] ([fdo#103540])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw4/igt@kms_cursor_legacy@pipe-c-forked-move.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw8/igt@kms_cursor_legacy@pipe-c-forked-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][27] -> [FAIL][28] ([fdo#103167]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][29] -> [FAIL][30] ([fdo#103166])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][31] -> [FAIL][32] ([fdo#108341])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb2/igt@kms_psr@no_drrs.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][35] -> [FAIL][36] ([fdo#99912])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl4/igt@kms_setmode@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl1/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#100047])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb7/igt@kms_sysfs_edid_timing.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb2/igt@kms_sysfs_edid_timing.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][39] ([fdo#110854]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb3/igt@gem_exec_balancer@smoke.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb1/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-apl: [DMESG-WARN][41] ([fdo#110913 ]) -> [PASS][42] +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl6/igt@gem_exec_reloc@basic-write-gtt-active.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl3/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_mmap_gtt@hang:
- shard-kbl: [DMESG-WARN][43] ([fdo#110913 ]) -> [PASS][44] +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl6/igt@gem_mmap_gtt@hang.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl3/igt@gem_mmap_gtt@hang.html
- shard-snb: [INCOMPLETE][45] ([fdo#105411]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb5/igt@gem_mmap_gtt@hang.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb6/igt@gem_mmap_gtt@hang.html
- shard-iclb: [DMESG-WARN][47] ([fdo#110913 ]) -> [PASS][48] +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb2/igt@gem_mmap_gtt@hang.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb5/igt@gem_mmap_gtt@hang.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-hsw: [DMESG-WARN][49] ([fdo#110789] / [fdo#110913 ]) -> [PASS][50] +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw6/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_softpin@softpin:
- shard-snb: [DMESG-WARN][51] ([fdo#110789] / [fdo#110913 ]) -> [PASS][52] +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb6/igt@gem_softpin@softpin.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb2/igt@gem_softpin@softpin.html
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: [FAIL][53] ([fdo#108686]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb7/igt@gem_tiled_swapping@non-threaded.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb6/igt@gem_tiled_swapping@non-threaded.html
- shard-glk: [DMESG-WARN][55] ([fdo#108686]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk3/igt@gem_tiled_swapping@non-threaded.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk9/igt@gem_tiled_swapping@non-threaded.html
- shard-apl: [DMESG-WARN][57] ([fdo#108686]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl6/igt@gem_tiled_swapping@non-threaded.html
- shard-snb: [DMESG-WARN][59] ([fdo#110853]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb6/igt@gem_tiled_swapping@non-threaded.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb1/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-glk: [DMESG-WARN][61] ([fdo#110913 ]) -> [PASS][62] +5 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
- shard-snb: [DMESG-WARN][63] ([fdo#110913 ]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
- shard-hsw: [DMESG-WARN][65] ([fdo#110913 ]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [INCOMPLETE][67] ([fdo#107713] / [fdo#108569] / [fdo#110331]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb8/igt@i915_selftest@live_hangcheck.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb7/igt@i915_selftest@live_hangcheck.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-iclb: [FAIL][71] ([fdo#108134]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb1/igt@kms_flip_tiling@flip-to-x-tiled.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb3/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-hsw: [SKIP][73] ([fdo#109271]) -> [PASS][74] +23 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render:
- shard-glk: [FAIL][75] ([fdo#103167]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-glk6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][77] ([fdo#103167]) -> [PASS][78] +5 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][79] ([fdo#109441]) -> [PASS][80] +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-iclb5/igt@kms_psr@psr2_no_drrs.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][81] ([fdo#99912]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-kbl2/igt@kms_setmode@basic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-kbl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-query-busy-hang:
- shard-snb: [SKIP][83] ([fdo#109271]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb4/igt@kms_vblank@pipe-b-query-busy-hang.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb5/igt@kms_vblank@pipe-b-query-busy-hang.html
#### Warnings ####
* igt@kms_atomic_transition@4x-modeset-transitions:
- shard-snb: [SKIP][85] ([fdo#109271]) -> [SKIP][86] ([fdo#109271] / [fdo#109278])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6334/shard-snb4/igt@kms_atomic_transition@4x-modeset-transitions.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/shard-snb1/igt@kms_atomic_transition@4x-modeset-transitions.html
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110331]: https://bugs.freedesktop.org/show_bug.cgi?id=110331
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110853]: https://bugs.freedesktop.org/show_bug.cgi?id=110853
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 6)
------------------------------
Missing (4): pig-skl-6260u shard-skl pig-hsw-4770r pig-glk-j5005
Build changes
-------------
* IGT: IGT_5065 -> IGTPW_3192
* Piglit: piglit_4509 -> None
CI_DRM_6334: 86d1a866f35634912d7699f1eb4d04a2007df18e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3192: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/
IGT_5065: f454000b5ba221b19d696a27415fe5824d743284 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3192/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC.
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
` (5 preceding siblings ...)
2019-06-25 6:54 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
@ 2019-06-25 16:20 ` Kazlauskas, Nicholas
6 siblings, 0 replies; 11+ messages in thread
From: Kazlauskas, Nicholas @ 2019-06-25 16:20 UTC (permalink / raw)
To: Zhang, Dingchen (David), igt-dev@lists.freedesktop.org
On 6/24/19 10:31 AM, Dingchen Zhang wrote:
> Need framebuffer CRC to validate AMDGPU bypass mode.
>
> For each color component less than 16-bits, padding zero bits,
> loop to update CRC for each RGB compoment in the framebuffer.
> The algorithm is based on DP spec v1.4.
>
> Cc: Harry Wentland <Harry.Wentland@amd.com>
> Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Change-Id: Ifc2076df6c9b2156db23cae7ad968c61f404d0e4
Drop the Change-Id's from these patches.
> Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
> ---
> lib/igt_fb.c | 195 +++++++++++++++++++++++++++++++++++++++++++++++++++
> lib/igt_fb.h | 2 +
> 2 files changed, 197 insertions(+)
>
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 9d4f905e..2ac943c0 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -65,6 +65,7 @@
> */
>
> #define PIXMAN_invalid 0
> +#define CRC_INIT_16 0x0000
Drop this define, it's only used within the CRC function itself and it's
just zero.
>
> #if CAIRO_VERSION < CAIRO_VERSION_ENCODE(1, 17, 2)
> /*
> @@ -903,6 +904,200 @@ int igt_create_bo_with_dimensions(int fd, int width, int height,
> return fb.gem_handle;
> }
>
> +#define get_u16_bit(x, n) ((x & (1 << n)) >> n )
> +#define set_u16_bit(x, n, val) ((x & ~(1 << n)) | (val << n))
> +/*
> + * update_crc16_dp:
> + * @crc_old: old 16-bit CRC value to be updated
> + * @d: input 16-bit data on which to calculate 16-bit CRC
> + *
> + * CRC algorithm implementation described in DP 1.4 spec Appendix J
> + * the 16-bit CRC IBM is applied, with the following polynomial:
> + *
> + * f(x) = x ^ 16 + x ^ 15 + x ^ 2 + 1
> + *
> + * the MSB is shifted in first, for any color format that is less than 16 bits
> + * per component, the LSB is zero-padded.
> + *
> + * The following implementation is based on the hardware parallel 16-bit CRC
> + * generation and ported to C code.
> + *
> + * Reference: VESA DisplayPort Standard v1.4, appendix J
> + *
> + * Returns:
> + * updated 16-bit CRC value.
> + */
> +static uint16_t update_crc16_dp(uint16_t crc_old, uint16_t d)
> +{
> + uint16_t crc_new = 0; /* 16-bit CRC output */
> +
> + /* internal use */
> + uint16_t b = crc_old;
> + uint8_t val;
> +
> + /* b[15] */
> + val = get_u16_bit(b, 0) ^ get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^
> + get_u16_bit(b, 3) ^ get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^
> + get_u16_bit(b, 6) ^ get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^
> + get_u16_bit(b, 9) ^ get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^
> + get_u16_bit(b, 12) ^ get_u16_bit(b, 14) ^ get_u16_bit(b, 15) ^
> + get_u16_bit(d, 0) ^ get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^
> + get_u16_bit(d, 3) ^ get_u16_bit(d, 4) ^ get_u16_bit(d, 5) ^
> + get_u16_bit(d, 6) ^ get_u16_bit(d, 7) ^ get_u16_bit(d, 8) ^
> + get_u16_bit(d, 9) ^ get_u16_bit(d, 10) ^ get_u16_bit(d, 11) ^
> + get_u16_bit(d, 12) ^ get_u16_bit(d, 14) ^ get_u16_bit(d, 15);
> + crc_new = set_u16_bit(crc_new, 15, val);
> +
> + /* b[14] */
> + val = get_u16_bit(b, 12) ^ get_u16_bit(b, 13) ^
> + get_u16_bit(d, 12) ^ get_u16_bit(d, 13);
> + crc_new = set_u16_bit(crc_new, 14, val);
> +
> + /* b[13] */
> + val = get_u16_bit(b, 11) ^ get_u16_bit(b, 12) ^
> + get_u16_bit(d, 11) ^ get_u16_bit(d, 12);
> + crc_new = set_u16_bit(crc_new, 13, val);
> +
> + /* b[12] */
> + val = get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^
> + get_u16_bit(d, 10) ^ get_u16_bit(d, 11);
> + crc_new = set_u16_bit(crc_new, 12, val);
> +
> + /* b[11] */
> + val = get_u16_bit(b, 9) ^ get_u16_bit(b, 10) ^
> + get_u16_bit(d, 9) ^ get_u16_bit(d, 10);
> + crc_new = set_u16_bit(crc_new, 11, val);
> +
> + /* b[10] */
> + val = get_u16_bit(b, 8) ^ get_u16_bit(b, 9) ^
> + get_u16_bit(d, 8) ^ get_u16_bit(d, 9);
> + crc_new = set_u16_bit(crc_new, 10, val);
> +
> + /* b[9] */
> + val = get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^
> + get_u16_bit(d, 7) ^ get_u16_bit(d, 8);
> + crc_new = set_u16_bit(crc_new, 9, val);
> +
> + /* b[8] */
> + val = get_u16_bit(b, 6) ^ get_u16_bit(b, 7) ^
> + get_u16_bit(d, 6) ^ get_u16_bit(d, 7);
> + crc_new = set_u16_bit(crc_new, 8, val);
> +
> + /* b[7] */
> + val = get_u16_bit(b, 5) ^ get_u16_bit(b, 6) ^
> + get_u16_bit(d, 5) ^ get_u16_bit(d, 6);
> + crc_new = set_u16_bit(crc_new, 7, val);
> +
> + /* b[6] */
> + val = get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^
> + get_u16_bit(d, 4) ^ get_u16_bit(d, 5);
> + crc_new = set_u16_bit(crc_new, 6, val);
> +
> + /* b[5] */
> + val = get_u16_bit(b, 3) ^ get_u16_bit(b, 4) ^
> + get_u16_bit(d, 3) ^ get_u16_bit(d, 4);
> + crc_new = set_u16_bit(crc_new, 5, val);
> +
> + /* b[4] */
> + val = get_u16_bit(b, 2) ^ get_u16_bit(b, 3) ^
> + get_u16_bit(d, 2) ^ get_u16_bit(d, 3);
> + crc_new = set_u16_bit(crc_new, 4, val);
> +
> + /* b[3] */
> + val = get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^ get_u16_bit(b, 15) ^
> + get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^ get_u16_bit(d, 15);
> + crc_new = set_u16_bit(crc_new, 3, val);
> +
> + /* b[2] */
> + val = get_u16_bit(b, 0) ^ get_u16_bit(b, 1) ^ get_u16_bit(b, 14) ^
> + get_u16_bit(d, 0) ^ get_u16_bit(d, 1) ^ get_u16_bit(d, 14);
> + crc_new = set_u16_bit(crc_new, 2, val);
> +
> + /* b[1] */
> + val = get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^ get_u16_bit(b, 3) ^
> + get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^ get_u16_bit(b, 6) ^
> + get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^ get_u16_bit(b, 9) ^
> + get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^ get_u16_bit(b, 12) ^
> + get_u16_bit(b, 13) ^ get_u16_bit(b, 14) ^
> + get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^ get_u16_bit(d, 3) ^
> + get_u16_bit(d, 4) ^ get_u16_bit(d, 5) ^ get_u16_bit(d, 6) ^
> + get_u16_bit(d, 7) ^ get_u16_bit(d, 8) ^ get_u16_bit(d, 9) ^
> + get_u16_bit(d, 10) ^ get_u16_bit(d, 11) ^ get_u16_bit(d, 12) ^
> + get_u16_bit(d, 13) ^ get_u16_bit(d, 14);
> + crc_new = set_u16_bit(crc_new, 1, val);
> +
> + /* b[0] */
> + val = get_u16_bit(b, 0) ^ get_u16_bit(b, 1) ^ get_u16_bit(b, 2) ^
> + get_u16_bit(b, 3) ^ get_u16_bit(b, 4) ^ get_u16_bit(b, 5) ^
> + get_u16_bit(b, 6) ^ get_u16_bit(b, 7) ^ get_u16_bit(b, 8) ^
> + get_u16_bit(b, 9) ^ get_u16_bit(b, 10) ^ get_u16_bit(b, 11) ^
> + get_u16_bit(b, 12) ^ get_u16_bit(b, 13) ^ get_u16_bit(b, 15) ^
> + get_u16_bit(d, 0) ^ get_u16_bit(d, 1) ^ get_u16_bit(d, 2) ^
> + get_u16_bit(d, 3) ^ get_u16_bit(d, 4) ^ get_u16_bit(d, 5) ^
> + get_u16_bit(d, 6) ^ get_u16_bit(d, 7) ^ get_u16_bit(d, 8) ^
> + get_u16_bit(d, 9) ^ get_u16_bit(d, 10) ^ get_u16_bit(d, 11) ^
> + get_u16_bit(d, 12) ^ get_u16_bit(d, 13) ^ get_u16_bit(d, 15);
> + crc_new = set_u16_bit(crc_new, 0, val);
> +
> + return crc_new;
> +}
This is quite verbose, but matching the spec is better than trying to be
overly aggressive with optimization. I'm fine with this.
> +
> +/**
> + * igt_fb_calc_crc:
> + * @fb: pointer to an #igt_fb structure
> + * @crc: pointer to an #igt_crc_t structure
> + *
> + * This function calculate the 16-bit frame CRC of RGB components over all
> + * the active pixels.
> + */
> +void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc)
> +{
> + int x, y, i;
> + void *ptr;
> + uint8_t *data;
> + uint16_t din;
> +
> + igt_assert(fb && crc);
> +
> + ptr = igt_fb_map_buffer(fb->fd, fb);
> + igt_assert(ptr);
> +
> + /* set for later CRC comparison */
> + crc->has_valid_frame = true;
> + crc->frame = 0;
> + crc->n_words = 3;
> + crc->crc[0] = CRC_INIT_16; /* R */
> + crc->crc[1] = CRC_INIT_16; /* G */
> + crc->crc[2] = CRC_INIT_16; /* B */
> +
> + data = ptr + fb->offsets[0];
> + for (y = 0; y < fb->height; ++y) {
> + for (x = 0; x < fb->width; ++x) {
> + switch (fb->drm_format) {
> + case DRM_FORMAT_XRGB8888:
> + i = x * 4 + y * fb->strides[0];
> +
> + din = data[i + 2] << 8; /* padding-zeros */
> + crc->crc[0] = update_crc16_dp(crc->crc[0], din);
> +
> + /* Green-component */
> + din = data[i + 1] << 8;
> + crc->crc[1] = update_crc16_dp(crc->crc[1], din);
> +
> + /* Blue-component */
> + din = data[i] << 8;
> + crc->crc[2] = update_crc16_dp(crc->crc[2], din);
> + break;
> + default:
> + igt_assert_f(0, "DRM Format Invalid");
> + break;
> + }
> + }
> + }
> +
> + igt_fb_unmap_buffer(fb, ptr);
> +}
> +
> /**
> * igt_paint_color:
> * @cr: cairo drawing context
> diff --git a/lib/igt_fb.h b/lib/igt_fb.h
> index adefebe1..be786911 100644
> --- a/lib/igt_fb.h
> +++ b/lib/igt_fb.h
> @@ -37,6 +37,7 @@
> #include <i915_drm.h>
>
> #include "igt_color_encoding.h"
> +#include "igt_debugfs.h"
This include really only needs to be within igt_fb.c itself as long as
you forward declare igt_crc_t, but you'd need igt_debugfs.h to really
use the igt_crc_t anyway.
I guess it's fine to have to it here.
>
> /*
> * Internal format to denote a buffer compatible with pixman's
> @@ -158,6 +159,7 @@ int igt_create_bo_with_dimensions(int fd, int width, int height, uint32_t format
> uint64_t modifier, unsigned stride,
> uint64_t *size_ret, unsigned *stride_ret,
> bool *is_dumb);
> +void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc);
>
> uint64_t igt_fb_mod_to_tiling(uint64_t modifier);
> uint64_t igt_fb_tiling_to_mod(uint64_t tiling);
>
With the fixes I've mentioned, this change is:
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Nicholas Kazlauskas
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/4] lib/igt_debugfs: add AMDGPU pipe crc sources
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_debugfs: add AMDGPU pipe crc sources Dingchen Zhang
@ 2019-06-25 16:23 ` Kazlauskas, Nicholas
0 siblings, 0 replies; 11+ messages in thread
From: Kazlauskas, Nicholas @ 2019-06-25 16:23 UTC (permalink / raw)
To: Zhang, Dingchen (David), igt-dev@lists.freedesktop.org
On 6/24/19 10:31 AM, Dingchen Zhang wrote:
> Need different pipe CRC sources to validate AMDGPU
> digital bypass mode.
>
> Added available AMDGPU pipe crc sources in igt_debugfs.h
>
> Cc: Harry Wentland <Harry.Wentland@amd.com>
> Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Change-Id: Ia6c9ccb7a904ec8a490e519425c006ae2ea95a9b
Drop the Change-ID.
> Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
> ---
> lib/igt_debugfs.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
> index 52520b3c..b49dd2b6 100644
> --- a/lib/igt_debugfs.h
> +++ b/lib/igt_debugfs.h
> @@ -83,6 +83,9 @@ typedef struct {
> } igt_crc_t;
>
> #define INTEL_PIPE_CRC_SOURCE_AUTO "auto"
> +#define AMDGPU_PIPE_CRC_SOURCE_AUTO "auto"
> +#define AMDGPU_PIPE_CRC_SOURCE_CRTC "crtc"
We can probably just drop the "auto" and "crtc" defines here if we're
not using them. Yes, it's a little strange that we're using the
INTEL_PIPE_CRC_SOURCE_AUTO for every test, but it's already the convention.
The DPRX one below is fine.
Maybe just make the patch title "Add DPRX CRC source for AMDGPU" with
that change.
Nicholas Kazlauskas
> +#define AMDGPU_PIPE_CRC_SOURCE_DPRX "dprx"
>
> void igt_assert_crc_equal(const igt_crc_t *a, const igt_crc_t *b);
> bool igt_check_crc_equal(const igt_crc_t *a, const igt_crc_t *b);
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_debugfs: add function to set pipe crc source name.
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 3/4] lib/igt_debugfs: add function to set pipe crc source name Dingchen Zhang
@ 2019-06-25 16:26 ` Kazlauskas, Nicholas
0 siblings, 0 replies; 11+ messages in thread
From: Kazlauskas, Nicholas @ 2019-06-25 16:26 UTC (permalink / raw)
To: Zhang, Dingchen (David), igt-dev@lists.freedesktop.org
On 6/24/19 10:31 AM, Dingchen Zhang wrote:
> need to get CRC from different pipe crc source. >
> frees the existed pipe crc source and replace it with the new.
This patch works for changing the CRC source dynamically but I don't
think we actually need this for anything right now.
Might be better to just leave this be for now.
Nicholas Kazlauskas
>
> Cc: Harry Wentland <Harry.Wentland@amd.com>
> Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Change-Id: I41edae38f6c11525722295e975e77e497344ea71
> Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
> ---
> lib/igt_debugfs.c | 15 +++++++++++++++
> lib/igt_debugfs.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
> index 82ce1834..6dd7c537 100644
> --- a/lib/igt_debugfs.c
> +++ b/lib/igt_debugfs.c
> @@ -994,6 +994,21 @@ void igt_pipe_crc_collect_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc)
> igt_pipe_crc_stop(pipe_crc);
> }
>
> +/**
> + * igt_pipe_crc_set_source:
> + * @pipe_crc: pipe CRC object
> + * @src: pipe CRC source name
> + *
> + * The functions frees the current existed pipe CRC source name and replace
> + * it with the new given name 'source'
> + */
> +void igt_pipe_crc_set_source(igt_pipe_crc_t *pipe_crc, const char *src)
> +{
> + free(pipe_crc->source);
> + pipe_crc->source = strdup(src);
> + igt_assert(pipe_crc->source);
> +}
> +
> /**
> * igt_reset_fifo_underrun_reporting:
> * @drm_fd: drm device file descriptor
> diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
> index b49dd2b6..640ec248 100644
> --- a/lib/igt_debugfs.h
> +++ b/lib/igt_debugfs.h
> @@ -108,6 +108,7 @@ void igt_pipe_crc_get_single(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc);
> void igt_pipe_crc_get_current(int drm_fd, igt_pipe_crc_t *pipe_crc, igt_crc_t *crc);
>
> void igt_pipe_crc_collect_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc);
> +void igt_pipe_crc_set_source(igt_pipe_crc_t *pipe_crc, const char *src);
>
> void igt_hpd_storm_set_threshold(int fd, unsigned int threshold);
> void igt_hpd_storm_reset(int fd);
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 4/4] tests/amdgpu: add 8bpc bypass mode test.
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 4/4] tests/amdgpu: add 8bpc bypass mode test Dingchen Zhang
@ 2019-06-25 16:29 ` Kazlauskas, Nicholas
0 siblings, 0 replies; 11+ messages in thread
From: Kazlauskas, Nicholas @ 2019-06-25 16:29 UTC (permalink / raw)
To: Zhang, Dingchen (David), igt-dev@lists.freedesktop.org
On 6/24/19 10:31 AM, Dingchen Zhang wrote:
> To validate the AMDGPU bypass mode feature.
>
> Generate DP test patterns, program the pipe and check if
> the CRCs of framebuffer and DP receiver match.
>
> Cc: Harry Wentland <Harry.Wentland@amd.com>
> Cc: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Change-Id: I5748f10188351399bb25c4fbacfd16ac66850877
> Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
> ---
> tests/amdgpu/amd_bypass.c | 383 ++++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 384 insertions(+)
> create mode 100644 tests/amdgpu/amd_bypass.c
>
> diff --git a/tests/amdgpu/amd_bypass.c b/tests/amdgpu/amd_bypass.c
> new file mode 100644
> index 00000000..17a67422
> --- /dev/null
> +++ b/tests/amdgpu/amd_bypass.c
> @@ -0,0 +1,383 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Author: AMD
I don't think we really need the Author: note here.
> + */
> +#include "drm.h"
> +#include "drmtest.h"
> +#include "igt.h"
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include "signal.h"
> +
> +/*
> + * internal use
> + * Common test data
> + * */
> +typedef struct {
> + int drm_fd;
> + int width;
> + int height;
> + enum pipe pipe_id;
> + igt_display_t display;
> + igt_plane_t *primary;
> + igt_output_t *output;
> + igt_pipe_t *pipe;
> + igt_pipe_crc_t *pipe_crc;
> + igt_crc_t crc_fb;
> + igt_crc_t crc_dprx;
> + drmModeModeInfo *mode;
> +} data_t;
> +
> +enum pattern {
> + TEST_PATTERN_DP_COLOR_RAMP,
> + TEST_PATTERN_DP_BLACK_WHITE_VERT_LINES,
> + TEST_PATTERN_DP_BLACK_WHITE_HORZ_LINES,
> + TEST_PATTERN_DP_COLOR_SQUARES_VESA,
> + /* please don't add pattern after the below line */
> + TEST_PATTERN_MAX,
> +};
> +
> +const char *ptnstr[TEST_PATTERN_MAX] = {
> + "DP Color Ramp",
> + "DP Vertical Lines",
> + "DP Horizontal Lines",
> + "DP Color Squares VESA"
> +};
> +
> +/* Common test setup. */
> +static void test_init(data_t *data)
> +{
> + igt_display_t *display = &data->display;
> +
> + /* It doesn't matter which pipe we choose on amdpgu. */
> + data->pipe_id = PIPE_A;
> + data->pipe = &data->display.pipes[data->pipe_id];
> +
> + igt_display_reset(display);
> +
> + data->output = igt_get_single_output_for_pipe(display, data->pipe_id);
> + igt_assert(data->output);
> +
> + data->mode = igt_output_get_mode(data->output);
> + igt_assert(data->mode);
> +
> + data->primary =
> + igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
> +
> + data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe_id,
> + AMDGPU_PIPE_CRC_SOURCE_AUTO);
> + igt_pipe_crc_set_source(data->pipe_crc, AMDGPU_PIPE_CRC_SOURCE_DPRX);
Just open the source on the AMDGPU_PIPE_CRC_SOURCE_DPRX rather than
changing it immediately after. That way we don't even need
igt_pipe_crc_set_source.
Nicholas Kazlauskas
> +
> + igt_output_set_pipe(data->output, data->pipe_id);
> +
> + data->width = data->mode->hdisplay;
> + data->height = data->mode->vdisplay;
> +}
> +
> +/* Common test cleanup. */
> +static void test_fini(data_t *data)
> +{
> + igt_pipe_crc_free(data->pipe_crc);
> + igt_display_reset(&data->display);
> +}
> +
> +/*
> + * draw the DP color ramp test pattern
> + * Reference: DP Link CTS 1.2 Core r1.1, sec. 3.1.5.1
> + */
> +static void draw_dp_test_pattern_color_ramp(igt_fb_t *fb)
> +{
> + const int h = 64; /* test pattern rectangle height */
> + const int block_h = h * 4; /* block height of R-G-B-White rectangles */
> + void *ptr_fb;
> + uint8_t *data;
> + int x,y;
> + int i;
> + uint8_t val;
> +
> + /*
> + * 64-by-256 pixels per rectangle
> + * R-G-B-White rectangle in order in vertical
> + * duplicate in horizontal
> + */
> + ptr_fb = igt_fb_map_buffer(fb->fd, fb);
> + igt_assert(ptr_fb);
> + data = ptr_fb + fb->offsets[0];
> +
> + for (y = 0; y < fb->height; ++y) {
> + for (x = 0, val = 0; x < fb->width; ++x, ++val) {
> + switch (fb->drm_format) {
> + case DRM_FORMAT_XRGB8888:
Can these switch statements be pulled out of the loop? fb->drm_format
isn't going to change on every pixel. The branch predictor will be fine
with this but it's bit unnecessary.
> + i = x * 4 + y * fb->strides[0];
> +
> + /* vertical R-G-B-White rec */
> + if ((y % block_h) < h) { /* Red */
> + data[i + 2] = val;
> + data[i + 1] = 0;
> + data[i + 0] = 0;
> + } else if ((y % block_h) < 2 * h) { /* Green */
> + data[i + 2] = 0;
> + data[i + 1] = val;
> + data[i + 0] = 0;
> + } else if ((y % block_h) < 3 * h) { /* Blue */
> + data[i + 2] = 0;
> + data[i + 1] = 0;
> + data[i + 0] = val;
> + } else { /* White */
> + data[i + 2] = val;
> + data[i + 1] = val;
> + data[i + 0] = val;
> + }
> + break;
> + default:
> + igt_assert_f(0, "DRM Format Invalid");
> + break;
> + }
> + }
> + }
> +
> + igt_fb_unmap_buffer(fb, ptr_fb);
> +}
> +
> +/*
> + * draw the DP vertical lines test pattern
> + * * Reference: DP Link CTS 1.2 Core r1.1, sec. 3.1.5.2
> + */
> +static void draw_dp_test_pattern_vert_lines(igt_fb_t *fb)
> +{
> + void *ptr_fb;
> + uint8_t *data;
> + int x, y;
> + int i;
> +
> + /* alternating black and white lines, 1 pixel wide */
> + ptr_fb = igt_fb_map_buffer(fb->fd, fb);
> + igt_assert(ptr_fb);
> + data = ptr_fb + fb->offsets[0];
> +
> + for (y = 0; y < fb->height; ++y) {
> + for (x = 0; x < fb->width; ++x) {
> + switch (fb->drm_format) {
> + case DRM_FORMAT_XRGB8888:
> + i = x * 4 + y * fb->strides[0];
> +
> + if ((x & 1) == 0) {
> + data[i + 2] = 0xff; /* R */
> + data[i + 1] = 0xff; /* G */
> + data[i + 0] = 0xff; /* B */
> + }
> + else {
> + data[i + 2] = 0;
> + data[i + 1] = 0;
> + data[i + 0] = 0;
> + }
> + break;
> + default:
> + igt_assert_f(0, "DRM Format Invalid");
> + break;
> + }
> + }
> + }
> +
> + igt_fb_unmap_buffer(fb, ptr_fb);
> +}
> +
> +/* draw the DP horizontal lines test pattern */
> +static void draw_dp_test_pattern_horz_lines(igt_fb_t *fb)
> +{
> + void *ptr_fb;
> + uint8_t *data;
> + int x, y;
> + int i;
> +
> + /* alternating black and white horizontal lines, 1 pixel high */
> + ptr_fb = igt_fb_map_buffer(fb->fd, fb);
> + igt_assert(ptr_fb);
> + data = ptr_fb + fb->offsets[0];
> +
> + for (y = 0; y < fb->height; ++y) {
> + for (x = 0; x < fb->width; ++x) {
> + switch (fb->drm_format) {
> + case DRM_FORMAT_XRGB8888:
> + i = x * 4 + y * fb->strides[0];
> +
> + if ((y & 1) == 0) {
> + data[i + 2] = 0xff; /* R */
> + data[i + 1] = 0xff; /* G */
> + data[i + 0] = 0xff; /* B */
> + }
> + else {
> + data[i + 2] = 0;
> + data[i + 1] = 0;
> + data[i + 0] = 0;
> + }
> + break;
> + default:
> + igt_assert_f(0, "DRM Format Invalid");
> + break;
> + }
> + }
> + }
> +
> + igt_fb_unmap_buffer(fb, ptr_fb);
> +}
> +
> +/*
> + * draw the DP color squares VESA test pattern
> + * Reference: DP Link CTS 1.2 Core r1.1, sec. 3.1.5.3
> + */
> +static void draw_dp_test_pattern_color_squares_vesa(igt_fb_t *fb)
> +{
> + const int h = 64; /* test pattern square height/width */
> + const int block_h = h * 2; /* block height of the repetition pattern */
> + const int block_w = h * 8; /* block width of the repetition pattern */
> + const uint8_t rgb[3][2][8] = {
> + {/* Red table of the pattern squares */
> + {255, 255, 0, 0, 255, 255, 0, 0},
> + {0, 255, 255, 0, 0, 255, 255, 0},
> + },
> + {/* Green table */
> + {255, 255, 255, 255, 0, 0, 0, 0},
> + {0, 0, 0, 255, 255, 255, 255, 0},
> + },
> + {/* Blue table */
> + {255, 0, 255, 0, 255, 0, 255, 0},
> + {255, 0, 255, 0, 255, 0, 255, 0},
> + },
> + };
> +
> + void *ptr_fb;
> + uint8_t *data;
> + int x, y;
> + int i, j, k;
> +
> + ptr_fb = igt_fb_map_buffer(fb->fd, fb);
> + igt_assert(ptr_fb);
> + data = ptr_fb + fb->offsets[0];
> +
> + for (y = 0; y < fb->height; ++y) {
> + for (x = 0; x < fb->width; ++x) {
> + switch (fb->drm_format) {
> + case DRM_FORMAT_XRGB8888:
> + i = x * 4 + y * fb->strides[0];
> + j = (y % block_h) / h;
> + k = (x % block_w) / h;
> +
> + data[i + 2] = rgb[0][j][k]; /* R */
> + data[i + 1] = rgb[1][j][k]; /* G */
> + data[i + 0] = rgb[2][j][k]; /* B */
> + break;
> + default:
> + igt_assert_f(0, "DRM Format Invalid");
> + break;
> + }
> + }
> + }
> +
> + igt_fb_unmap_buffer(fb, ptr_fb);
> +}
> +
> +/* generate test pattern and fills a FB */
> +static void generate_test_pattern(igt_fb_t *fb, data_t *data, enum pattern ptn)
> +{
> + igt_assert(fb->fd && (ptn < TEST_PATTERN_MAX));
> +
> + if (ptn == TEST_PATTERN_DP_COLOR_RAMP) {
> + draw_dp_test_pattern_color_ramp(fb);
> + } else if (ptn == TEST_PATTERN_DP_BLACK_WHITE_VERT_LINES) {
> + draw_dp_test_pattern_vert_lines(fb);
> + } else if (ptn == TEST_PATTERN_DP_BLACK_WHITE_HORZ_LINES) {
> + draw_dp_test_pattern_horz_lines(fb);
> + } else if (ptn == TEST_PATTERN_DP_COLOR_SQUARES_VESA) {
> + draw_dp_test_pattern_color_squares_vesa(fb);
> + }
> +}
> +
> +static void bypass_8bpc_test(data_t *data)
> +{
> + igt_display_t *display = &data->display;
> + igt_fb_t fb;
> + enum pattern ptn;
> +
> + test_init(data);
> +
> + igt_create_fb(data->drm_fd, data->width, data->height,
> + DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE, &fb);
> +
> + /*
> + * Settings:
> + * no degamma
> + * no regamma
> + * no CTM
> + */
> + igt_pipe_obj_replace_prop_blob(data->pipe, IGT_CRTC_DEGAMMA_LUT, NULL, 0);
> + igt_pipe_obj_replace_prop_blob(data->pipe, IGT_CRTC_GAMMA_LUT, NULL, 0);
> + igt_pipe_obj_replace_prop_blob(data->pipe, IGT_CRTC_CTM, NULL, 0);
> +
> + igt_plane_set_fb(data->primary, &fb);
> + igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
> +
> + /* traverse all the test pattern to validate 8bpc bypass mode */
> + for (ptn = TEST_PATTERN_DP_COLOR_RAMP; ptn < TEST_PATTERN_MAX; ++ptn) {
> + igt_debug("Test Pattern: %s\n", ptnstr[ptn]);
> +
> + generate_test_pattern(&fb, data, ptn);
> +
> + /* Grab FB and DPRX CRCs and compare */
> + igt_fb_calc_crc(&fb, &data->crc_fb);
> + igt_pipe_crc_collect_crc(data->pipe_crc, &data->crc_dprx);
> +
> + igt_assert_crc_equal(&data->crc_fb, &data->crc_dprx);
> + }
> +
> + igt_plane_set_fb(data->primary, NULL);
> + test_fini(data);
> + igt_remove_fb(data->drm_fd, &fb);
> +}
> +
> +igt_main
> +{
> + data_t data;
> + memset(&data, 0, sizeof(data));
> +
> + igt_skip_on_simulation();
> +
> + igt_fixture {
> + data.drm_fd = drm_open_driver_master(DRIVER_AMDGPU);
> + if (data.drm_fd == -1)
> + igt_skip("Not an amdgpu driver.\n");
> + igt_require_pipe_crc(data.drm_fd);
> +
> + kmstest_set_vt_graphics_mode();
> +
> + igt_display_require(&data.display, data.drm_fd);
> + igt_require(data.display.is_atomic);
> + igt_display_require_output(&data.display);
> + }
> +
> + igt_subtest("8bpc-bypass-mode")
> + bypass_8bpc_test(&data);
> +
> + igt_fixture {
> + igt_display_fini(&data.display);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 42086374..b7982291 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -4,6 +4,7 @@ amdgpu_deps = test_deps
> if libdrm_amdgpu.found()
> amdgpu_progs += [ 'amd_abm',
> 'amd_basic',
> + 'amd_bypass',
> 'amd_color',
> 'amd_cs_nop',
> 'amd_prime',
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-06-25 16:29 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-06-24 14:31 [igt-dev] [PATCH i-g-t 1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Dingchen Zhang
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_debugfs: add AMDGPU pipe crc sources Dingchen Zhang
2019-06-25 16:23 ` Kazlauskas, Nicholas
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 3/4] lib/igt_debugfs: add function to set pipe crc source name Dingchen Zhang
2019-06-25 16:26 ` Kazlauskas, Nicholas
2019-06-24 14:31 ` [igt-dev] [PATCH i-g-t 4/4] tests/amdgpu: add 8bpc bypass mode test Dingchen Zhang
2019-06-25 16:29 ` Kazlauskas, Nicholas
2019-06-24 15:48 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib/igt_fb: add functionality of getting framebuffer 16-bit CRC Patchwork
2019-06-24 19:05 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2019-06-25 6:54 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
2019-06-25 16:20 ` [igt-dev] [PATCH i-g-t 1/4] " Kazlauskas, Nicholas
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