[igt-dev] [PATCH i-g-t v2 0/4] Basic LMEM support in IGT

[igt-dev] [PATCH i-g-t v2 0/4] Basic LMEM support in IGT

[Zbigniew Kempczyński]

This is second version of LMEM enabling in IGT.

v2: Refactoring, addressing issues from previous review.
    Fixing bugs in tests.

Cc: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Lukasz Kalamarz (4):
  lib/i915/gem_mman: add mmap_offset support
  lib/i915/intel_memory_region: Add lib to manage memory regions
  tests/i915/gem_mmap_offset: Add new API test for gem_mmap_offset
  tests/i915/gem_exec_basic: Iterate over all memory regions

 lib/Makefile.sources           |   2 +
 lib/i915/gem_mman.c            | 178 +++++++++++++++-----
 lib/i915/gem_mman.h            |  39 ++++-
 lib/i915/intel_memory_region.c | 295 +++++++++++++++++++++++++++++++++
 lib/i915/intel_memory_region.h | 139 ++++++++++++++++
 lib/ioctl_wrappers.h           |   1 +
 lib/meson.build                |   1 +
 tests/Makefile.sources         |   3 +
 tests/i915/gem_exec_basic.c    | 109 +++++++-----
 tests/i915/gem_mmap_offset.c   | 156 +++++++++++++++++
 tests/meson.build              |   1 +
 11 files changed, 845 insertions(+), 79 deletions(-)
 create mode 100644 lib/i915/intel_memory_region.c
 create mode 100644 lib/i915/intel_memory_region.h
 create mode 100644 tests/i915/gem_mmap_offset.c

-- 
2.23.0

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[igt-dev] [PATCH i-g-t v2 1/4] lib/i915/gem_mman: add mmap_offset support

[Zbigniew Kempczyński]

From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>

With introduction of LMEM concept new IOCTL call were implemented
- gem_mmap_offset. This patch add support in IGT for it.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 lib/i915/gem_mman.c | 178 ++++++++++++++++++++++++++++++++++----------
 lib/i915/gem_mman.h |  39 +++++++++-
 2 files changed, 177 insertions(+), 40 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 6256627b..920f9ca5 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -40,6 +40,44 @@
 #define VG(x) do {} while (0)
 #endif
 
+#define LOCAL_I915_PARAM_MMAP_OFFSET_VERSION 54
+
+static bool gem_has_mmap_offset(int fd)
+{
+	int has_mmap_offset = 0;
+	struct drm_i915_getparam gp;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = LOCAL_I915_PARAM_MMAP_OFFSET_VERSION;
+	gp.value = &has_mmap_offset;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	return has_mmap_offset > 0;
+}
+
+void gem_require_mmap_offset(int i915)
+{
+	igt_require(gem_has_mmap_offset(i915));
+}
+
+static int gem_mmap_gtt_version(int fd)
+{
+	struct drm_i915_getparam gp;
+	int gtt_version = -1;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = I915_PARAM_MMAP_GTT_VERSION;
+	gp.value = &gtt_version;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	return gtt_version;
+}
+
+bool gem_mmap_has_gtt(int fd)
+{
+	return gem_mmap_gtt_version(fd) > 0;
+}
+
 /**
  * __gem_mmap__gtt:
  * @fd: open i915 drm file descriptor
@@ -101,46 +139,63 @@ int gem_munmap(void *ptr, uint64_t size)
 	return ret;
 }
 
-bool gem_mmap__has_wc(int fd)
+bool __gem_mmap__has_wc(int fd)
 {
-	static int has_wc = -1;
-
-	if (has_wc == -1) {
-		struct drm_i915_getparam gp;
-		int mmap_version = -1;
-		int gtt_version = -1;
-
-		has_wc = 0;
-
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_GTT_VERSION;
-		gp.value = &gtt_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_VERSION;
-		gp.value = &mmap_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-		/* Do we have the new mmap_ioctl with DOMAIN_WC? */
-		if (mmap_version >= 1 && gtt_version >= 2) {
-			struct drm_i915_gem_mmap arg;
-
-			/* Does this device support wc-mmaps ? */
-			memset(&arg, 0, sizeof(arg));
-			arg.handle = gem_create(fd, 4096);
-			arg.offset = 0;
-			arg.size = 4096;
-			arg.flags = I915_MMAP_WC;
-			has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
-			gem_close(fd, arg.handle);
-		}
-		errno = 0;
+	int has_wc = 0;
+
+	struct drm_i915_getparam gp;
+	int mmap_version = -1;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = I915_PARAM_MMAP_VERSION;
+	gp.value = &mmap_version;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	/* Do we have the mmap_ioctl with DOMAIN_WC? */
+	if (mmap_version >= 1 && gem_mmap_gtt_version(fd) >= 2) {
+		struct drm_i915_gem_mmap arg;
+
+		/* Does this device support wc-mmaps ? */
+		memset(&arg, 0, sizeof(arg));
+		arg.handle = gem_create(fd, 4096);
+		arg.offset = 0;
+		arg.size = 4096;
+		arg.flags = I915_MMAP_WC;
+		has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
+		gem_close(fd, arg.handle);
+	}
+	errno = 0;
+
+	return has_wc > 0;
+}
+
+bool __gem_mmap_offset__has_wc(int fd)
+{
+	int has_wc = 0;
+
+	if (gem_has_mmap_offset(fd)) {
+		struct local_i915_gem_mmap_offset arg;
+
+		/* Does this device support wc-mmaps ? */
+		memset(&arg, 0, sizeof(arg));
+		arg.handle = gem_create(fd, 4096);
+		arg.offset = 0;
+		arg.flags = LOCAL_I915_MMAP_OFFSET_WC;
+		has_wc = igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET,
+				   &arg) == 0;
+		gem_close(fd, arg.handle);
 	}
 
+	errno = 0;
+
 	return has_wc > 0;
 }
 
+bool gem_mmap__has_wc(int fd)
+{
+	return __gem_mmap_offset__has_wc(fd) || __gem_mmap__has_wc(fd);
+}
+
 /**
  * __gem_mmap:
  * @fd: open i915 drm file descriptor
@@ -157,8 +212,8 @@ bool gem_mmap__has_wc(int fd)
  *
  * Returns: A pointer to the created memory mapping, NULL on failure.
  */
-static void
-*__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned int prot, uint64_t flags)
+void *__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+		 unsigned int prot, uint64_t flags)
 {
 	struct drm_i915_gem_mmap arg;
 
@@ -177,6 +232,43 @@ static void
 	return from_user_pointer(arg.addr_ptr);
 }
 
+/**
+ * __gem_mmap_offset:
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ * @flags: flags used to determine caching
+ *
+ * Similar to __gem_mmap but use MMAP_OFFSET IOCTL.
+ *
+ * Returns: A pointer to the created memory mapping, NULL on failure.
+ */
+void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+			unsigned int prot, uint64_t flags)
+{
+	struct local_i915_gem_mmap_offset arg;
+	void *ptr;
+
+	memset(&arg, 0, sizeof(arg));
+	arg.handle = handle;
+	arg.offset = offset;
+	arg.flags = flags;
+
+	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET, &arg))
+		return NULL;
+
+	ptr = mmap64(0, size, prot, MAP_SHARED, fd, arg.offset);
+
+	if (ptr == MAP_FAILED)
+		ptr = NULL;
+	else
+		errno = 0;
+
+	return ptr;
+}
+
 /**
  * __gem_mmap__wc:
  * @fd: open i915 drm file descriptor
@@ -205,13 +297,17 @@ void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, un
  * @size: size of the mmap arena
  * @prot: memory protection bits as used by mmap()
  *
- * Like __gem_mmap__wc() except we assert on failure.
+ * Try to __gem_mmap_offset, then __gem_mmap__wc(). Assert on failure.
  *
  * Returns: A pointer to the created memory mapping
  */
 void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
 {
-	void *ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
+	void *ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
+				       LOCAL_I915_MMAP_OFFSET_WC);
+	if (!ptr)
+		ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
+
 	igt_assert(ptr);
 	return ptr;
 }
@@ -248,7 +344,11 @@ void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, u
  */
 void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
 {
-	void *ptr = __gem_mmap__cpu(fd, handle, offset, size, prot);
+	void *ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
+				       LOCAL_I915_MMAP_OFFSET_WB);
+	if (!ptr)
+		ptr = __gem_mmap__cpu(fd, handle, offset, size, prot);
+
 	igt_assert(ptr);
 	return ptr;
 }
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 096ff592..e4c954c6 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -25,12 +25,45 @@
 #ifndef GEM_MMAN_H
 #define GEM_MMAN_H
 
+#define LOCAL_I915_GEM_MMAP_OFFSET       DRM_I915_GEM_MMAP_GTT
+#define LOCAL_IOCTL_I915_GEM_MMAP_OFFSET         DRM_IOWR(DRM_COMMAND_BASE + \
+	LOCAL_I915_GEM_MMAP_OFFSET, struct local_i915_gem_mmap_offset)
+
+struct local_i915_gem_mmap_offset {
+	/** Handle for the object being mapped. */
+	__u32 handle;
+	__u32 pad;
+	/**
+	 * Fake offset to use for subsequent mmap call
+	 *
+	 * This is a fixed-size type for 32/64 compatibility.
+	 */
+	__u64 offset;
+	/**
+	 * Flags for extended behaviour.
+	 *
+	 * It is mandatory that either one of the _WC/_WB flags
+	 * should be passed here.
+	 */
+	__u64 flags;
+#define LOCAL_I915_MMAP_OFFSET_WC (1 << 0)
+#define LOCAL_I915_MMAP_OFFSET_WB (1 << 1)
+#define LOCAL_I915_MMAP_OFFSET_UC (1 << 2)
+#define LOCAL_I915_MMAP_OFFSET_FLAGS \
+	(LOCAL_I915_MMAP_OFFSET_WC | LOCAL_I915_MMAP_OFFSET_WB | LOCAL_I915_MMAP_OFFSET_UC)
+};
+
+void gem_require_mmap_offset(int i915);
+bool gem_mmap_has_gtt(int fd);
+
 void *gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned prot);
 void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 
+bool __gem_mmap__has_wc(int fd);
+bool __gem_mmap_offset__has_wc(int fd);
 bool gem_mmap__has_wc(int fd);
 void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
-
+void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 #ifndef I915_GEM_DOMAIN_WC
 #define I915_GEM_DOMAIN_WC 0x80
 #endif
@@ -38,6 +71,10 @@ void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsi
 bool gem_has_mappable_ggtt(int i915);
 void gem_require_mappable_ggtt(int i915);
 
+void *__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+		 unsigned int prot, uint64_t flags);
+void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+			 unsigned int prot, uint64_t flags);
 void *__gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned prot);
 void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
-- 
2.23.0

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Re: [igt-dev] [PATCH i-g-t v2 1/4] lib/i915/gem_mman: add mmap_offset support

[Summers, Stuart]

[-- Attachment #1.1: Type: text/plain, Size: 10771 bytes --]

On Tue, 2019-11-19 at 17:02 +0100, Zbigniew Kempczyński wrote:
> From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
> 
> With introduction of LMEM concept new IOCTL call were implemented
> - gem_mmap_offset. This patch add support in IGT for it.
> 
> Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  lib/i915/gem_mman.c | 178 ++++++++++++++++++++++++++++++++++------
> ----
>  lib/i915/gem_mman.h |  39 +++++++++-
>  2 files changed, 177 insertions(+), 40 deletions(-)
> 
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index 6256627b..920f9ca5 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -40,6 +40,44 @@
>  #define VG(x) do {} while (0)
>  #endif
>  
> +#define LOCAL_I915_PARAM_MMAP_OFFSET_VERSION 54
> +
> +static bool gem_has_mmap_offset(int fd)
> +{
> +	int has_mmap_offset = 0;
> +	struct drm_i915_getparam gp;
> +
> +	memset(&gp, 0, sizeof(gp));
> +	gp.param = LOCAL_I915_PARAM_MMAP_OFFSET_VERSION;
> +	gp.value = &has_mmap_offset;
> +	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> +
> +	return has_mmap_offset > 0;
> +}
> +
> +void gem_require_mmap_offset(int i915)
> +{
> +	igt_require(gem_has_mmap_offset(i915));
> +}
> +
> +static int gem_mmap_gtt_version(int fd)
> +{
> +	struct drm_i915_getparam gp;
> +	int gtt_version = -1;
> +
> +	memset(&gp, 0, sizeof(gp));
> +	gp.param = I915_PARAM_MMAP_GTT_VERSION;
> +	gp.value = &gtt_version;
> +	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> +
> +	return gtt_version;
> +}
> +
> +bool gem_mmap_has_gtt(int fd)
> +{
> +	return gem_mmap_gtt_version(fd) > 0;

Chris mentioned this in a patch I had posted over the weekend, but this
isn't going to properly support the legacy platforms which don't have
IOCTL versioning.

What if we pull has_gtt_mmap() in from tests/i915/gem_userptr_blits.c,
and make it a test we can use across the different tests that need it.
I did test this locally and it seems to work, although I haven't done a
full regression.

IMO this can also be separated out in a new patch, since it isn't
specifically required for the mmap_offset changes here.

Thanks,
Stuart

> +}
> +
>  /**
>   * __gem_mmap__gtt:
>   * @fd: open i915 drm file descriptor
> @@ -101,46 +139,63 @@ int gem_munmap(void *ptr, uint64_t size)
>  	return ret;
>  }
>  
> -bool gem_mmap__has_wc(int fd)
> +bool __gem_mmap__has_wc(int fd)
>  {
> -	static int has_wc = -1;
> -
> -	if (has_wc == -1) {
> -		struct drm_i915_getparam gp;
> -		int mmap_version = -1;
> -		int gtt_version = -1;
> -
> -		has_wc = 0;
> -
> -		memset(&gp, 0, sizeof(gp));
> -		gp.param = I915_PARAM_MMAP_GTT_VERSION;
> -		gp.value = &gtt_version;
> -		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> -
> -		memset(&gp, 0, sizeof(gp));
> -		gp.param = I915_PARAM_MMAP_VERSION;
> -		gp.value = &mmap_version;
> -		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> -
> -		/* Do we have the new mmap_ioctl with DOMAIN_WC? */
> -		if (mmap_version >= 1 && gtt_version >= 2) {
> -			struct drm_i915_gem_mmap arg;
> -
> -			/* Does this device support wc-mmaps ? */
> -			memset(&arg, 0, sizeof(arg));
> -			arg.handle = gem_create(fd, 4096);
> -			arg.offset = 0;
> -			arg.size = 4096;
> -			arg.flags = I915_MMAP_WC;
> -			has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP,
> &arg) == 0;
> -			gem_close(fd, arg.handle);
> -		}
> -		errno = 0;
> +	int has_wc = 0;
> +
> +	struct drm_i915_getparam gp;
> +	int mmap_version = -1;
> +
> +	memset(&gp, 0, sizeof(gp));
> +	gp.param = I915_PARAM_MMAP_VERSION;
> +	gp.value = &mmap_version;
> +	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> +
> +	/* Do we have the mmap_ioctl with DOMAIN_WC? */
> +	if (mmap_version >= 1 && gem_mmap_gtt_version(fd) >= 2) {
> +		struct drm_i915_gem_mmap arg;
> +
> +		/* Does this device support wc-mmaps ? */
> +		memset(&arg, 0, sizeof(arg));
> +		arg.handle = gem_create(fd, 4096);
> +		arg.offset = 0;
> +		arg.size = 4096;
> +		arg.flags = I915_MMAP_WC;
> +		has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg)
> == 0;
> +		gem_close(fd, arg.handle);
> +	}
> +	errno = 0;
> +
> +	return has_wc > 0;
> +}
> +
> +bool __gem_mmap_offset__has_wc(int fd)
> +{
> +	int has_wc = 0;
> +
> +	if (gem_has_mmap_offset(fd)) {
> +		struct local_i915_gem_mmap_offset arg;
> +
> +		/* Does this device support wc-mmaps ? */
> +		memset(&arg, 0, sizeof(arg));
> +		arg.handle = gem_create(fd, 4096);
> +		arg.offset = 0;
> +		arg.flags = LOCAL_I915_MMAP_OFFSET_WC;
> +		has_wc = igt_ioctl(fd,
> LOCAL_IOCTL_I915_GEM_MMAP_OFFSET,
> +				   &arg) == 0;
> +		gem_close(fd, arg.handle);
>  	}
>  
> +	errno = 0;
> +
>  	return has_wc > 0;
>  }
>  
> +bool gem_mmap__has_wc(int fd)
> +{
> +	return __gem_mmap_offset__has_wc(fd) || __gem_mmap__has_wc(fd);
> +}
> +
>  /**
>   * __gem_mmap:
>   * @fd: open i915 drm file descriptor
> @@ -157,8 +212,8 @@ bool gem_mmap__has_wc(int fd)
>   *
>   * Returns: A pointer to the created memory mapping, NULL on
> failure.
>   */
> -static void
> -*__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size,
> unsigned int prot, uint64_t flags)
> +void *__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t
> size,
> +		 unsigned int prot, uint64_t flags)
>  {
>  	struct drm_i915_gem_mmap arg;
>  
> @@ -177,6 +232,43 @@ static void
>  	return from_user_pointer(arg.addr_ptr);
>  }
>  
> +/**
> + * __gem_mmap_offset:
> + * @fd: open i915 drm file descriptor
> + * @handle: gem buffer object handle
> + * @offset: offset in the gem buffer of the mmap arena
> + * @size: size of the mmap arena
> + * @prot: memory protection bits as used by mmap()
> + * @flags: flags used to determine caching
> + *
> + * Similar to __gem_mmap but use MMAP_OFFSET IOCTL.
> + *
> + * Returns: A pointer to the created memory mapping, NULL on
> failure.
> + */
> +void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset,
> uint64_t size,
> +			unsigned int prot, uint64_t flags)
> +{
> +	struct local_i915_gem_mmap_offset arg;
> +	void *ptr;
> +
> +	memset(&arg, 0, sizeof(arg));
> +	arg.handle = handle;
> +	arg.offset = offset;
> +	arg.flags = flags;
> +
> +	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET, &arg))
> +		return NULL;
> +
> +	ptr = mmap64(0, size, prot, MAP_SHARED, fd, arg.offset);
> +
> +	if (ptr == MAP_FAILED)
> +		ptr = NULL;
> +	else
> +		errno = 0;
> +
> +	return ptr;
> +}
> +
>  /**
>   * __gem_mmap__wc:
>   * @fd: open i915 drm file descriptor
> @@ -205,13 +297,17 @@ void *__gem_mmap__wc(int fd, uint32_t handle,
> uint64_t offset, uint64_t size, un
>   * @size: size of the mmap arena
>   * @prot: memory protection bits as used by mmap()
>   *
> - * Like __gem_mmap__wc() except we assert on failure.
> + * Try to __gem_mmap_offset, then __gem_mmap__wc(). Assert on
> failure.
>   *
>   * Returns: A pointer to the created memory mapping
>   */
>  void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset,
> uint64_t size, unsigned prot)
>  {
> -	void *ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
> +	void *ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
> +				       LOCAL_I915_MMAP_OFFSET_WC);
> +	if (!ptr)
> +		ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
> +
>  	igt_assert(ptr);
>  	return ptr;
>  }
> @@ -248,7 +344,11 @@ void *__gem_mmap__cpu(int fd, uint32_t handle,
> uint64_t offset, uint64_t size, u
>   */
>  void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset,
> uint64_t size, unsigned prot)
>  {
> -	void *ptr = __gem_mmap__cpu(fd, handle, offset, size, prot);
> +	void *ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
> +				       LOCAL_I915_MMAP_OFFSET_WB);
> +	if (!ptr)
> +		ptr = __gem_mmap__cpu(fd, handle, offset, size, prot);
> +
>  	igt_assert(ptr);
>  	return ptr;
>  }
> diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
> index 096ff592..e4c954c6 100644
> --- a/lib/i915/gem_mman.h
> +++ b/lib/i915/gem_mman.h
> @@ -25,12 +25,45 @@
>  #ifndef GEM_MMAN_H
>  #define GEM_MMAN_H
>  
> +#define LOCAL_I915_GEM_MMAP_OFFSET       DRM_I915_GEM_MMAP_GTT
> +#define
> LOCAL_IOCTL_I915_GEM_MMAP_OFFSET         DRM_IOWR(DRM_COMMAND_BASE +
> \
> +	LOCAL_I915_GEM_MMAP_OFFSET, struct local_i915_gem_mmap_offset)
> +
> +struct local_i915_gem_mmap_offset {
> +	/** Handle for the object being mapped. */
> +	__u32 handle;
> +	__u32 pad;
> +	/**
> +	 * Fake offset to use for subsequent mmap call
> +	 *
> +	 * This is a fixed-size type for 32/64 compatibility.
> +	 */
> +	__u64 offset;
> +	/**
> +	 * Flags for extended behaviour.
> +	 *
> +	 * It is mandatory that either one of the _WC/_WB flags
> +	 * should be passed here.
> +	 */
> +	__u64 flags;
> +#define LOCAL_I915_MMAP_OFFSET_WC (1 << 0)
> +#define LOCAL_I915_MMAP_OFFSET_WB (1 << 1)
> +#define LOCAL_I915_MMAP_OFFSET_UC (1 << 2)
> +#define LOCAL_I915_MMAP_OFFSET_FLAGS \
> +	(LOCAL_I915_MMAP_OFFSET_WC | LOCAL_I915_MMAP_OFFSET_WB |
> LOCAL_I915_MMAP_OFFSET_UC)
> +};
> +
> +void gem_require_mmap_offset(int i915);
> +bool gem_mmap_has_gtt(int fd);
> +
>  void *gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned
> prot);
>  void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset,
> uint64_t size, unsigned prot);
>  
> +bool __gem_mmap__has_wc(int fd);
> +bool __gem_mmap_offset__has_wc(int fd);
>  bool gem_mmap__has_wc(int fd);
>  void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset,
> uint64_t size, unsigned prot);
> -
> +void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
> uint64_t size, unsigned prot);
>  #ifndef I915_GEM_DOMAIN_WC
>  #define I915_GEM_DOMAIN_WC 0x80
>  #endif
> @@ -38,6 +71,10 @@ void *gem_mmap__wc(int fd, uint32_t handle,
> uint64_t offset, uint64_t size, unsi
>  bool gem_has_mappable_ggtt(int i915);
>  void gem_require_mappable_ggtt(int i915);
>  
> +void *__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t
> size,
> +		 unsigned int prot, uint64_t flags);
> +void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset,
> uint64_t size,
> +			 unsigned int prot, uint64_t flags);
>  void *__gem_mmap__gtt(int fd, uint32_t handle, uint64_t size,
> unsigned prot);
>  void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset,
> uint64_t size, unsigned prot);
>  void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset,
> uint64_t size, unsigned prot);

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Re: [igt-dev] [PATCH i-g-t v2 1/4] lib/i915/gem_mman: add mmap_offset support

[Zbigniew Kempczyński]

On Tue, Nov 19, 2019 at 05:23:09PM +0100, Summers, Stuart wrote:
 
> Chris mentioned this in a patch I had posted over the weekend, but this
> isn't going to properly support the legacy platforms which don't have
> IOCTL versioning.
> 
> What if we pull has_gtt_mmap() in from tests/i915/gem_userptr_blits.c,
> and make it a test we can use across the different tests that need it.
> I did test this locally and it seems to work, although I haven't done a
> full regression.
> 
> IMO this can also be separated out in a new patch, since it isn't
> specifically required for the mmap_offset changes here.
> 

Ok, understand. I'm going to remove this function then and if you 
have code already tested (taken from gem_userptr_blits) please send
it in another patch.

Thanks for comments.
Zbigniew 
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[igt-dev] [PATCH i-g-t v2 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Zbigniew Kempczyński]

From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>

LMEM series introduced concept of memory_regions. This patch implement
helper functions that allow user to manage them in more convenient way.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Zbigniew Kempczyński <lukasz.kalamarz@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/intel_memory_region.c | 295 +++++++++++++++++++++++++++++++++
 lib/i915/intel_memory_region.h | 139 ++++++++++++++++
 lib/ioctl_wrappers.h           |   1 +
 lib/meson.build                |   1 +
 5 files changed, 438 insertions(+)
 create mode 100644 lib/i915/intel_memory_region.c
 create mode 100644 lib/i915/intel_memory_region.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 6333923e..de2ad73a 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -17,6 +17,8 @@ lib_source_list =	 	\
 	i915/gem_mman.h	\
 	i915/gem_vm.c	\
 	i915/gem_vm.h	\
+	i915/intel_memory_region.c	\
+	i915/intel_memory_region.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
new file mode 100644
index 00000000..3768214f
--- /dev/null
+++ b/lib/i915/intel_memory_region.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <signal.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <stdarg.h>
+#include <alloca.h>
+
+#include "intel_reg.h"
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+#include "igt_dummyload.h"
+#include "igt_gt.h"
+#include "intel_chipset.h"
+
+#include "i915/intel_memory_region.h"
+
+#define SZ_4K (4096)
+#define SZ_64K (65536)
+
+#define i915_query_items(fd, items, n_items) do { \
+		igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
+		errno = 0; \
+	} while (0)
+#define i915_query_items_err(fd, items, n_items, err) do { \
+		igt_assert_eq(__i915_query_items(fd, items, n_items), -err); \
+	} while (0)
+
+static int
+__i915_query(int fd, struct drm_i915_query *q)
+{
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		return -errno;
+	return 0;
+}
+
+static int
+__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
+{
+	struct drm_i915_query q = {
+		.num_items = n_items,
+		.items_ptr = to_user_pointer(items),
+	};
+	return __i915_query(fd, &q);
+}
+
+bool gem_has_query_support(int fd)
+{
+	struct drm_i915_query query = {};
+
+	return __i915_query(fd, &query) == 0;
+}
+
+const struct intel_memory_region intel_memory_regions[] = {
+	{ "SMEM", LOCAL_I915_SYSTEM_MEMORY, 0 },
+	{ "LMEM", LOCAL_I915_DEVICE_MEMORY, 0 },
+	{ NULL, 0, 0}
+};
+
+/**
+ *  gem_get_batch_size:
+ *  @fd: open i915 drm file descriptor
+ *  @region: region in which we want to create a batch
+ *
+ *  FIXME: Currently function assumes we have 64K on DEVICE and 4K
+ *  on SYSTEM memory. I know Chris is going to kill me for that
+ *  but I'll fix this when patch with memory region page size detection
+ *  will be merged.
+ */
+uint32_t gem_get_batch_size(int fd, uint32_t region)
+{
+	return IS_DEVICE_MEMORY_REGION(region) ? SZ_64K : SZ_4K;
+}
+
+/**
+ * gem_get_query_memory_regions:
+ * @fd: open i915 drm file descriptor
+ *
+ * This function wraps query mechanism for memory regions.
+ *
+ * Returns: Filled struct with available memory regions.
+ */
+struct local_i915_query_memory_region_info *gem_query_memory_regions(int fd)
+{
+	struct drm_i915_query_item item;
+	struct local_i915_query_memory_region_info *query_info;
+
+	memset(&item, 0, sizeof(item));
+	item.query_id = LOCAL_I915_QUERY_MEMREGION_INFO;
+	i915_query_items(fd, &item, 1);
+
+	query_info = calloc(1, item.length);
+
+	item.data_ptr = to_user_pointer(query_info);
+	i915_query_items(fd, &item, 1);
+
+	return query_info;
+}
+
+/**
+ * gem_get_lmem_region_count:
+ * @fd: open i915 drm file descriptor
+ *
+ * Helper function to check how many lmem regions are available on device.
+ *
+ * Returns: Number of found lmem regions.
+ */
+uint8_t gem_get_lmem_region_count(int fd)
+{
+	struct local_i915_query_memory_region_info *query_info;
+	uint8_t num_regions;
+	uint8_t lmem_regions = 0;
+
+	query_info = gem_query_memory_regions(fd);
+	num_regions = query_info->num_regions;
+
+	for (int i = 0; i < num_regions; i++) {
+		if (IS_DEVICE_MEMORY_REGION(query_info->regions[i].id))
+			lmem_regions += 1;
+	}
+	free(query_info);
+
+	return lmem_regions;
+}
+
+/**
+ * gem_has_lmem:
+ * @fd: open i915 drm file descriptor
+ *
+ * Helper function to check if lmem is available on device.
+ *
+ * Returns: True if at least one lmem region was found.
+ */
+bool gem_has_lmem(int fd)
+{
+	return gem_get_lmem_region_count(fd) > 0;
+}
+
+/**
+ * gem_query_has_memory_region:
+ * @query_info: query result of memory regions
+ * @region: region existance to check inside @query_info regions
+ *
+ * This function check existence of region in @query_info
+ *
+ * Returns: true if memory region was found. Otherwise false.
+ */
+bool gem_query_has_memory_region(struct local_i915_query_memory_region_info *query_info,
+			   uint32_t region)
+{
+	for (int i = 0; i < query_info->num_regions; i++)
+		if (query_info->regions[i].id == region)
+			return true;
+
+	return false;
+}
+
+/**
+ * gem_query_require_region:
+ * @query_info: query result of memory regions
+ * @region: region to check inside query
+ *
+ * Function lead to skipping test if @region doesn't exists in @query_info.
+ */
+void gem_query_require_region(struct local_i915_query_memory_region_info *query_info,
+			      uint32_t region)
+{
+	igt_require(gem_query_has_memory_region(query_info, region));
+}
+
+/**
+ * __gem_migrate_to_memory_regions:
+ * @fd: open i915 drm file descriptor
+ * @handle: buffer object handle
+ * @mem_regions: memory regions id array
+ * @size: memory regions array size
+ *
+ * Wrapper function on IOCTL_I915_GEM_OBJECT_SETPARAM. It sets object to be
+ * migrated into one of memory region specified in the array. Array contains
+ * memory regions in requested priority order - if no migration to first
+ * memory region is possible next one is selected and so on.
+ *
+ * Returns: errno
+ */
+static int __gem_migrate_to_memory_regions(int fd, int handle,
+					   uint32_t *mem_regions,
+					   uint32_t size)
+{
+	struct local_i915_gem_object_param obj;
+	int err = 0;
+
+	memset(&obj, 0, sizeof(obj));
+	obj.handle = handle;
+	obj.size = size;
+	obj.param = I915_PARAM_MEMORY_REGION | I915_OBJECT_PARAM;
+	obj.data = to_user_pointer(mem_regions);
+
+	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_OBJECT_SETPARAM, &obj)) {
+		err = -errno;
+		errno = 0;
+	}
+
+	return err;
+}
+
+/**
+ * gem_migrate_to_memory_region:
+ * @fd: open i915 drm file descriptor
+ * @handle: handle to GEM bo
+ * @type: memory region type
+ * @instance: memory region instance
+ *
+ * This function wraps GEM_OBJECT_SETPARAM into user friendly version. Object
+ * which user pass @handle will be migrated to memory region, specified
+ * by @type and @instance.
+ *
+ * Returns: errno if error occurred.
+ */
+int gem_migrate_to_memory_region(int fd, int handle, uint32_t region)
+{
+	return __gem_migrate_to_memory_regions(fd, handle, &region, 1);
+}
+
+/**
+ * gem_migrate_to_lmem:
+ * @fd: open i915 drm file descriptor
+ * @handle: handle to object that user want to migrate to LMEM
+ *
+ * This function wraps GEM_OBJECT_SETPARAM into user friendly version. Object
+ * which user pass @handle will be migrated to LMEM.
+ *
+ * Returns: errno if error occurred.
+ */
+int gem_migrate_to_lmem(int fd, int handle)
+{
+	return gem_migrate_to_memory_region(fd, handle, REGION_DEVICE_MEMORY(0));
+}
+
+/**
+ * gem_migrate_to_smem:
+ * @fd: open i915 drm file descriptor
+ * @hadle: handle to object that user want to migrate to SMEM
+ *
+ * This function wraps GEM_OBJECT_SETPARAM into user friendly version. Object
+ * onto which user pass @handle will be migrated to SMEM.
+ *
+ * Returns: errno if error occurred.
+ */
+int gem_migrate_to_smem(int fd, int handle)
+{
+	return gem_migrate_to_memory_region(fd, handle, REGION_SYSTEM_MEMORY(0));
+}
+
+/* gem_create_in_memory_region_list:
+ * @fd: opened i915 drm file descriptor
+ * @size: requested size of the buffer
+ * @mem_regions: memory regions array (priority list)
+ * @num_regions: @mem_regions length
+ */
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+					  uint32_t *mem_regions,
+					  int num_regions)
+{
+	uint32_t handle = gem_create(fd, size);
+
+	if (gem_has_lmem(fd)) {
+		int ret = __gem_migrate_to_memory_regions(fd, handle,
+							  mem_regions,
+							  num_regions);
+		igt_assert_eq(ret, 0);
+	}
+
+	return handle;
+}
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
new file mode 100644
index 00000000..68fd13a9
--- /dev/null
+++ b/lib/i915/intel_memory_region.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include <stdint.h>
+#include "benchmarks/ilog2.h"
+#include "i915_drm.h"
+
+#ifndef INTEL_MEMORY_REGION_H
+#define INTEL_MEMORY_REGION_H
+
+#define INTEL_MEMORY_TYPE_SHIFT 16
+
+#define INTEL_MEMORY_REGION_ID(type, instance) \
+			((BIT((type) + INTEL_MEMORY_TYPE_SHIFT)) | BIT(instance))
+#define MEMORY_TYPE_FROM_REGION(r) (ilog2(r >> INTEL_MEMORY_TYPE_SHIFT))
+#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2(r & 0xffff))
+
+#define IS_DEVICE_MEMORY_REGION(region) \
+	(MEMORY_TYPE_FROM_REGION(region) == LOCAL_I915_DEVICE_MEMORY)
+#define IS_SYSTEM_MEMORY_REGION(region) \
+	(MEMORY_TYPE_FROM_REGION(region) == LOCAL_I915_SYSTEM_MEMORY)
+
+/* Region macros for migration */
+#define REGION_SYSTEM_MEMORY(n) INTEL_MEMORY_REGION_ID(LOCAL_I915_SYSTEM_MEMORY, n)
+#define REGION_DEVICE_MEMORY(n) INTEL_MEMORY_REGION_ID(LOCAL_I915_DEVICE_MEMORY, n)
+
+#define LOCAL_I915_QUERY_MEMREGION_INFO   4
+struct local_i915_memory_region_info {
+
+	/** Base type of a region */
+#define LOCAL_I915_SYSTEM_MEMORY         0
+#define LOCAL_I915_DEVICE_MEMORY         1
+
+	/** The region id is encoded in a layout which makes it possible to
+	 * retrieve the following information:
+	 *
+	 *  Base type: log2(ID >> 16)
+	 */
+	__u32 id;
+
+	/** Reserved field. MBZ */
+	__u32 rsvd0;
+
+	/** Unused for now. MBZ */
+	__u64 flags;
+
+	__u64 size;
+
+	/** Reserved fields must be cleared to zero. */
+	__u64 rsvd1[4];
+};
+
+struct local_i915_query_memory_region_info {
+
+	/** Number of struct drm_i915_memory_region_info structs */
+	__u32 num_regions;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	struct local_i915_memory_region_info regions[];
+};
+
+struct local_i915_gem_object_param {
+	/** Handle for the object */
+	__u32 handle;
+
+	__u32 size;
+
+	/** Set the memory region for the object listed in preference order
+	 *  as an array of region ids within data. To force an object
+	 *  to a particular memory region, set the region as the sole entry.
+	 *
+	 *  Valid region ids are derived from the id field of
+	 *  struct drm_i915_memory_region_info.
+	 *  See struct drm_i915_query_memory_region_info.
+	 */
+#define I915_OBJECT_PARAM  (1ull<<32)
+#define I915_PARAM_MEMORY_REGION 0x1
+	__u64 param;
+
+	__u64 data;
+};
+
+#define LOCAL_I915_GEM_OBJECT_SETPARAM	DRM_I915_GEM_CONTEXT_SETPARAM
+#define LOCAL_IOCTL_I915_GEM_OBJECT_SETPARAM	DRM_IOWR(DRM_COMMAND_BASE \
+	+ LOCAL_I915_GEM_OBJECT_SETPARAM, struct local_i915_gem_object_param)
+
+extern const struct intel_memory_region {
+	const char *region_name;
+	uint8_t memory_type;
+	uint8_t memory_instance;
+} intel_memory_regions[];
+
+bool gem_has_query_support(int fd);
+
+uint32_t gem_get_batch_size(int fd, uint32_t region);
+
+struct local_i915_query_memory_region_info *gem_query_memory_regions(int fd);
+
+uint8_t gem_get_lmem_region_count(int fd);
+
+bool gem_has_lmem(int fd);
+bool gem_query_has_memory_region(struct local_i915_query_memory_region_info *query_info,
+				 uint32_t region);
+void gem_query_require_region(struct local_i915_query_memory_region_info *query_info,
+			      uint32_t region);
+int gem_migrate_to_memory_region(int fd, int handle, uint32_t region);
+int gem_migrate_to_lmem(int fd, int handle);
+int gem_migrate_to_smem(int fd, int handle);
+
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+					  uint32_t *mem_regions,
+					  int num_regions);
+#define gem_create_in_memory_regions(fd, size, regions...) ({ \
+	unsigned int arr__[] = { regions }; \
+	gem_create_in_memory_region_list(fd, size, arr__, ARRAY_SIZE(arr__)); \
+})
+
+#endif /* INTEL_MEMORY_REGION_H */
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index f2412d78..885cbb06 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -38,6 +38,7 @@
 
 #include "i915/gem_context.h"
 #include "i915/gem_scheduler.h"
+#include "i915/intel_memory_region.h"
 
 /**
  * igt_ioctl:
diff --git a/lib/meson.build b/lib/meson.build
index 73c07b0f..f25bd3e2 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -7,6 +7,7 @@ lib_sources = [
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
 	'i915/gem_vm.c',
+	'i915/intel_memory_region.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.23.0

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igt-dev@lists.freedesktop.org
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Re: [igt-dev] [PATCH i-g-t v2 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Vanshidhar Konda]

On Tue, Nov 19, 2019 at 05:02:21PM +0100, Zbigniew Kempczyński wrote:
>From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
>
>LMEM series introduced concept of memory_regions. This patch implement
>helper functions that allow user to manage them in more convenient way.
>
>Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
>Signed-off-by: Zbigniew Kempczyński <lukasz.kalamarz@intel.com>
>Cc: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>---
> lib/Makefile.sources           |   2 +
> lib/i915/intel_memory_region.c | 295 +++++++++++++++++++++++++++++++++
> lib/i915/intel_memory_region.h | 139 ++++++++++++++++
> lib/ioctl_wrappers.h           |   1 +
> lib/meson.build                |   1 +
> 5 files changed, 438 insertions(+)
> create mode 100644 lib/i915/intel_memory_region.c
> create mode 100644 lib/i915/intel_memory_region.h
>
>diff --git a/lib/Makefile.sources b/lib/Makefile.sources
>index 6333923e..de2ad73a 100644
>--- a/lib/Makefile.sources
>+++ b/lib/Makefile.sources
>@@ -17,6 +17,8 @@ lib_source_list =	 	\
> 	i915/gem_mman.h	\
> 	i915/gem_vm.c	\
> 	i915/gem_vm.h	\
>+	i915/intel_memory_region.c	\
>+	i915/intel_memory_region.h	\
> 	i915_3d.h		\
> 	i915_reg.h		\
> 	i915_pciids.h		\
>diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
>new file mode 100644
>index 00000000..3768214f
>--- /dev/null
>+++ b/lib/i915/intel_memory_region.c
>@@ -0,0 +1,295 @@
>+/*
>+ * Copyright © 2019 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ */
>+
>+#include <signal.h>
>+#include <sys/ioctl.h>
>+#include <sys/time.h>
>+#include <stdarg.h>
>+#include <alloca.h>
>+
>+#include "intel_reg.h"
>+#include "drmtest.h"
>+#include "ioctl_wrappers.h"
>+#include "igt_dummyload.h"
>+#include "igt_gt.h"
>+#include "intel_chipset.h"
>+
>+#include "i915/intel_memory_region.h"
>+
>+#define SZ_4K (4096)
>+#define SZ_64K (65536)
>+
>+#define i915_query_items(fd, items, n_items) do { \
>+		igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
>+		errno = 0; \
>+	} while (0)
>+#define i915_query_items_err(fd, items, n_items, err) do { \
>+		igt_assert_eq(__i915_query_items(fd, items, n_items), -err); \
>+	} while (0)
>+
>+static int
>+__i915_query(int fd, struct drm_i915_query *q)
>+{
>+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
>+		return -errno;
>+	return 0;
>+}
>+
>+static int
>+__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
>+{
>+	struct drm_i915_query q = {
>+		.num_items = n_items,
>+		.items_ptr = to_user_pointer(items),
>+	};
>+	return __i915_query(fd, &q);
>+}
>+
>+bool gem_has_query_support(int fd)
>+{
>+	struct drm_i915_query query = {};
>+
>+	return __i915_query(fd, &query) == 0;
>+}
>+
>+const struct intel_memory_region intel_memory_regions[] = {
>+	{ "SMEM", LOCAL_I915_SYSTEM_MEMORY, 0 },
>+	{ "LMEM", LOCAL_I915_DEVICE_MEMORY, 0 },
>+	{ NULL, 0, 0}
>+};
>+
>+/**
>+ *  gem_get_batch_size:
>+ *  @fd: open i915 drm file descriptor
>+ *  @region: region in which we want to create a batch
>+ *
>+ *  FIXME: Currently function assumes we have 64K on DEVICE and 4K
>+ *  on SYSTEM memory. I know Chris is going to kill me for that
>+ *  but I'll fix this when patch with memory region page size detection
>+ *  will be merged.
>+ */
>+uint32_t gem_get_batch_size(int fd, uint32_t region)
>+{
>+	return IS_DEVICE_MEMORY_REGION(region) ? SZ_64K : SZ_4K;
>+}
>+
>+/**
>+ * gem_get_query_memory_regions:
>+ * @fd: open i915 drm file descriptor
>+ *
>+ * This function wraps query mechanism for memory regions.
>+ *
>+ * Returns: Filled struct with available memory regions.
>+ */
>+struct local_i915_query_memory_region_info *gem_query_memory_regions(int fd)
>+{
>+	struct drm_i915_query_item item;
>+	struct local_i915_query_memory_region_info *query_info;
>+
>+	memset(&item, 0, sizeof(item));
>+	item.query_id = LOCAL_I915_QUERY_MEMREGION_INFO;
>+	i915_query_items(fd, &item, 1);
>+
>+	query_info = calloc(1, item.length);
>+
>+	item.data_ptr = to_user_pointer(query_info);
>+	i915_query_items(fd, &item, 1);
>+
>+	return query_info;
>+}
>+
>+/**
>+ * gem_get_lmem_region_count:
>+ * @fd: open i915 drm file descriptor
>+ *
>+ * Helper function to check how many lmem regions are available on device.
>+ *
>+ * Returns: Number of found lmem regions.
>+ */
>+uint8_t gem_get_lmem_region_count(int fd)
>+{
>+	struct local_i915_query_memory_region_info *query_info;
>+	uint8_t num_regions;
>+	uint8_t lmem_regions = 0;
>+
>+	query_info = gem_query_memory_regions(fd);
>+	num_regions = query_info->num_regions;
>+
>+	for (int i = 0; i < num_regions; i++) {
>+		if (IS_DEVICE_MEMORY_REGION(query_info->regions[i].id))
>+			lmem_regions += 1;
>+	}
>+	free(query_info);
>+
>+	return lmem_regions;
>+}
>+
>+/**
>+ * gem_has_lmem:
>+ * @fd: open i915 drm file descriptor
>+ *
>+ * Helper function to check if lmem is available on device.
>+ *
>+ * Returns: True if at least one lmem region was found.
>+ */
>+bool gem_has_lmem(int fd)
>+{
>+	return gem_get_lmem_region_count(fd) > 0;
>+}
>+
>+/**
>+ * gem_query_has_memory_region:
>+ * @query_info: query result of memory regions
>+ * @region: region existance to check inside @query_info regions
>+ *
>+ * This function check existence of region in @query_info
>+ *
>+ * Returns: true if memory region was found. Otherwise false.
>+ */
>+bool gem_query_has_memory_region(struct local_i915_query_memory_region_info *query_info,
>+			   uint32_t region)
>+{
>+	for (int i = 0; i < query_info->num_regions; i++)
>+		if (query_info->regions[i].id == region)
>+			return true;
>+
>+	return false;
>+}
>+
>+/**
>+ * gem_query_require_region:
>+ * @query_info: query result of memory regions
>+ * @region: region to check inside query
>+ *
>+ * Function lead to skipping test if @region doesn't exists in @query_info.
>+ */
>+void gem_query_require_region(struct local_i915_query_memory_region_info *query_info,
>+			      uint32_t region)

Fix formatting for second line

>+{
>+	igt_require(gem_query_has_memory_region(query_info, region));
>+}
>+
>+/**
>+ * __gem_migrate_to_memory_regions:
>+ * @fd: open i915 drm file descriptor
>+ * @handle: buffer object handle
>+ * @mem_regions: memory regions id array
>+ * @size: memory regions array size
>+ *
>+ * Wrapper function on IOCTL_I915_GEM_OBJECT_SETPARAM. It sets object to be
>+ * migrated into one of memory region specified in the array. Array contains
>+ * memory regions in requested priority order - if no migration to first
>+ * memory region is possible next one is selected and so on.
>+ *
>+ * Returns: errno
>+ */
>+static int __gem_migrate_to_memory_regions(int fd, int handle,
>+					   uint32_t *mem_regions,
>+					   uint32_t size)
>+{
>+	struct local_i915_gem_object_param obj;
>+	int err = 0;
>+
>+	memset(&obj, 0, sizeof(obj));
>+	obj.handle = handle;
>+	obj.size = size;
>+	obj.param = I915_PARAM_MEMORY_REGION | I915_OBJECT_PARAM;
>+	obj.data = to_user_pointer(mem_regions);
>+
>+	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_OBJECT_SETPARAM, &obj)) {
>+		err = -errno;
>+		errno = 0;
>+	}
>+
>+	return err;
>+}
>+
>+/**
>+ * gem_migrate_to_memory_region:
>+ * @fd: open i915 drm file descriptor
>+ * @handle: handle to GEM bo
>+ * @type: memory region type
>+ * @instance: memory region instance
>+ *
>+ * This function wraps GEM_OBJECT_SETPARAM into user friendly version. Object
>+ * which user pass @handle will be migrated to memory region, specified
>+ * by @type and @instance.
>+ *
>+ * Returns: errno if error occurred.
>+ */
>+int gem_migrate_to_memory_region(int fd, int handle, uint32_t region)
>+{
>+	return __gem_migrate_to_memory_regions(fd, handle, &region, 1);
>+}
>+
>+/**
>+ * gem_migrate_to_lmem:
>+ * @fd: open i915 drm file descriptor
>+ * @handle: handle to object that user want to migrate to LMEM
>+ *
>+ * This function wraps GEM_OBJECT_SETPARAM into user friendly version. Object
>+ * which user pass @handle will be migrated to LMEM.
>+ *
>+ * Returns: errno if error occurred.
>+ */
>+int gem_migrate_to_lmem(int fd, int handle)
>+{
>+	return gem_migrate_to_memory_region(fd, handle, REGION_DEVICE_MEMORY(0));
>+}
>+
>+/**
>+ * gem_migrate_to_smem:
>+ * @fd: open i915 drm file descriptor
>+ * @hadle: handle to object that user want to migrate to SMEM
>+ *
>+ * This function wraps GEM_OBJECT_SETPARAM into user friendly version. Object
>+ * onto which user pass @handle will be migrated to SMEM.
>+ *
>+ * Returns: errno if error occurred.
>+ */
>+int gem_migrate_to_smem(int fd, int handle)
>+{
>+	return gem_migrate_to_memory_region(fd, handle, REGION_SYSTEM_MEMORY(0));
>+}
>+
>+/* gem_create_in_memory_region_list:
>+ * @fd: opened i915 drm file descriptor
>+ * @size: requested size of the buffer
>+ * @mem_regions: memory regions array (priority list)
>+ * @num_regions: @mem_regions length
>+ */
>+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
>+					  uint32_t *mem_regions,
>+					  int num_regions)
>+{
>+	uint32_t handle = gem_create(fd, size);
>+
>+	if (gem_has_lmem(fd)) {

Why have a check for LMEM only? Is it not possible to have multiple
SMEM regions? Or that the object is always created in SMEM?

Other than these two comments, looks good to me.

Acked-by: Vanshidhar Konda <vanshidhar.r.konda@intel.com>

>+		int ret = __gem_migrate_to_memory_regions(fd, handle,
>+							  mem_regions,
>+							  num_regions);
>+		igt_assert_eq(ret, 0);
>+	}
>+
>+	return handle;
>+}
>diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
>new file mode 100644
>index 00000000..68fd13a9
>--- /dev/null
>+++ b/lib/i915/intel_memory_region.h
>@@ -0,0 +1,139 @@
>+/*
>+ * Copyright © 2019 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ */
>+#include <stdint.h>
>+#include "benchmarks/ilog2.h"
>+#include "i915_drm.h"
>+
>+#ifndef INTEL_MEMORY_REGION_H
>+#define INTEL_MEMORY_REGION_H
>+
>+#define INTEL_MEMORY_TYPE_SHIFT 16
>+
>+#define INTEL_MEMORY_REGION_ID(type, instance) \
>+			((BIT((type) + INTEL_MEMORY_TYPE_SHIFT)) | BIT(instance))
>+#define MEMORY_TYPE_FROM_REGION(r) (ilog2(r >> INTEL_MEMORY_TYPE_SHIFT))
>+#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2(r & 0xffff))
>+
>+#define IS_DEVICE_MEMORY_REGION(region) \
>+	(MEMORY_TYPE_FROM_REGION(region) == LOCAL_I915_DEVICE_MEMORY)
>+#define IS_SYSTEM_MEMORY_REGION(region) \
>+	(MEMORY_TYPE_FROM_REGION(region) == LOCAL_I915_SYSTEM_MEMORY)
>+
>+/* Region macros for migration */
>+#define REGION_SYSTEM_MEMORY(n) INTEL_MEMORY_REGION_ID(LOCAL_I915_SYSTEM_MEMORY, n)
>+#define REGION_DEVICE_MEMORY(n) INTEL_MEMORY_REGION_ID(LOCAL_I915_DEVICE_MEMORY, n)
>+
>+#define LOCAL_I915_QUERY_MEMREGION_INFO   4
>+struct local_i915_memory_region_info {
>+
>+	/** Base type of a region */
>+#define LOCAL_I915_SYSTEM_MEMORY         0
>+#define LOCAL_I915_DEVICE_MEMORY         1
>+
>+	/** The region id is encoded in a layout which makes it possible to
>+	 * retrieve the following information:
>+	 *
>+	 *  Base type: log2(ID >> 16)
>+	 */
>+	__u32 id;
>+
>+	/** Reserved field. MBZ */
>+	__u32 rsvd0;
>+
>+	/** Unused for now. MBZ */
>+	__u64 flags;
>+
>+	__u64 size;
>+
>+	/** Reserved fields must be cleared to zero. */
>+	__u64 rsvd1[4];
>+};
>+
>+struct local_i915_query_memory_region_info {
>+
>+	/** Number of struct drm_i915_memory_region_info structs */
>+	__u32 num_regions;
>+
>+	/** MBZ */
>+	__u32 rsvd[3];
>+
>+	struct local_i915_memory_region_info regions[];
>+};
>+
>+struct local_i915_gem_object_param {
>+	/** Handle for the object */
>+	__u32 handle;
>+
>+	__u32 size;
>+
>+	/** Set the memory region for the object listed in preference order
>+	 *  as an array of region ids within data. To force an object
>+	 *  to a particular memory region, set the region as the sole entry.
>+	 *
>+	 *  Valid region ids are derived from the id field of
>+	 *  struct drm_i915_memory_region_info.
>+	 *  See struct drm_i915_query_memory_region_info.
>+	 */
>+#define I915_OBJECT_PARAM  (1ull<<32)
>+#define I915_PARAM_MEMORY_REGION 0x1
>+	__u64 param;
>+
>+	__u64 data;
>+};
>+
>+#define LOCAL_I915_GEM_OBJECT_SETPARAM	DRM_I915_GEM_CONTEXT_SETPARAM
>+#define LOCAL_IOCTL_I915_GEM_OBJECT_SETPARAM	DRM_IOWR(DRM_COMMAND_BASE \
>+	+ LOCAL_I915_GEM_OBJECT_SETPARAM, struct local_i915_gem_object_param)
>+
>+extern const struct intel_memory_region {
>+	const char *region_name;
>+	uint8_t memory_type;
>+	uint8_t memory_instance;
>+} intel_memory_regions[];
>+
>+bool gem_has_query_support(int fd);
>+
>+uint32_t gem_get_batch_size(int fd, uint32_t region);
>+
>+struct local_i915_query_memory_region_info *gem_query_memory_regions(int fd);
>+
>+uint8_t gem_get_lmem_region_count(int fd);
>+
>+bool gem_has_lmem(int fd);
>+bool gem_query_has_memory_region(struct local_i915_query_memory_region_info *query_info,
>+				 uint32_t region);
>+void gem_query_require_region(struct local_i915_query_memory_region_info *query_info,
>+			      uint32_t region);
>+int gem_migrate_to_memory_region(int fd, int handle, uint32_t region);
>+int gem_migrate_to_lmem(int fd, int handle);
>+int gem_migrate_to_smem(int fd, int handle);
>+
>+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
>+					  uint32_t *mem_regions,
>+					  int num_regions);
>+#define gem_create_in_memory_regions(fd, size, regions...) ({ \
>+	unsigned int arr__[] = { regions }; \
>+	gem_create_in_memory_region_list(fd, size, arr__, ARRAY_SIZE(arr__)); \
>+})
>+
>+#endif /* INTEL_MEMORY_REGION_H */
>diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
>index f2412d78..885cbb06 100644
>--- a/lib/ioctl_wrappers.h
>+++ b/lib/ioctl_wrappers.h
>@@ -38,6 +38,7 @@
>
> #include "i915/gem_context.h"
> #include "i915/gem_scheduler.h"
>+#include "i915/intel_memory_region.h"
>
> /**
>  * igt_ioctl:
>diff --git a/lib/meson.build b/lib/meson.build
>index 73c07b0f..f25bd3e2 100644
>--- a/lib/meson.build
>+++ b/lib/meson.build
>@@ -7,6 +7,7 @@ lib_sources = [
> 	'i915/gem_ring.c',
> 	'i915/gem_mman.c',
> 	'i915/gem_vm.c',
>+	'i915/intel_memory_region.c',
> 	'igt_color_encoding.c',
> 	'igt_debugfs.c',
> 	'igt_device.c',
>-- 
>2.23.0
>
>_______________________________________________
>igt-dev mailing list
>igt-dev@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v2 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Zbigniew Kempczyński]

On Tue, Nov 19, 2019 at 10:03:29AM -0800, Vanshidhar Konda wrote:

<cut>
> > + * gem_query_has_memory_region:
> > + * @query_info: query result of memory regions
> > + * @region: region existance to check inside @query_info regions
> > + *
> > + * This function check existence of region in @query_info
> > + *
> > + * Returns: true if memory region was found. Otherwise false.
> > + */
> > +bool gem_query_has_memory_region(struct local_i915_query_memory_region_info *query_info,
> > +			   uint32_t region)
> > +{
> > +	for (int i = 0; i < query_info->num_regions; i++)
> > +		if (query_info->regions[i].id == region)
> > +			return true;
> > +
> > +	return false;
> > +}
> > +
> > +/**
> > + * gem_query_require_region:
> > + * @query_info: query result of memory regions
> > + * @region: region to check inside query
> > + *
> > + * Function lead to skipping test if @region doesn't exists in @query_info.
> > + */
> > +void gem_query_require_region(struct local_i915_query_memory_region_info *query_info,
> > +			      uint32_t region)
> 
> Fix formatting for second line

Ok, be in v3 in an hour.
 
> > +/* gem_create_in_memory_region_list:
> > + * @fd: opened i915 drm file descriptor
> > + * @size: requested size of the buffer
> > + * @mem_regions: memory regions array (priority list)
> > + * @num_regions: @mem_regions length
> > + */
> > +uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
> > +					  uint32_t *mem_regions,
> > +					  int num_regions)
> > +{
> > +	uint32_t handle = gem_create(fd, size);
> > +
> > +	if (gem_has_lmem(fd)) {
> 
> Why have a check for LMEM only? Is it not possible to have multiple
> SMEM regions? Or that the object is always created in SMEM?
> 
> Other than these two comments, looks good to me.

Good point. Until now I thought we will have single SMEM region,
but who knows :)

> 
> Acked-by: Vanshidhar Konda <vanshidhar.r.konda@intel.com>

Thanks for comments and A-B.

Zbigniew
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Re: [igt-dev] [PATCH i-g-t v2 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Petri Latvala]

On Tue, Nov 19, 2019 at 05:02:21PM +0100, Zbigniew Kempczyński wrote:
> diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
> new file mode 100644
> index 00000000..68fd13a9
> --- /dev/null
> +++ b/lib/i915/intel_memory_region.h
> @@ -0,0 +1,139 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +#include <stdint.h>
> +#include "benchmarks/ilog2.h"


Do not include headers from benchmarks/, especially one that is x86-only.


-- 
Petri Latvala
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Re: [igt-dev] [PATCH i-g-t v2 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Zbigniew Kempczyński]

On Wed, Nov 20, 2019 at 11:34:50AM +0200, Petri Latvala wrote:
> On Tue, Nov 19, 2019 at 05:02:21PM +0100, Zbigniew Kempczyński wrote:
> > diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
> > new file mode 100644
> > index 00000000..68fd13a9
> > --- /dev/null
> > +++ b/lib/i915/intel_memory_region.h
> > @@ -0,0 +1,139 @@
> > +/*
> > + * Copyright © 2019 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the next
> > + * paragraph) shall be included in all copies or substantial portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +#include <stdint.h>
> > +#include "benchmarks/ilog2.h"
> 
> 
> Do not include headers from benchmarks/, especially one that is x86-only.
> 

Ok. I've replaced that code to different implementation than kernel side,
but intel_memory_region.[ch] is x86-only. So imo this code should be a part
of some not-benchmark include available for i915 tests.

Zbigniew 
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[igt-dev] [PATCH i-g-t v2 3/4] tests/i915/gem_mmap_offset: Add new API test for gem_mmap_offset

[Zbigniew Kempczyński]

From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>

This test is a copy/paste of few gem_mmap subtests, due to good
coverage in previous one. We also need to be sure that we cover
all available memory regions.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 tests/Makefile.sources       |   3 +
 tests/i915/gem_mmap_offset.c | 156 +++++++++++++++++++++++++++++++++++
 tests/meson.build            |   1 +
 3 files changed, 160 insertions(+)
 create mode 100644 tests/i915/gem_mmap_offset.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 27801c89..9c6c3933 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -320,6 +320,9 @@ gem_mmap_SOURCES = i915/gem_mmap.c
 TESTS_progs += gem_mmap_gtt
 gem_mmap_gtt_SOURCES = i915/gem_mmap_gtt.c
 
+TESTS_progs += gem_mmap_offset
+gem_mmap_offset_SOURCES = i915/gem_mmap_offset.c
+
 TESTS_progs += gem_mmap_offset_exhaustion
 gem_mmap_offset_exhaustion_SOURCES = i915/gem_mmap_offset_exhaustion.c
 
diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
new file mode 100644
index 00000000..b2339111
--- /dev/null
+++ b/tests/i915/gem_mmap_offset.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include "drm.h"
+
+IGT_TEST_DESCRIPTION("Basic MMAP_OFFSET IOCTL tests for mem regions\n");
+
+static int mmap_offset_ioctl(int fd, struct local_i915_gem_mmap_offset *arg)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET, arg))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+igt_main
+{
+	uint8_t *addr;
+	uint32_t obj_size, batch_size;
+	uint32_t mem_type, mem_instance;
+	uint32_t region;
+	int fd;
+	const struct intel_memory_region *mr;
+	struct local_i915_query_memory_region_info *query_info;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_INTEL);
+		gem_require_mmap_offset(fd);
+
+		query_info = gem_query_memory_regions(fd);
+		igt_assert(query_info);
+	}
+
+	for (mr = intel_memory_regions; mr->region_name; mr++) {
+		mem_type = mr->memory_type;
+		mem_instance = mr->memory_instance;
+		region = INTEL_MEMORY_REGION_ID(mem_type, mem_instance);
+		batch_size = gem_get_batch_size(fd, region);
+		obj_size = 4 * batch_size;
+
+		igt_subtest_f("bad-object-%s", mr->region_name) {
+			uint32_t real_handle;
+			uint32_t handles[20];
+			int i = 0;
+
+			gem_query_require_region(query_info, region);
+
+			real_handle = gem_create_in_memory_regions(fd, obj_size,
+								   region);
+
+			handles[i++] = 0xdeadbeef;
+			for (int bit = 0; bit < 16; bit++)
+				handles[i++] = real_handle | (1 << (bit + 16));
+			handles[i] = real_handle + 1;
+
+			for (; i >= 0; i--) {
+				struct local_i915_gem_mmap_offset arg = {
+					.handle = handles[i],
+					.flags = LOCAL_I915_MMAP_OFFSET_WB,
+				};
+
+				igt_debug("Trying MMAP IOCTL with handle %x\n",
+					  handles[i]);
+				igt_assert_eq(mmap_offset_ioctl(fd, &arg),
+					      -ENOENT);
+			}
+
+			gem_close(fd, real_handle);
+		}
+
+		igt_subtest_f("basic-%s", mr->region_name) {
+			struct local_i915_gem_mmap_offset arg;
+			uint8_t *expected;
+			uint8_t *buf;
+
+			gem_query_require_region(query_info, region);
+
+			arg.handle = gem_create_in_memory_regions(fd, obj_size,
+								  region);
+			arg.flags = LOCAL_I915_MMAP_OFFSET_WB;
+
+			igt_assert_eq(mmap_offset_ioctl(fd, &arg), 0);
+			addr = mmap64(0, obj_size, PROT_READ | PROT_WRITE,
+				      MAP_SHARED, fd, arg.offset);
+			igt_assert(addr != MAP_FAILED);
+
+			igt_debug("Testing contents of newly created object.\n");
+			expected = calloc(obj_size, sizeof(*expected));
+			igt_assert_eq(memcmp(addr, expected, obj_size), 0);
+			free(expected);
+
+			igt_debug("Testing coherency of writes and mmap reads.\n");
+			buf = calloc(obj_size, sizeof(*buf));
+			memset(buf + 1024, 0x01, 1024);
+			gem_write(fd, arg.handle, 0, buf, obj_size);
+			igt_assert_eq(memcmp(buf, addr, obj_size), 0);
+
+			igt_debug("Testing that mapping stays after close\n");
+			gem_close(fd, arg.handle);
+			igt_assert_eq(memcmp(buf, addr, obj_size), 0);
+			free(buf);
+
+			igt_debug("Testing unmapping\n");
+			munmap(addr, obj_size);
+		}
+
+		igt_subtest_f("short-mmap-%s", mr->region_name) {
+			uint32_t handle;
+
+			gem_query_require_region(query_info, region);
+
+			handle = gem_create_in_memory_regions(fd, obj_size,
+							      region);
+			igt_assert(obj_size > batch_size);
+
+			addr = gem_mmap__cpu(fd, handle, 0, batch_size,
+					     PROT_WRITE);
+			memset(addr, 0, batch_size);
+			munmap(addr, batch_size);
+
+			gem_close(fd, handle);
+		}
+	}
+
+	igt_fixture {
+		free(query_info);
+		close(fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 755fc9e6..644b5504 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -174,6 +174,7 @@ i915_progs = [
 	'gem_media_vme',
 	'gem_mmap',
 	'gem_mmap_gtt',
+	'gem_mmap_offset',
 	'gem_mmap_offset_exhaustion',
 	'gem_mmap_wc',
 	'gem_partial_pwrite_pread',
-- 
2.23.0

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Re: [igt-dev] [PATCH i-g-t v2 3/4] tests/i915/gem_mmap_offset: Add new API test for gem_mmap_offset

[Vanshidhar Konda]

On Tue, Nov 19, 2019 at 05:02:22PM +0100, Zbigniew Kempczyński wrote:
>From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
>
>This test is a copy/paste of few gem_mmap subtests, due to good
>coverage in previous one. We also need to be sure that we cover
>all available memory regions.
>
>Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
>Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>Cc: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>---
> tests/Makefile.sources       |   3 +
> tests/i915/gem_mmap_offset.c | 156 +++++++++++++++++++++++++++++++++++
> tests/meson.build            |   1 +
> 3 files changed, 160 insertions(+)
> create mode 100644 tests/i915/gem_mmap_offset.c
>
>diff --git a/tests/Makefile.sources b/tests/Makefile.sources
>index 27801c89..9c6c3933 100644
>--- a/tests/Makefile.sources
>+++ b/tests/Makefile.sources
>@@ -320,6 +320,9 @@ gem_mmap_SOURCES = i915/gem_mmap.c
> TESTS_progs += gem_mmap_gtt
> gem_mmap_gtt_SOURCES = i915/gem_mmap_gtt.c
>
>+TESTS_progs += gem_mmap_offset
>+gem_mmap_offset_SOURCES = i915/gem_mmap_offset.c
>+
> TESTS_progs += gem_mmap_offset_exhaustion
> gem_mmap_offset_exhaustion_SOURCES = i915/gem_mmap_offset_exhaustion.c
>
>diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
>new file mode 100644
>index 00000000..b2339111
>--- /dev/null
>+++ b/tests/i915/gem_mmap_offset.c
>@@ -0,0 +1,156 @@
>+/*
>+ * Copyright © 2019 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ */
>+
>+#include "igt.h"
>+#include <errno.h>
>+#include <sys/stat.h>
>+#include <sys/ioctl.h>
>+#include "drm.h"
>+
>+IGT_TEST_DESCRIPTION("Basic MMAP_OFFSET IOCTL tests for mem regions\n");
>+
>+static int mmap_offset_ioctl(int fd, struct local_i915_gem_mmap_offset *arg)
>+{
>+	int err = 0;
>+
>+	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET, arg))
>+		err = -errno;
>+
>+	errno = 0;
>+	return err;
>+}
>+
>+igt_main
>+{
>+	uint8_t *addr;
>+	uint32_t obj_size, batch_size;
>+	uint32_t mem_type, mem_instance;
>+	uint32_t region;
>+	int fd;
>+	const struct intel_memory_region *mr;
>+	struct local_i915_query_memory_region_info *query_info;
>+
>+	igt_fixture {
>+		fd = drm_open_driver(DRIVER_INTEL);
>+		gem_require_mmap_offset(fd);
>+
>+		query_info = gem_query_memory_regions(fd);
>+		igt_assert(query_info);
>+	}
>+
>+	for (mr = intel_memory_regions; mr->region_name; mr++) {
>+		mem_type = mr->memory_type;
>+		mem_instance = mr->memory_instance;
>+		region = INTEL_MEMORY_REGION_ID(mem_type, mem_instance);
>+		batch_size = gem_get_batch_size(fd, region);
>+		obj_size = 4 * batch_size;
>+
>+		igt_subtest_f("bad-object-%s", mr->region_name) {
>+			uint32_t real_handle;
>+			uint32_t handles[20];
>+			int i = 0;
>+
>+			gem_query_require_region(query_info, region);
>+
>+			real_handle = gem_create_in_memory_regions(fd, obj_size,
>+								   region);
>+
>+			handles[i++] = 0xdeadbeef;
>+			for (int bit = 0; bit < 16; bit++)
>+				handles[i++] = real_handle | (1 << (bit + 16));
>+			handles[i] = real_handle + 1;
>+
>+			for (; i >= 0; i--) {
>+				struct local_i915_gem_mmap_offset arg = {
>+					.handle = handles[i],
>+					.flags = LOCAL_I915_MMAP_OFFSET_WB,

May be we should use LOCAL_I915_MMAP_OFFSET_UC - it is possible that
WB/WC is not supported on all memory regions.

>+				};
>+
>+				igt_debug("Trying MMAP IOCTL with handle %x\n",
>+					  handles[i]);
>+				igt_assert_eq(mmap_offset_ioctl(fd, &arg),
>+					      -ENOENT);
>+			}
>+
>+			gem_close(fd, real_handle);
>+		}
>+
>+		igt_subtest_f("basic-%s", mr->region_name) {
>+			struct local_i915_gem_mmap_offset arg;
>+			uint8_t *expected;
>+			uint8_t *buf;
>+
>+			gem_query_require_region(query_info, region);
>+
>+			arg.handle = gem_create_in_memory_regions(fd, obj_size,
>+								  region);
>+			arg.flags = LOCAL_I915_MMAP_OFFSET_WB;

See above comment about using MMAP_OFFSET_UC.

>+
>+			igt_assert_eq(mmap_offset_ioctl(fd, &arg), 0);
>+			addr = mmap64(0, obj_size, PROT_READ | PROT_WRITE,
>+				      MAP_SHARED, fd, arg.offset);
>+			igt_assert(addr != MAP_FAILED);
>+
>+			igt_debug("Testing contents of newly created object.\n");
>+			expected = calloc(obj_size, sizeof(*expected));
>+			igt_assert_eq(memcmp(addr, expected, obj_size), 0);
>+			free(expected);
>+
>+			igt_debug("Testing coherency of writes and mmap reads.\n");
>+			buf = calloc(obj_size, sizeof(*buf));
>+			memset(buf + 1024, 0x01, 1024);
>+			gem_write(fd, arg.handle, 0, buf, obj_size);
>+			igt_assert_eq(memcmp(buf, addr, obj_size), 0);

Is read/write to LMEM supposed to be coherent with CPU?

>+
>+			igt_debug("Testing that mapping stays after close\n");
>+			gem_close(fd, arg.handle);
>+			igt_assert_eq(memcmp(buf, addr, obj_size), 0);
>+			free(buf);
>+
>+			igt_debug("Testing unmapping\n");
>+			munmap(addr, obj_size);
>+		}
>+
>+		igt_subtest_f("short-mmap-%s", mr->region_name) {
>+			uint32_t handle;
>+
>+			gem_query_require_region(query_info, region);
>+
>+			handle = gem_create_in_memory_regions(fd, obj_size,
>+							      region);
>+			igt_assert(obj_size > batch_size);
>+
>+			addr = gem_mmap__cpu(fd, handle, 0, batch_size,
>+					     PROT_WRITE);

It is possible that this will fail if WB is not allowed on a memory
region.

>+			memset(addr, 0, batch_size);
>+			munmap(addr, batch_size);
>+
>+			gem_close(fd, handle);
>+		}
>+	}
>+
>+	igt_fixture {
>+		free(query_info);
>+		close(fd);
>+	}
>+}
>diff --git a/tests/meson.build b/tests/meson.build
>index 755fc9e6..644b5504 100644
>--- a/tests/meson.build
>+++ b/tests/meson.build
>@@ -174,6 +174,7 @@ i915_progs = [
> 	'gem_media_vme',
> 	'gem_mmap',
> 	'gem_mmap_gtt',
>+	'gem_mmap_offset',
> 	'gem_mmap_offset_exhaustion',
> 	'gem_mmap_wc',
> 	'gem_partial_pwrite_pread',
>-- 
>2.23.0
>
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Re: [igt-dev] [PATCH i-g-t v2 3/4] tests/i915/gem_mmap_offset: Add new API test for gem_mmap_offset

[Zbigniew Kempczyński]

On Tue, Nov 19, 2019 at 10:13:37AM -0800, Vanshidhar Konda wrote:

<cut>
> > +			for (; i >= 0; i--) {
> > +				struct local_i915_gem_mmap_offset arg = {
> > +					.handle = handles[i],
> > +					.flags = LOCAL_I915_MMAP_OFFSET_WB,
> 
> May be we should use LOCAL_I915_MMAP_OFFSET_UC - it is possible that
> WB/WC is not supported on all memory regions.

You're right, we want to check object lookup, not PAT feature.
Will be fixed in v3. 
 
> > +				};
> > +
> > +				igt_debug("Trying MMAP IOCTL with handle %x\n",
> > +					  handles[i]);
> > +				igt_assert_eq(mmap_offset_ioctl(fd, &arg),
> > +					      -ENOENT);
> > +			}
> > +
> > +			gem_close(fd, real_handle);
> > +		}
> > +
> > +		igt_subtest_f("basic-%s", mr->region_name) {
> > +			struct local_i915_gem_mmap_offset arg;
> > +			uint8_t *expected;
> > +			uint8_t *buf;
> > +
> > +			gem_query_require_region(query_info, region);
> > +
> > +			arg.handle = gem_create_in_memory_regions(fd, obj_size,
> > +								  region);
> > +			arg.flags = LOCAL_I915_MMAP_OFFSET_WB;
> 
> See above comment about using MMAP_OFFSET_UC.

In this case I think better is to iterate over WB, WC then UC flags. 
I'll add appropriate code around this.
 
> > +
> > +			igt_assert_eq(mmap_offset_ioctl(fd, &arg), 0);
> > +			addr = mmap64(0, obj_size, PROT_READ | PROT_WRITE,
> > +				      MAP_SHARED, fd, arg.offset);
> > +			igt_assert(addr != MAP_FAILED);
> > +
> > +			igt_debug("Testing contents of newly created object.\n");
> > +			expected = calloc(obj_size, sizeof(*expected));
> > +			igt_assert_eq(memcmp(addr, expected, obj_size), 0);
> > +			free(expected);
> > +
> > +			igt_debug("Testing coherency of writes and mmap reads.\n");
> > +			buf = calloc(obj_size, sizeof(*buf));
> > +			memset(buf + 1024, 0x01, 1024);
> > +			gem_write(fd, arg.handle, 0, buf, obj_size);
> > +			igt_assert_eq(memcmp(buf, addr, obj_size), 0);
> 
> Is read/write to LMEM supposed to be coherent with CPU?

I will add appropriate sync code.

> 
> > +
> > +			igt_debug("Testing that mapping stays after close\n");
> > +			gem_close(fd, arg.handle);
> > +			igt_assert_eq(memcmp(buf, addr, obj_size), 0);
> > +			free(buf);
> > +
> > +			igt_debug("Testing unmapping\n");
> > +			munmap(addr, obj_size);
> > +		}
> > +
> > +		igt_subtest_f("short-mmap-%s", mr->region_name) {
> > +			uint32_t handle;
> > +
> > +			gem_query_require_region(query_info, region);
> > +
> > +			handle = gem_create_in_memory_regions(fd, obj_size,
> > +							      region);
> > +			igt_assert(obj_size > batch_size);
> > +
> > +			addr = gem_mmap__cpu(fd, handle, 0, batch_size,
> > +					     PROT_WRITE);
> 
> It is possible that this will fail if WB is not allowed on a memory
> region.

I will add fallback to WC / UC.

Zbigniew

> 
> > +			memset(addr, 0, batch_size);
> > +			munmap(addr, batch_size);
> > +
> > +			gem_close(fd, handle);
> > +		}
> > +	}
> > +
> > +	igt_fixture {
> > +		free(query_info);
> > +		close(fd);
> > +	}
> > +}
> > diff --git a/tests/meson.build b/tests/meson.build
> > index 755fc9e6..644b5504 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -174,6 +174,7 @@ i915_progs = [
> > 	'gem_media_vme',
> > 	'gem_mmap',
> > 	'gem_mmap_gtt',
> > +	'gem_mmap_offset',
> > 	'gem_mmap_offset_exhaustion',
> > 	'gem_mmap_wc',
> > 	'gem_partial_pwrite_pread',
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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[igt-dev] [PATCH i-g-t v2 4/4] tests/i915/gem_exec_basic: Iterate over all memory regions

[Zbigniew Kempczyński]

From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>

As a part of local memory effort we need to make sure, that basic
scenarios are covered for every available memory region. This patch is
an attempt for this problem. If it will be accepted it will be
replicated on each test that can benefit from it.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 tests/i915/gem_exec_basic.c | 109 +++++++++++++++++++++++-------------
 1 file changed, 70 insertions(+), 39 deletions(-)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index 1287860b..4a444916 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -25,12 +25,12 @@
 
 IGT_TEST_DESCRIPTION("Basic sanity check of execbuf-ioctl rings.");
 
-static uint32_t batch_create(int fd)
+static uint32_t batch_create(int fd, uint32_t batch_size, uint32_t region)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	uint32_t handle;
 
-	handle = gem_create(fd, 4096);
+	handle = gem_create_in_memory_regions(fd, batch_size, region);
 	gem_write(fd, handle, 0, &bbe, sizeof(bbe));
 
 	return handle;
@@ -42,7 +42,7 @@ static void batch_fini(int fd, uint32_t handle)
 	gem_close(fd, handle);
 }
 
-static void noop(int fd, uint64_t flags)
+static void noop(int fd, uint64_t flags, uint32_t batch_size, uint32_t region)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
@@ -50,8 +50,7 @@ static void noop(int fd, uint64_t flags)
 	gem_require_ring(fd, flags);
 
 	memset(&exec, 0, sizeof(exec));
-
-	exec.handle = batch_create(fd);
+	exec.handle = batch_create(fd, batch_size, region);
 
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&exec);
@@ -62,7 +61,8 @@ static void noop(int fd, uint64_t flags)
 	batch_fini(fd, exec.handle);
 }
 
-static void readonly(int fd, uint64_t flags)
+static void readonly(int fd, uint64_t flags, uint32_t batch_size,
+		     uint32_t region)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 exec;
@@ -70,39 +70,41 @@ static void readonly(int fd, uint64_t flags)
 	gem_require_ring(fd, flags);
 
 	memset(&exec, 0, sizeof(exec));
-	exec.handle = batch_create(fd);
+	exec.handle = batch_create(fd, batch_size, region);
 
-	execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+	execbuf = mmap(NULL, batch_size, PROT_WRITE,
+		       MAP_ANON | MAP_PRIVATE, -1, 0);
 	igt_assert(execbuf != NULL);
 
 	execbuf->buffers_ptr = to_user_pointer(&exec);
 	execbuf->buffer_count = 1;
 	execbuf->flags = flags;
-	igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
+	igt_assert(mprotect(execbuf, batch_size, PROT_READ) == 0);
 
 	gem_execbuf(fd, execbuf);
 
-	munmap(execbuf, 4096);
-
+	munmap(execbuf, batch_size);
 	batch_fini(fd, exec.handle);
 }
 
-static void gtt(int fd, uint64_t flags)
+static void gtt(int fd, uint64_t flags, uint32_t batch_size, uint32_t region)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 *exec;
 	uint32_t handle;
 
 	gem_require_ring(fd, flags);
+	gem_require_mappable_ggtt(fd);
+	igt_require(IS_SYSTEM_MEMORY_REGION(region));
 
-	handle = gem_create(fd, 4096);
-
+	handle = gem_create_in_memory_regions(fd, handle, region);
 	gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
-	execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
+
+	execbuf = gem_mmap__gtt(fd, handle, batch_size, PROT_WRITE);
 	exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
 	gem_close(fd, handle);
 
-	exec->handle = batch_create(fd);
+	exec->handle = batch_create(fd, batch_size, region);
 
 	execbuf->buffers_ptr = to_user_pointer(exec);
 	execbuf->buffer_count = 1;
@@ -111,36 +113,41 @@ static void gtt(int fd, uint64_t flags)
 	gem_execbuf(fd, execbuf);
 
 	batch_fini(fd, exec->handle);
-	munmap(execbuf, 4096);
+	munmap(execbuf, batch_size);
 }
 
-static void all(int i915)
+static void all(int i915, uint32_t batch_size, uint32_t region)
 {
 	const struct intel_execution_engine2 *e;
 
 	__for_each_physical_engine(i915, e)
-		noop(i915, e->flags);
+		noop(i915, e->flags, batch_size, region);
 }
 
-static void readonly_all(int i915)
+static void readonly_all(int i915, uint32_t batch_size, uint32_t region)
 {
 	const struct intel_execution_engine2 *e;
 
 	__for_each_physical_engine(i915, e)
-		readonly(i915, e->flags);
+		readonly(i915, e->flags, batch_size, region);
 }
 
-static void gtt_all(int i915)
+static void gtt_all(int i915, uint32_t batch_size, uint32_t region)
 {
 	const struct intel_execution_engine2 *e;
 
 	__for_each_physical_engine(i915, e)
-		gtt(i915, e->flags);
+		gtt(i915, e->flags, batch_size, region);
 }
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const struct intel_memory_region *mr;
+	struct local_i915_query_memory_region_info *query_info;
+	uint32_t mem_type, mem_instance;
+	uint32_t batch_size;
+	uint32_t region;
 	int fd = -1;
 
 	igt_fixture {
@@ -148,27 +155,51 @@ igt_main
 		igt_require_gem(fd);
 
 		igt_fork_hang_detector(fd);
-	}
-
-	igt_subtest("basic-all")
-		all(fd);
 
-	igt_subtest("readonly-all")
-		readonly_all(fd);
-
-	igt_subtest("gtt-all")
-		gtt_all(fd);
+		query_info = gem_query_memory_regions(fd);
+		igt_assert(query_info);
+	}
 
-	__for_each_physical_engine(fd, e) {
-		igt_subtest_f("basic-%s", e->name)
-			noop(fd, e->flags);
-		igt_subtest_f("readonly-%s", e->name)
-			readonly(fd, e->flags);
-		igt_subtest_f("gtt-%s", e->name)
-			gtt(fd, e->flags);
+	for (mr = intel_memory_regions; mr->region_name; mr++) {
+		mem_type = mr->memory_type;
+		mem_instance = mr->memory_instance;
+		region = INTEL_MEMORY_REGION_ID(mem_type, mem_instance);
+
+		batch_size = gem_get_batch_size(fd, region);
+
+		igt_subtest_f("basic-%s-all", mr->region_name) {
+			gem_query_require_region(query_info, region);
+			all(fd, batch_size, region);
+		}
+
+		igt_subtest_f("readonly-%s-all", mr->region_name) {
+			gem_query_require_region(query_info, region);
+			readonly_all(fd, batch_size, region);
+		}
+
+		igt_subtest_f("gtt-%s-all", mr->region_name) {
+			gem_query_require_region(query_info, region);
+			gtt_all(fd, batch_size, region);
+		}
+
+		__for_each_physical_engine(fd, e) {
+			igt_subtest_f("basic-%s-%s", mr->region_name, e->name) {
+				gem_query_require_region(query_info, region);
+				noop(fd, e->flags, batch_size, region);
+			}
+			igt_subtest_f("readonly-%s-%s", mr->region_name, e->name) {
+				gem_query_require_region(query_info, region);
+				readonly(fd, e->flags, batch_size, region);
+			}
+			igt_subtest_f("gtt-%s-%s", mr->region_name, e->name) {
+				gem_query_require_region(query_info, region);
+				gtt(fd, e->flags, batch_size, region);
+			}
+		}
 	}
 
 	igt_fixture {
+		free(query_info);
 		igt_stop_hang_detector();
 		close(fd);
 	}
-- 
2.23.0

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Re: [igt-dev] [PATCH i-g-t v2 4/4] tests/i915/gem_exec_basic: Iterate over all memory regions

[Vanshidhar Konda]

On Tue, Nov 19, 2019 at 05:02:23PM +0100, Zbigniew Kempczyński wrote:
>From: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
>
>As a part of local memory effort we need to make sure, that basic
>scenarios are covered for every available memory region. This patch is
>an attempt for this problem. If it will be accepted it will be
>replicated on each test that can benefit from it.
>
>Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
>Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>Cc: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>---
> tests/i915/gem_exec_basic.c | 109 +++++++++++++++++++++++-------------
> 1 file changed, 70 insertions(+), 39 deletions(-)
>
>diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
>index 1287860b..4a444916 100644
>--- a/tests/i915/gem_exec_basic.c
>+++ b/tests/i915/gem_exec_basic.c
>@@ -25,12 +25,12 @@
>
> IGT_TEST_DESCRIPTION("Basic sanity check of execbuf-ioctl rings.");
>
>-static uint32_t batch_create(int fd)
>+static uint32_t batch_create(int fd, uint32_t batch_size, uint32_t region)
> {
> 	const uint32_t bbe = MI_BATCH_BUFFER_END;
> 	uint32_t handle;
>
>-	handle = gem_create(fd, 4096);
>+	handle = gem_create_in_memory_regions(fd, batch_size, region);
> 	gem_write(fd, handle, 0, &bbe, sizeof(bbe));
>
> 	return handle;
>@@ -42,7 +42,7 @@ static void batch_fini(int fd, uint32_t handle)
> 	gem_close(fd, handle);
> }
>
>-static void noop(int fd, uint64_t flags)
>+static void noop(int fd, uint64_t flags, uint32_t batch_size, uint32_t region)
> {
> 	struct drm_i915_gem_execbuffer2 execbuf;
> 	struct drm_i915_gem_exec_object2 exec;
>@@ -50,8 +50,7 @@ static void noop(int fd, uint64_t flags)
> 	gem_require_ring(fd, flags);
>
> 	memset(&exec, 0, sizeof(exec));
>-
>-	exec.handle = batch_create(fd);
>+	exec.handle = batch_create(fd, batch_size, region);
>
> 	memset(&execbuf, 0, sizeof(execbuf));
> 	execbuf.buffers_ptr = to_user_pointer(&exec);
>@@ -62,7 +61,8 @@ static void noop(int fd, uint64_t flags)
> 	batch_fini(fd, exec.handle);
> }
>
>-static void readonly(int fd, uint64_t flags)
>+static void readonly(int fd, uint64_t flags, uint32_t batch_size,
>+		     uint32_t region)
> {
> 	struct drm_i915_gem_execbuffer2 *execbuf;
> 	struct drm_i915_gem_exec_object2 exec;
>@@ -70,39 +70,41 @@ static void readonly(int fd, uint64_t flags)
> 	gem_require_ring(fd, flags);
>
> 	memset(&exec, 0, sizeof(exec));
>-	exec.handle = batch_create(fd);
>+	exec.handle = batch_create(fd, batch_size, region);
>
>-	execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
>+	execbuf = mmap(NULL, batch_size, PROT_WRITE,
>+		       MAP_ANON | MAP_PRIVATE, -1, 0);
> 	igt_assert(execbuf != NULL);
>
> 	execbuf->buffers_ptr = to_user_pointer(&exec);
> 	execbuf->buffer_count = 1;
> 	execbuf->flags = flags;
>-	igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
>+	igt_assert(mprotect(execbuf, batch_size, PROT_READ) == 0);
>
> 	gem_execbuf(fd, execbuf);
>
>-	munmap(execbuf, 4096);
>-
>+	munmap(execbuf, batch_size);
> 	batch_fini(fd, exec.handle);
> }
>
>-static void gtt(int fd, uint64_t flags)
>+static void gtt(int fd, uint64_t flags, uint32_t batch_size, uint32_t region)
> {
> 	struct drm_i915_gem_execbuffer2 *execbuf;
> 	struct drm_i915_gem_exec_object2 *exec;
> 	uint32_t handle;
>
> 	gem_require_ring(fd, flags);
>+	gem_require_mappable_ggtt(fd);
>+	igt_require(IS_SYSTEM_MEMORY_REGION(region));
>
>-	handle = gem_create(fd, 4096);
>-
>+	handle = gem_create_in_memory_regions(fd, handle, region);
> 	gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>-	execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
>+
>+	execbuf = gem_mmap__gtt(fd, handle, batch_size, PROT_WRITE);
> 	exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
> 	gem_close(fd, handle);
>
>-	exec->handle = batch_create(fd);
>+	exec->handle = batch_create(fd, batch_size, region);
>
> 	execbuf->buffers_ptr = to_user_pointer(exec);
> 	execbuf->buffer_count = 1;
>@@ -111,36 +113,41 @@ static void gtt(int fd, uint64_t flags)
> 	gem_execbuf(fd, execbuf);
>
> 	batch_fini(fd, exec->handle);
>-	munmap(execbuf, 4096);
>+	munmap(execbuf, batch_size);
> }
>
>-static void all(int i915)
>+static void all(int i915, uint32_t batch_size, uint32_t region)
> {
> 	const struct intel_execution_engine2 *e;
>
> 	__for_each_physical_engine(i915, e)
>-		noop(i915, e->flags);
>+		noop(i915, e->flags, batch_size, region);
> }
>
>-static void readonly_all(int i915)
>+static void readonly_all(int i915, uint32_t batch_size, uint32_t region)
> {
> 	const struct intel_execution_engine2 *e;
>
> 	__for_each_physical_engine(i915, e)
>-		readonly(i915, e->flags);
>+		readonly(i915, e->flags, batch_size, region);
> }
>
>-static void gtt_all(int i915)
>+static void gtt_all(int i915, uint32_t batch_size, uint32_t region)
> {
> 	const struct intel_execution_engine2 *e;
>
> 	__for_each_physical_engine(i915, e)
>-		gtt(i915, e->flags);
>+		gtt(i915, e->flags, batch_size, region);
> }
>
> igt_main
> {
> 	const struct intel_execution_engine2 *e;
>+	const struct intel_memory_region *mr;
>+	struct local_i915_query_memory_region_info *query_info;
>+	uint32_t mem_type, mem_instance;
>+	uint32_t batch_size;
>+	uint32_t region;
> 	int fd = -1;
>
> 	igt_fixture {
>@@ -148,27 +155,51 @@ igt_main
> 		igt_require_gem(fd);
>
> 		igt_fork_hang_detector(fd);
>-	}
>-
>-	igt_subtest("basic-all")
>-		all(fd);
>
>-	igt_subtest("readonly-all")
>-		readonly_all(fd);
>-
>-	igt_subtest("gtt-all")
>-		gtt_all(fd);
>+		query_info = gem_query_memory_regions(fd);
>+		igt_assert(query_info);
>+	}
>
>-	__for_each_physical_engine(fd, e) {
>-		igt_subtest_f("basic-%s", e->name)
>-			noop(fd, e->flags);
>-		igt_subtest_f("readonly-%s", e->name)
>-			readonly(fd, e->flags);
>-		igt_subtest_f("gtt-%s", e->name)
>-			gtt(fd, e->flags);
>+	for (mr = intel_memory_regions; mr->region_name; mr++) {
>+		mem_type = mr->memory_type;
>+		mem_instance = mr->memory_instance;
>+		region = INTEL_MEMORY_REGION_ID(mem_type, mem_instance);
>+
>+		batch_size = gem_get_batch_size(fd, region);
>+
>+		igt_subtest_f("basic-%s-all", mr->region_name) {
>+			gem_query_require_region(query_info, region);
>+			all(fd, batch_size, region);
>+		}
>+
>+		igt_subtest_f("readonly-%s-all", mr->region_name) {
>+			gem_query_require_region(query_info, region);
>+			readonly_all(fd, batch_size, region);
>+		}
>+
>+		igt_subtest_f("gtt-%s-all", mr->region_name) {
>+			gem_query_require_region(query_info, region);
>+			gtt_all(fd, batch_size, region);
>+		}
>+
>+		__for_each_physical_engine(fd, e) {
>+			igt_subtest_f("basic-%s-%s", mr->region_name, e->name) {
>+				gem_query_require_region(query_info, region);
>+				noop(fd, e->flags, batch_size, region);
>+			}
>+			igt_subtest_f("readonly-%s-%s", mr->region_name, e->name) {
>+				gem_query_require_region(query_info, region);
>+				readonly(fd, e->flags, batch_size, region);
>+			}
>+			igt_subtest_f("gtt-%s-%s", mr->region_name, e->name) {
>+				gem_query_require_region(query_info, region);
>+				gtt(fd, e->flags, batch_size, region);
>+			}
>+		}
> 	}
>
> 	igt_fixture {
>+		free(query_info);
> 		igt_stop_hang_detector();
> 		close(fd);
> 	}

Reviewed-by: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
>-- 
>2.23.0
>
>_______________________________________________
>igt-dev mailing list
>igt-dev@lists.freedesktop.org
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[igt-dev] ✗ GitLab.Pipeline: warning for Basic LMEM support in IGT (rev2)

[Patchwork]

== Series Details ==

Series: Basic LMEM support in IGT (rev2)
URL   : https://patchwork.freedesktop.org/series/65171/
State : warning

== Summary ==

Did not get list of undocumented tests for this run, something is wrong!

Other than that, pipeline status: FAILED.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/80595 for the overview.

build:tests-debian-meson-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/976769):
  [149/869] Compiling C object 'tests/59830eb@@kms_cursor_legacy@exe/kms_cursor_legacy.c.o'.
  [150/869] Compiling C object 'tests/59830eb@@kms_frontbuffer_tracking@exe/kms_frontbuffer_tracking.c.o'.
  ninja: build stopped: subcommand failed.
  ninja: Entering directory `build'
  [1/723] Generating version.h with a custom command.
  [2/721] Linking static target lib/libigt-igt_gvt_c.a.
  [3/721] Compiling C object 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o'.
  FAILED: lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o 
  /usr/bin/arm-linux-gnueabihf-gcc -Ilib/76b5a35@@igt-i915_intel_memory_region_c@sta -Ilib -I../lib -I../include/drm-uapi -I../lib/stubs/syscalls -I. -I../ -I../lib/stubs/drm -I/usr/include/cairo -I/usr/include/glib-2.0 -I/usr/lib/arm-linux-gnueabihf/glib-2.0/include -I/usr/include/pixman-1 -I/usr/include/freetype2 -I/usr/include/libpng16 -I/usr/include/libdrm -I/usr/include/valgrind -I/usr/include/alsa -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -std=gnu11 -O2 -g -D_GNU_SOURCE -include config.h -D_FORTIFY_SOURCE=2 -Wbad-function-cast -Wdeclaration-after-statement -Wformat=2 -Wlogical-op -Wmissing-declarations -Wmissing-format-attribute -Wmissing-noreturn -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wredundant-decls -Wshadow -Wstrict-prototypes -Wuninitialized -Wunused -Wno-clobbered -Wno-maybe-uninitialized -Wno-missing-field-initializers -Wno-pointer-arith -Wno-sign-compare -Wno-type-limits -Wno-unused-parameter -Wno-unused-result -Werror=address -Werror=array-bounds -Werror=implicit -Werror=init-self -Werror=int-to-pointer-cast -Werror=main -Werror=missing-braces -Werror=nonnull -Werror=pointer-to-int-cast -Werror=return-type -Werror=sequence-point -Werror=trigraphs -Werror=write-strings -fno-builtin-malloc -fno-builtin-calloc -fPIC -pthread '-DIGT_DATADIR="/usr/local/share/igt-gpu-tools"' '-DIGT_SRCDIR="/builds/gfx-ci/igt-ci-tags/tests"' '-DIGT_LOG_DOMAIN="i915/intel_memory_region"'  -MD -MQ 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o' -MF 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o.d' -o 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o' -c ../lib/i915/intel_memory_region.c
  {standard input}: Assembler messages:
  {standard input}:246: Error: bad instruction `bsrl r1,r3'
  {standard input}:571: Error: bad instruction `bsrl r4,r3'
  ninja: build stopped: subcommand failed.
  section_end:1574182097:build_script
  ^[[0Ksection_start:1574182097:after_script
  ^[[0Ksection_end:1574182098:after_script
  ^[[0Ksection_start:1574182098:upload_artifacts_on_failure
  ^[[0Ksection_end:1574182100:upload_artifacts_on_failure
  ^[[0K^[[31;1mERROR: Job failed: exit code 1
  ^[[0;m

build:tests-debian-meson-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/976770):
  [155/869] Compiling C object 'lib/76b5a35@@igt-igt_aux_c@sta/igt_aux.c.o'.
  [156/869] Compiling C object 'tests/59830eb@@kms_cursor_legacy@exe/kms_cursor_legacy.c.o'.
  [157/869] Compiling C object 'tests/59830eb@@kms_frontbuffer_tracking@exe/kms_frontbuffer_tracking.c.o'.
  ninja: build stopped: subcommand failed.
  ninja: Entering directory `build'
  [1/716] Generating version.h with a custom command.
  [2/714] Compiling C object 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o'.
  FAILED: lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o 
  /usr/bin/aarch64-linux-gnu-gcc -Ilib/76b5a35@@igt-i915_intel_memory_region_c@sta -Ilib -I../lib -I../include/drm-uapi -I../lib/stubs/syscalls -I. -I../ -I../lib/stubs/drm -I/usr/include/cairo -I/usr/include/glib-2.0 -I/usr/lib/aarch64-linux-gnu/glib-2.0/include -I/usr/include/pixman-1 -I/usr/include/freetype2 -I/usr/include/libpng16 -I/usr/include/libdrm -I/usr/include/valgrind -I/usr/include/alsa -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -std=gnu11 -O2 -g -D_GNU_SOURCE -include config.h -D_FORTIFY_SOURCE=2 -Wbad-function-cast -Wdeclaration-after-statement -Wformat=2 -Wlogical-op -Wmissing-declarations -Wmissing-format-attribute -Wmissing-noreturn -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wredundant-decls -Wshadow -Wstrict-prototypes -Wuninitialized -Wunused -Wno-clobbered -Wno-maybe-uninitialized -Wno-missing-field-initializers -Wno-pointer-arith -Wno-sign-compare -Wno-type-limits -Wno-unused-parameter -Wno-unused-result -Werror=address -Werror=array-bounds -Werror=implicit -Werror=init-self -Werror=int-to-pointer-cast -Werror=main -Werror=missing-braces -Werror=nonnull -Werror=pointer-to-int-cast -Werror=return-type -Werror=sequence-point -Werror=trigraphs -Werror=write-strings -fno-builtin-malloc -fno-builtin-calloc -fPIC -pthread '-DIGT_DATADIR="/usr/local/share/igt-gpu-tools"' '-DIGT_SRCDIR="/builds/gfx-ci/igt-ci-tags/tests"' '-DIGT_LOG_DOMAIN="i915/intel_memory_region"'  -MD -MQ 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o' -MF 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o.d' -o 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o' -c ../lib/i915/intel_memory_region.c
  {standard input}: Assembler messages:
  {standard input}:185: Error: unknown mnemonic `bsrl' -- `bsrl x1,x2'
  {standard input}:484: Error: unknown mnemonic `bsrl' -- `bsrl x3,x2'
  ninja: build stopped: subcommand failed.
  section_end:1574182116:build_script
  ^[[0Ksection_start:1574182116:after_script
  ^[[0Ksection_end:1574182118:after_script
  ^[[0Ksection_start:1574182118:upload_artifacts_on_failure
  ^[[0Ksection_end:1574182119:upload_artifacts_on_failure
  ^[[0K^[[31;1mERROR: Job failed: exit code 1
  ^[[0;m

build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/976771):
  [140/869] Compiling C object 'tests/59830eb@@kms_frontbuffer_tracking@exe/kms_frontbuffer_tracking.c.o'.
  ninja: build stopped: subcommand failed.
  ninja: Entering directory `build'
  [1/732] Generating version.h with a custom command.
  [2/731] Linking static target lib/libigt-drmtest_c.a.
  [3/731] Linking static target lib/libigt-igt_gvt_c.a.
  [4/731] Compiling C object 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o'.
  FAILED: lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o 
  /usr/bin/mips-linux-gnu-gcc -Ilib/76b5a35@@igt-i915_intel_memory_region_c@sta -Ilib -I../lib -I../include/drm-uapi -I../lib/stubs/syscalls -I. -I../ -I../lib/stubs/drm -I/usr/include/cairo -I/usr/include/glib-2.0 -I/usr/lib/mips-linux-gnu/glib-2.0/include -I/usr/include/pixman-1 -I/usr/include/freetype2 -I/usr/include/libpng16 -I/usr/include/libdrm -I/usr/include/valgrind -I/usr/include/alsa -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -std=gnu11 -O2 -g -D_GNU_SOURCE -include config.h -D_FORTIFY_SOURCE=2 -Wbad-function-cast -Wdeclaration-after-statement -Wformat=2 -Wlogical-op -Wmissing-declarations -Wmissing-format-attribute -Wmissing-noreturn -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wredundant-decls -Wshadow -Wstrict-prototypes -Wuninitialized -Wunused -Wno-clobbered -Wno-maybe-uninitialized -Wno-missing-field-initializers -Wno-pointer-arith -Wno-sign-compare -Wno-type-limits -Wno-unused-parameter -Wno-unused-result -Werror=address -Werror=array-bounds -Werror=implicit -Werror=init-self -Werror=int-to-pointer-cast -Werror=main -Werror=missing-braces -Werror=nonnull -Werror=pointer-to-int-cast -Werror=return-type -Werror=sequence-point -Werror=trigraphs -Werror=write-strings -fno-builtin-malloc -fno-builtin-calloc -fPIC -pthread '-DIGT_DATADIR="/usr/local/share/igt-gpu-tools"' '-DIGT_SRCDIR="/builds/gfx-ci/igt-ci-tags/tests"' '-DIGT_LOG_DOMAIN="i915/intel_memory_region"'  -MD -MQ 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o' -MF 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o.d' -o 'lib/76b5a35@@igt-i915_intel_memory_region_c@sta/i915_intel_memory_region.c.o' -c ../lib/i915/intel_memory_region.c
  {standard input}: Assembler messages:
  {standard input}:256: Error: unrecognized opcode `bsrl $5,$2'
  {standard input}:655: Error: unrecognized opcode `bsrl $7,$3'
  ninja: build stopped: subcommand failed.
  section_end:1574182135:build_script
  ^[[0Ksection_start:1574182135:after_script
  ^[[0Ksection_end:1574182137:after_script
  ^[[0Ksection_start:1574182137:upload_artifacts_on_failure
  ^[[0Ksection_end:1574182138:upload_artifacts_on_failure
  ^[[0K^[[31;1mERROR: Job failed: exit code 1
  ^[[0;m

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/80595
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igt-dev@lists.freedesktop.org
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[igt-dev] ✗ Fi.CI.BAT: failure for Basic LMEM support in IGT (rev2)

[Patchwork]

== Series Details ==

Series: Basic LMEM support in IGT (rev2)
URL   : https://patchwork.freedesktop.org/series/65171/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7373 -> IGTPW_3728
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3728 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3728, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3728:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_basic@basic-all:
    - fi-icl-u2:          [PASS][1] -> [SKIP][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-u2/igt@gem_exec_basic@basic-all.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-u2/igt@gem_exec_basic@basic-all.html
    - fi-cml-u2:          [PASS][3] -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-cml-u2/igt@gem_exec_basic@basic-all.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-cml-u2/igt@gem_exec_basic@basic-all.html
    - fi-icl-u3:          [PASS][5] -> [SKIP][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-u3/igt@gem_exec_basic@basic-all.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-u3/igt@gem_exec_basic@basic-all.html
    - fi-cml-s:           [PASS][7] -> [SKIP][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-cml-s/igt@gem_exec_basic@basic-all.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-cml-s/igt@gem_exec_basic@basic-all.html
    - fi-icl-y:           [PASS][9] -> [SKIP][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-y/igt@gem_exec_basic@basic-all.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-y/igt@gem_exec_basic@basic-all.html
    - fi-icl-dsi:         [PASS][11] -> [SKIP][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-dsi/igt@gem_exec_basic@basic-all.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-dsi/igt@gem_exec_basic@basic-all.html
    - fi-icl-guc:         [PASS][13] -> [SKIP][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-guc/igt@gem_exec_basic@basic-all.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-guc/igt@gem_exec_basic@basic-all.html

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
    - fi-hsw-4770:        [PASS][15] -> [FAIL][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-hsw-4770/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-hsw-4770/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
    - fi-blb-e6850:       [PASS][17] -> [FAIL][18] +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-blb-e6850/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-blb-e6850/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
    - fi-ilk-650:         [PASS][19] -> [FAIL][20] +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-ilk-650/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-ilk-650/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
    - fi-snb-2520m:       [PASS][21] -> [FAIL][22] +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-snb-2520m/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-snb-2520m/igt@gem_mmap_gtt@basic-small-bo-tiledx.html

  * igt@gem_mmap_gtt@basic-small-bo-tiledy:
    - fi-bwr-2160:        [PASS][23] -> [FAIL][24] +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bwr-2160/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bwr-2160/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-kbl-guc:         [PASS][25] -> [FAIL][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-kbl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-kbl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-bsw-nick:        [PASS][27] -> [FAIL][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bsw-nick/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bsw-nick/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-kbl-r:           [PASS][29] -> [FAIL][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-kbl-r/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-kbl-r/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-bsw-kefka:       [PASS][31] -> [FAIL][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bsw-kefka/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bsw-kefka/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-kbl-soraka:      [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-kbl-soraka/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-kbl-soraka/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-icl-u3:          [PASS][35] -> [FAIL][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-skl-6770hq:      [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-skl-6770hq/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-skl-6770hq/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-snb-2600:        [PASS][39] -> [FAIL][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-snb-2600/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-snb-2600/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-cfl-guc:         [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-cfl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-cfl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-skl-lmem:        [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-skl-lmem/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-skl-lmem/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-byt-j1900:       [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-byt-j1900/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-byt-j1900/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-skl-6700k2:      [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-skl-6700k2/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-skl-6700k2/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-byt-n2820:       [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-byt-n2820/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-byt-n2820/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-cfl-8700k:       [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-cfl-8700k/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-cfl-8700k/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-apl-guc:         [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-apl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-apl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-icl-dsi:         [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-bdw-5557u:       [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bdw-5557u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bdw-5557u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-pnv-d510:        [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-pnv-d510/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-pnv-d510/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-skl-6600u:       [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-skl-6600u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-skl-6600u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-skl-guc:         [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-skl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-skl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-icl-y:           [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-y/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-y/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-hsw-4770r:       NOTRUN -> [FAIL][67] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-hsw-4770r/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-kbl-7500u:       [PASS][68] -> [FAIL][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-kbl-7500u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-kbl-7500u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-hsw-peppy:       [PASS][70] -> [FAIL][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-hsw-peppy/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-hsw-peppy/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-kbl-8809g:       [PASS][72] -> [FAIL][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-kbl-8809g/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-kbl-8809g/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-glk-dsi:         [PASS][74] -> [FAIL][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-glk-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-glk-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-kbl-x1275:       [PASS][76] -> [FAIL][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-kbl-x1275/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-kbl-x1275/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-bsw-n3050:       [PASS][78] -> [FAIL][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bsw-n3050/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bsw-n3050/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-ivb-3770:        [PASS][80] -> [FAIL][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-ivb-3770/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-ivb-3770/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-cml-u2:          [PASS][82] -> [FAIL][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-cml-u2/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-cml-u2/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-icl-u2:          [PASS][84] -> [FAIL][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-u2/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-u2/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-icl-guc:         [PASS][86] -> [FAIL][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-guc/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-bxt-dsi:         [PASS][88] -> [FAIL][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bxt-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bxt-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
    - fi-whl-u:           [PASS][90] -> [FAIL][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-whl-u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-whl-u/igt@gem_mmap_gtt@basic-small-bo-tiledy.html

  * igt@gem_workarounds@basic-read:
    - fi-icl-dsi:         [PASS][92] -> [TIMEOUT][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-dsi/igt@gem_workarounds@basic-read.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-dsi/igt@gem_workarounds@basic-read.html
    - fi-cml-u2:          [PASS][94] -> [TIMEOUT][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-cml-u2/igt@gem_workarounds@basic-read.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-cml-u2/igt@gem_workarounds@basic-read.html
    - fi-icl-y:           [PASS][96] -> [TIMEOUT][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-y/igt@gem_workarounds@basic-read.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-y/igt@gem_workarounds@basic-read.html
    - fi-icl-u3:          [PASS][98] -> [TIMEOUT][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-u3/igt@gem_workarounds@basic-read.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-u3/igt@gem_workarounds@basic-read.html
    - fi-glk-dsi:         [PASS][100] -> [CRASH][101] +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-glk-dsi/igt@gem_workarounds@basic-read.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-glk-dsi/igt@gem_workarounds@basic-read.html
    - fi-icl-guc:         [PASS][102] -> [TIMEOUT][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-guc/igt@gem_workarounds@basic-read.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-guc/igt@gem_workarounds@basic-read.html
    - fi-icl-u2:          [PASS][104] -> [TIMEOUT][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-u2/igt@gem_workarounds@basic-read.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-u2/igt@gem_workarounds@basic-read.html
    - fi-bsw-nick:        [PASS][106] -> [CRASH][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bsw-nick/igt@gem_workarounds@basic-read.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bsw-nick/igt@gem_workarounds@basic-read.html
    - fi-bdw-5557u:       [PASS][108] -> [TIMEOUT][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bdw-5557u/igt@gem_workarounds@basic-read.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bdw-5557u/igt@gem_workarounds@basic-read.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          [PASS][110] -> [CRASH][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
    - fi-bsw-n3050:       [PASS][112] -> [CRASH][113] +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bsw-n3050/igt@kms_frontbuffer_tracking@basic.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bsw-n3050/igt@kms_frontbuffer_tracking@basic.html
    - fi-bsw-kefka:       [PASS][114] -> [CRASH][115] +1 similar issue
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bsw-kefka/igt@kms_frontbuffer_tracking@basic.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bsw-kefka/igt@kms_frontbuffer_tracking@basic.html
    - fi-kbl-soraka:      [PASS][116] -> [CRASH][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-kbl-soraka/igt@kms_frontbuffer_tracking@basic.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-kbl-soraka/igt@kms_frontbuffer_tracking@basic.html
    - fi-icl-guc:         [PASS][118] -> [CRASH][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
    - fi-bxt-dsi:         [PASS][120] -> [CRASH][121] +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-bxt-dsi/igt@kms_frontbuffer_tracking@basic.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-bxt-dsi/igt@kms_frontbuffer_tracking@basic.html
    - fi-ivb-3770:        [PASS][122] -> [CRASH][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-ivb-3770/igt@kms_frontbuffer_tracking@basic.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-ivb-3770/igt@kms_frontbuffer_tracking@basic.html
    - fi-skl-6700k2:      [PASS][124] -> [CRASH][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-skl-6700k2/igt@kms_frontbuffer_tracking@basic.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-skl-6700k2/igt@kms_frontbuffer_tracking@basic.html
    - fi-cml-u2:          [PASS][126] -> [CRASH][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
    - fi-apl-guc:         [PASS][128] -> [CRASH][129] +1 similar issue
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-apl-guc/igt@kms_frontbuffer_tracking@basic.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-apl-guc/igt@kms_frontbuffer_tracking@basic.html
    - fi-byt-j1900:       [PASS][130] -> [CRASH][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-byt-j1900/igt@kms_frontbuffer_tracking@basic.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-byt-j1900/igt@kms_frontbuffer_tracking@basic.html
    - fi-hsw-4770:        [PASS][132] -> [CRASH][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-hsw-4770/igt@kms_frontbuffer_tracking@basic.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/fi-hsw-4770/igt@kms_frontbuffer_tracking@basic.html
    - fi-skl-6600u:       [PASS][134] -> [CRASH][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7373/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html
   [135]: https://intel-gfx-ci.01

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3728/index.html
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