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* [igt-dev] [PATCH i-g-t 1/2] tests/kms_chamelium: Fix dp-mode-timings test
@ 2020-04-07  9:00 Arkadiusz Hiler
  2020-04-07  9:00 ` [igt-dev] [PATCH i-g-t 2/2] HAX: add dp-mode-timings to BAT Arkadiusz Hiler
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Arkadiusz Hiler @ 2020-04-07  9:00 UTC (permalink / raw)
  To: igt-dev; +Cc: Nidhi Gupta

Chamelium provides us with hsync_offset value which is read form its
receiver register described as "Hsync start edge to H active start
edge", vsync_offest is analogous.

Let's calculate the correct things on IGT side.

Cc: Nidhi Gupta <nidhi1.gupta@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
 tests/kms_chamelium.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/tests/kms_chamelium.c b/tests/kms_chamelium.c
index 77c203d3..19df784b 100644
--- a/tests/kms_chamelium.c
+++ b/tests/kms_chamelium.c
@@ -915,10 +915,14 @@ static void check_mode(struct chamelium *chamelium, struct chamelium_port *port,
 	chamelium_port_get_video_params(chamelium, port, &video_params);
 
 	mode_clock = (double) mode->clock / 1000;
-	mode_hsync_offset = mode->hsync_start - mode->hdisplay;
-	mode_vsync_offset = mode->vsync_start - mode->vdisplay;
+
+	/* this is what chamelium understands as offsets */
+	mode_hsync_offset = mode->htotal - mode->hsync_start;
+	mode_vsync_offset = mode->vtotal - mode->vsync_start;
+
 	mode_hsync_width = mode->hsync_end - mode->hsync_start;
 	mode_vsync_width = mode->vsync_end - mode->vsync_start;
+
 	mode_hsync_polarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
 	mode_vsync_polarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
 
-- 
2.24.1

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^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] tests/kms_chamelium: Fix dp-mode-timings test
@ 2020-04-07 10:13 Arkadiusz Hiler
  2020-04-08  9:17 ` Petri Latvala
  0 siblings, 1 reply; 7+ messages in thread
From: Arkadiusz Hiler @ 2020-04-07 10:13 UTC (permalink / raw)
  To: igt-dev; +Cc: Nidhi Gupta, Petri Latvala

Chamelium provides us with hsync_offset value which is read form its
receiver register described as "Hsync start edge to H active start
edge", vsync_offest is analogous.

Let's calculate the correct things on IGT side.

v2: keep the original checks for HDMI (Petri)

Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Nidhi Gupta <nidhi1.gupta@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
 tests/kms_chamelium.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/tests/kms_chamelium.c b/tests/kms_chamelium.c
index 77c203d3..69c9de4e 100644
--- a/tests/kms_chamelium.c
+++ b/tests/kms_chamelium.c
@@ -915,10 +915,20 @@ static void check_mode(struct chamelium *chamelium, struct chamelium_port *port,
 	chamelium_port_get_video_params(chamelium, port, &video_params);
 
 	mode_clock = (double) mode->clock / 1000;
-	mode_hsync_offset = mode->hsync_start - mode->hdisplay;
-	mode_vsync_offset = mode->vsync_start - mode->vdisplay;
+
+	if (chamelium_port_get_type(port) == DRM_MODE_CONNECTOR_DisplayPort) {
+		/* this is what chamelium understands as offsets for DP */
+		mode_hsync_offset = mode->htotal - mode->hsync_start;
+		mode_vsync_offset = mode->vtotal - mode->vsync_start;
+	} else {
+		/* and this is what they are for other connectors */
+		mode_hsync_offset = mode->hsync_start - mode->hdisplay;
+		mode_vsync_offset = mode->vsync_start - mode->vdisplay;
+	}
+
 	mode_hsync_width = mode->hsync_end - mode->hsync_start;
 	mode_vsync_width = mode->vsync_end - mode->vsync_start;
+
 	mode_hsync_polarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
 	mode_vsync_polarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
 
-- 
2.24.1

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^ permalink raw reply related	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-04-08  9:28 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-04-07  9:00 [igt-dev] [PATCH i-g-t 1/2] tests/kms_chamelium: Fix dp-mode-timings test Arkadiusz Hiler
2020-04-07  9:00 ` [igt-dev] [PATCH i-g-t 2/2] HAX: add dp-mode-timings to BAT Arkadiusz Hiler
2020-04-07  9:50 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] tests/kms_chamelium: Fix dp-mode-timings test Patchwork
2020-04-07 16:19 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2020-04-07 10:13 [igt-dev] [PATCH i-g-t 1/2] " Arkadiusz Hiler
2020-04-08  9:17 ` Petri Latvala
2020-04-08  9:28   ` Arkadiusz Hiler

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