* [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test
@ 2020-11-20 9:36 Mika Kahola
2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 1/4] tests/kms_ccs: Add debug information on format modifier Mika Kahola
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Mika Kahola @ 2020-11-20 9:36 UTC (permalink / raw)
To: igt-dev
The patch proposes a method to test CCS with clear color
capability.
The test paints a solid color on primary fb and a small sprite fb.
These are cleared with fast clear feature. A crc is captured and
compared against the reference.
v2: Modify _gen9_render_copyfunc to support fast clear (Matt)
Enable fast clear bit on 3D sequence (Matt)
Add helper function to figure out clear color modifier (Matt)
v3: Remove unrelated line additions/removes
v4: Fast clear with color (Imre)
v5: Write raw 32-bit color values to register (Imre)
Require 32-bit color format
v6: Rebase to use batchbuffer without libdrm dependency
v7: Enable clear color (Nanley)
v8: Various cleanups (Imre)
v9: Splitting patch series into three patches (Imre)
v10: Remove switch from CCS CC modifier check (Imre)
Color map conversion (Imre)
Separate function to check CCS CC plane (Imre)
Removed left-over comment (Imre)
Replace inte_bb_reset() with intel_bb_sync() and
intel_bb_destroy() when cleaning up (Imre)
Fix logic to test CCS clear color only with
XRGB8888 format (Imre)
Move fast clear to it's own function (Imre)
Mika Kahola (4):
tests/kms_ccs: Add debug information on format modifier
lib/rendercopy: Enable fast clear
lib/intel_aux_pgtable: Initialize aux pagetable for fast clear
tests/kms_ccs: CCS Clear Color test
lib/gen8_render.h | 1 +
lib/gen9_render.h | 6 +-
lib/igt_fb.c | 20 +++--
lib/igt_fb.h | 3 +
lib/intel_aux_pgtable.c | 39 +++++++---
lib/intel_batchbuffer.c | 5 ++
lib/intel_batchbuffer.h | 6 ++
lib/rendercopy.h | 4 +
lib/rendercopy_gen9.c | 167 ++++++++++++++++++++++++++++------------
tests/kms_ccs.c | 93 ++++++++++++++++++----
10 files changed, 263 insertions(+), 81 deletions(-)
--
2.25.1
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^ permalink raw reply [flat|nested] 11+ messages in thread* [igt-dev] [PATCH i-g-t v10 1/4] tests/kms_ccs: Add debug information on format modifier 2020-11-20 9:36 [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test Mika Kahola @ 2020-11-20 9:36 ` Mika Kahola 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 2/4] lib/rendercopy: Enable fast clear Mika Kahola ` (4 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Mika Kahola @ 2020-11-20 9:36 UTC (permalink / raw) To: igt-dev We could benefit on information on what format modifier is in use when running the test. This in mind, let's add informative string along with the list of ccs modifiers. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> --- tests/kms_ccs.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index b60e4908..53abecce 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -81,12 +81,15 @@ static const uint32_t formats[] = { DRM_FORMAT_P016, }; -static const uint64_t ccs_modifiers[] = { - LOCAL_I915_FORMAT_MOD_Y_TILED_CCS, - LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS, - LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, - LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, - LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, +static const struct { + uint64_t modifier; + const char *str; +} ccs_modifiers[5] = { + {LOCAL_I915_FORMAT_MOD_Y_TILED_CCS, "LOCAL_I915_FORMAT_MOD_Y_TILED_CCS"}, + {LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS, "LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS"}, + {LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, "LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS"}, + {LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, "LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC"}, + {LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, "LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS"}, }; static bool check_ccs_planes; @@ -422,7 +425,8 @@ static int __test_output(data_t *data) for (i = 0; i < ARRAY_SIZE(ccs_modifiers); i++) { int j; - data->ccs_modifier = ccs_modifiers[i]; + data->ccs_modifier = ccs_modifiers[i].modifier; + igt_debug("Modifier in use: %s\n", ccs_modifiers[i].str); for (j = 0; j < ARRAY_SIZE(formats); j++) { data->format = formats[j]; valid_tests += test_ccs(data); -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v10 2/4] lib/rendercopy: Enable fast clear 2020-11-20 9:36 [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 1/4] tests/kms_ccs: Add debug information on format modifier Mika Kahola @ 2020-11-20 9:36 ` Mika Kahola 2020-11-20 11:43 ` Imre Deak 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 3/4] lib/intel_aux_pgtable: Initialize aux pagetable for " Mika Kahola ` (3 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Mika Kahola @ 2020-11-20 9:36 UTC (permalink / raw) To: igt-dev Enable fast clear rendering on rendercopy function. v2: Modify _gen9_render_copyfunc to support fast clear (Matt) Enable fast clear bit on 3D sequence (Matt) Add helper function to figure out clear color modifier (Matt) v3: Remove unrelated line additions/removes v4: Fast clear with color (Imre) v5: Write raw 32-bit color values to register (Imre) Require 32-bit color format v6: Rebase to use batchbuffer without libdrm dependency v7: Enable clear color (Nanley) v8: Various cleanups (Imre) Modificate buffer creation (Imre) v9: Renaming of render_copyfunc() to render_op() (Imre) Remove igt_render_clearfunc variable (Imre) v10: Dst buffer width division by 64 pixels and height by 16 lines (Imre) Reorder ss10 bit fields (Imre) Relocate buffer with clear color value enabled (Imre) Set fast clear enable bit in correct dword (Imre) Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- lib/gen8_render.h | 1 + lib/gen9_render.h | 6 +- lib/igt_fb.c | 20 +++-- lib/igt_fb.h | 3 + lib/intel_batchbuffer.c | 5 ++ lib/intel_batchbuffer.h | 6 ++ lib/rendercopy.h | 4 + lib/rendercopy_gen9.c | 167 ++++++++++++++++++++++++++++------------ 8 files changed, 156 insertions(+), 56 deletions(-) diff --git a/lib/gen8_render.h b/lib/gen8_render.h index 31dc01bc..1b0f527e 100644 --- a/lib/gen8_render.h +++ b/lib/gen8_render.h @@ -26,6 +26,7 @@ # define GEN8_VS_FLOATING_POINT_MODE_ALTERNATE (1 << 16) +#define GEN8_3DSTATE_FAST_CLEAR_ENABLE (1 << 8) #define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \ GEN4_3D(3, 0, 0x21) #define GEN8_3DSTATE_PS_BLEND GEN4_3D(3, 0, 0x4d) diff --git a/lib/gen9_render.h b/lib/gen9_render.h index 6274e902..0bd797f9 100644 --- a/lib/gen9_render.h +++ b/lib/gen9_render.h @@ -127,7 +127,11 @@ struct gen9_surface_state { } ss9; struct { - uint32_t aux_base_addr; + uint32_t quilt_width:5; + uint32_t quilt_height:5; + uint32_t clearvalue_addr_enable:1; + uint32_t procedual_texture:1; + uint32_t aux_base_addr:20; } ss10; struct { diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 43f8c475..422a9e06 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -2141,9 +2141,10 @@ static int yuv_semiplanar_bpp(uint32_t drm_format) } } -static struct intel_buf *create_buf(struct fb_blit_upload *blit, - const struct igt_fb *fb, - const char *name) +struct intel_buf * +igt_fb_create_intel_buf(int fd, struct buf_ops *bops, + const struct igt_fb *fb, + const char *name) { struct intel_buf *buf; uint32_t bo_name, handle, compression; @@ -2169,10 +2170,10 @@ static struct intel_buf *create_buf(struct fb_blit_upload *blit, compression = I915_COMPRESSION_NONE; } - bo_name = gem_flink(blit->fd, fb->gem_handle); - handle = gem_open(blit->fd, bo_name); + bo_name = gem_flink(fd, fb->gem_handle); + handle = gem_open(fd, bo_name); - buf = intel_buf_create_using_handle(blit->bops, handle, + buf = intel_buf_create_using_handle(bops, handle, fb->width, fb->height, fb->plane_bpp[0], 0, igt_fb_mod_to_tiling(fb->modifier), @@ -2213,6 +2214,13 @@ static struct intel_buf *create_buf(struct fb_blit_upload *blit, return buf; } +static struct intel_buf *create_buf(struct fb_blit_upload *blit, + const struct igt_fb *fb, + const char *name) +{ + return igt_fb_create_intel_buf(blit->fd, blit->bops, fb, name); +} + static void fini_buf(struct intel_buf *buf) { intel_buf_destroy(buf); diff --git a/lib/igt_fb.h b/lib/igt_fb.h index b36db965..bc5b8fa0 100644 --- a/lib/igt_fb.h +++ b/lib/igt_fb.h @@ -39,6 +39,7 @@ #include "igt_color_encoding.h" #include "igt_debugfs.h" +#include "intel_bufops.h" /* * Internal format to denote a buffer compatible with pixman's @@ -129,6 +130,8 @@ igt_create_fb_with_bo_size(int fd, int width, int height, enum igt_color_range color_range, struct igt_fb *fb, uint64_t bo_size, unsigned bo_stride); +struct intel_buf *igt_fb_create_intel_buf(int fd, struct buf_ops *bops, + const struct igt_fb *fb, const char *name); unsigned int igt_create_fb(int fd, int width, int height, uint32_t format, uint64_t modifier, struct igt_fb *fb); unsigned int igt_create_color_fb(int fd, int width, int height, diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 7b4cfb0d..faec8531 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -1096,6 +1096,11 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid) return copy; } +igt_render_clearfunc_t igt_get_render_clearfunc(int devid) +{ + return IS_GEN12(devid) ? gen12_render_clearfunc : NULL; +} + /** * igt_get_media_fillfunc: * @devid: pci device id diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index ab1b0c28..250566da 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -374,6 +374,12 @@ typedef void (*igt_vebox_copyfunc_t)(struct intel_bb *ibb, igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid); +typedef void (*igt_render_clearfunc_t)(struct intel_bb *ibb, + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, + unsigned int width, unsigned int height, + const float cc_color[4]); +igt_render_clearfunc_t igt_get_render_clearfunc(int devid); + /** * igt_fillfunc_t: * @i915: drm fd diff --git a/lib/rendercopy.h b/lib/rendercopy.h index 7d5f0802..d2d9c586 100644 --- a/lib/rendercopy.h +++ b/lib/rendercopy.h @@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct intel_bb *ibb, intel_bb_out(ibb, u.ui); } +void gen12_render_clearfunc(struct intel_bb *ibb, + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, + unsigned int width, unsigned int height, + const float clear_color[4]); void gen12_render_copyfunc(struct intel_bb *ibb, struct intel_buf *src, uint32_t src_x, uint32_t src_y, uint32_t width, uint32_t height, diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index ef6855c9..95563066 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -185,23 +185,25 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, read_domain, write_domain, - buf->ccs[0].offset, + (buf->cc.offset ? (1 << 10) : 0) | buf->ccs[0].offset, intel_bb_offset(ibb) + 4 * 10, buf->addr.offset); - ss->ss10.aux_base_addr = (address + buf->ccs[0].offset); + ss->ss10.aux_base_addr = (address + buf->ccs[0].offset) >> 12; ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >> 32; - } - if (buf->cc.offset) { - igt_assert(buf->compression == I915_COMPRESSION_RENDER); + if (buf->cc.offset) { + igt_assert(buf->compression == I915_COMPRESSION_RENDER); - address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, - read_domain, write_domain, - buf->cc.offset, - intel_bb_offset(ibb) + 4 * 12, - buf->addr.offset); - ss->ss12.clear_address = address + buf->cc.offset; - ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32; + ss->ss10.clearvalue_addr_enable = 1; + + address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, + read_domain, write_domain, + buf->cc.offset, + intel_bb_offset(ibb) + 4 * 12, + buf->addr.offset); + ss->ss12.clear_address = address + buf->cc.offset; + ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32; + } } return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*ss)); @@ -218,7 +220,9 @@ gen8_bind_surfaces(struct intel_bb *ibb, binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, 32); binding_table[0] = gen8_bind_buf(ibb, dst, 1); - binding_table[1] = gen8_bind_buf(ibb, src, 0); + + if (src != NULL) + binding_table[1] = gen8_bind_buf(ibb, src, 0); return binding_table_offset; } @@ -273,17 +277,37 @@ gen7_fill_vertex_buffer_data(struct intel_bb *ibb, intel_bb_ptr_align(ibb, 8); offset = intel_bb_offset(ibb); - emit_vertex_2s(ibb, dst_x + width, dst_y + height); - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); + if (src != NULL) { + emit_vertex_2s(ibb, dst_x + width, dst_y + height); + + emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); - emit_vertex_2s(ibb, dst_x, dst_y + height); - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); + emit_vertex_2s(ibb, dst_x, dst_y + height); - emit_vertex_2s(ibb, dst_x, dst_y); - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); - emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); + + emit_vertex_2s(ibb, dst_x, dst_y); + + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); + emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); + } else { + emit_vertex_2s(ibb, (dst_x + width)/64, DIV_ROUND_UP(dst_y + height, 16)); + + emit_vertex_normalized(ibb, 0, 0); + emit_vertex_normalized(ibb, 0, 0); + + emit_vertex_2s(ibb, dst_x/64, DIV_ROUND_UP(dst_y + height, 16)); + + emit_vertex_normalized(ibb, 0, 0); + emit_vertex_normalized(ibb, 0, 0); + + emit_vertex_2s(ibb, dst_x/64, dst_y/16); + + emit_vertex_normalized(ibb, 0, 0); + emit_vertex_normalized(ibb, 0, 0); + } return offset; } @@ -729,7 +753,7 @@ gen8_emit_sf(struct intel_bb *ibb) } static void -gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { +gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) { const int max_threads = 63; intel_bb_out(ibb, GEN6_3DSTATE_WM | (2 - 2)); @@ -753,12 +777,19 @@ gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { intel_bb_out(ibb, GEN7_3DSTATE_PS | (12-2)); intel_bb_out(ibb, kernel); intel_bb_out(ibb, 0); /* kernel hi */ - intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT | - 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); + + if (fast_clear) + intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); + else + intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT | + 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); + intel_bb_out(ibb, 0); /* scratch space stuff */ intel_bb_out(ibb, 0); /* scratch hi */ + intel_bb_out(ibb, (max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT | - GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); + GEN6_3DSTATE_WM_16_DISPATCH_ENABLE | + (fast_clear ? GEN8_3DSTATE_FAST_CLEAR_ENABLE : 0)); intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); intel_bb_out(ibb, 0); // kernel 1 intel_bb_out(ibb, 0); /* kernel 1 hi */ @@ -876,27 +907,32 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset) #define BATCH_STATE_SPLIT 2048 static -void _gen9_render_copyfunc(struct intel_bb *ibb, - struct intel_buf *src, - unsigned int src_x, unsigned int src_y, - unsigned int width, unsigned int height, - struct intel_buf *dst, - unsigned int dst_x, unsigned int dst_y, - struct intel_buf *aux_pgtable_buf, - const uint32_t ps_kernel[][4], - uint32_t ps_kernel_size) +void _gen9_render_op(struct intel_bb *ibb, + struct intel_buf *src, + unsigned int src_x, unsigned int src_y, + unsigned int width, unsigned int height, + struct intel_buf *dst, + unsigned int dst_x, unsigned int dst_y, + struct intel_buf *aux_pgtable_buf, + const float clear_color[4], + const uint32_t ps_kernel[][4], + uint32_t ps_kernel_size) { uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table; uint32_t scissor_state; uint32_t vertex_buffer; uint32_t aux_pgtable_state; + bool fast_clear = !src; - igt_assert(src->bpp == dst->bpp); + if (!fast_clear) + igt_assert(src->bpp == dst->bpp); intel_bb_flush_render(ibb); intel_bb_add_intel_buf(ibb, dst, true); - intel_bb_add_intel_buf(ibb, src, false); + + if (!fast_clear) + intel_bb_add_intel_buf(ibb, src, false); intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); @@ -924,6 +960,18 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, gen12_emit_aux_pgtable_state(ibb, aux_pgtable_state, true); + if (fast_clear) { + for (int i = 0; i < 4; i++) { + intel_bb_out(ibb, MI_STORE_DWORD_IMM); + intel_bb_emit_reloc(ibb, dst->handle, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst->cc.offset + i*sizeof(float), + dst->addr.offset); + intel_bb_out(ibb, *(uint32_t*)&clear_color[i]); + } + } + + gen8_emit_sip(ibb); gen7_emit_push_constants(ibb); @@ -953,7 +1001,7 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, gen8_emit_sf(ibb); - gen8_emit_ps(ibb, ps_kernel_off); + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS); intel_bb_out(ibb, ps_binding_table); @@ -991,9 +1039,9 @@ void gen9_render_copyfunc(struct intel_bb *ibb, unsigned int dst_x, unsigned int dst_y) { - _gen9_render_copyfunc(ibb, src, src_x, src_y, - width, height, dst, dst_x, dst_y, NULL, - ps_kernel_gen9, sizeof(ps_kernel_gen9)); + _gen9_render_op(ibb, src, src_x, src_y, + width, height, dst, dst_x, dst_y, NULL, NULL, + ps_kernel_gen9, sizeof(ps_kernel_gen9)); } void gen11_render_copyfunc(struct intel_bb *ibb, @@ -1003,9 +1051,9 @@ void gen11_render_copyfunc(struct intel_bb *ibb, struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y) { - _gen9_render_copyfunc(ibb, src, src_x, src_y, - width, height, dst, dst_x, dst_y, NULL, - ps_kernel_gen11, sizeof(ps_kernel_gen11)); + _gen9_render_op(ibb, src, src_x, src_y, + width, height, dst, dst_x, dst_y, NULL, NULL, + ps_kernel_gen11, sizeof(ps_kernel_gen11)); } void gen12_render_copyfunc(struct intel_bb *ibb, @@ -1019,11 +1067,32 @@ void gen12_render_copyfunc(struct intel_bb *ibb, gen12_aux_pgtable_init(&pgtable_info, ibb, src, dst); - _gen9_render_copyfunc(ibb, src, src_x, src_y, - width, height, dst, dst_x, dst_y, - pgtable_info.pgtable_buf, - gen12_render_copy, - sizeof(gen12_render_copy)); + _gen9_render_op(ibb, src, src_x, src_y, + width, height, dst, dst_x, dst_y, + pgtable_info.pgtable_buf, + NULL, + gen12_render_copy, + sizeof(gen12_render_copy)); + + gen12_aux_pgtable_cleanup(ibb, &pgtable_info); +} + +void gen12_render_clearfunc(struct intel_bb *ibb, + struct intel_buf *dst, + unsigned int dst_x, unsigned int dst_y, + unsigned int width, unsigned int height, + const float clear_color[4]) +{ + struct aux_pgtable_info pgtable_info = { }; + + gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst); + + _gen9_render_op(ibb, NULL, 0, 0, + width, height, dst, dst_x, dst_y, + pgtable_info.pgtable_buf, + clear_color, + gen12_render_copy, + sizeof(gen12_render_copy)); gen12_aux_pgtable_cleanup(ibb, &pgtable_info); } -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v10 2/4] lib/rendercopy: Enable fast clear 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 2/4] lib/rendercopy: Enable fast clear Mika Kahola @ 2020-11-20 11:43 ` Imre Deak 0 siblings, 0 replies; 11+ messages in thread From: Imre Deak @ 2020-11-20 11:43 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev On Fri, Nov 20, 2020 at 11:36:44AM +0200, Mika Kahola wrote: > Enable fast clear rendering on rendercopy function. > > v2: Modify _gen9_render_copyfunc to support fast clear (Matt) > Enable fast clear bit on 3D sequence (Matt) > Add helper function to figure out clear color modifier (Matt) > v3: Remove unrelated line additions/removes > v4: Fast clear with color (Imre) > v5: Write raw 32-bit color values to register (Imre) > Require 32-bit color format > v6: Rebase to use batchbuffer without libdrm dependency > v7: Enable clear color (Nanley) > v8: Various cleanups (Imre) > Modificate buffer creation (Imre) > v9: Renaming of render_copyfunc() to render_op() (Imre) > Remove igt_render_clearfunc variable (Imre) > v10: Dst buffer width division by 64 pixels and height by 16 lines (Imre) > Reorder ss10 bit fields (Imre) > Relocate buffer with clear color value enabled (Imre) > Set fast clear enable bit in correct dword (Imre) > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > lib/gen8_render.h | 1 + > lib/gen9_render.h | 6 +- > lib/igt_fb.c | 20 +++-- > lib/igt_fb.h | 3 + > lib/intel_batchbuffer.c | 5 ++ > lib/intel_batchbuffer.h | 6 ++ > lib/rendercopy.h | 4 + > lib/rendercopy_gen9.c | 167 ++++++++++++++++++++++++++++------------ > 8 files changed, 156 insertions(+), 56 deletions(-) > > diff --git a/lib/gen8_render.h b/lib/gen8_render.h > index 31dc01bc..1b0f527e 100644 > --- a/lib/gen8_render.h > +++ b/lib/gen8_render.h > @@ -26,6 +26,7 @@ > > # define GEN8_VS_FLOATING_POINT_MODE_ALTERNATE (1 << 16) > > +#define GEN8_3DSTATE_FAST_CLEAR_ENABLE (1 << 8) > #define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \ > GEN4_3D(3, 0, 0x21) > #define GEN8_3DSTATE_PS_BLEND GEN4_3D(3, 0, 0x4d) > diff --git a/lib/gen9_render.h b/lib/gen9_render.h > index 6274e902..0bd797f9 100644 > --- a/lib/gen9_render.h > +++ b/lib/gen9_render.h > @@ -127,7 +127,11 @@ struct gen9_surface_state { > } ss9; > > struct { > - uint32_t aux_base_addr; > + uint32_t quilt_width:5; > + uint32_t quilt_height:5; > + uint32_t clearvalue_addr_enable:1; > + uint32_t procedual_texture:1; PT would need a "Only on TGL+" comment > + uint32_t aux_base_addr:20; > } ss10; > > struct { > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > index 43f8c475..422a9e06 100644 > --- a/lib/igt_fb.c > +++ b/lib/igt_fb.c > @@ -2141,9 +2141,10 @@ static int yuv_semiplanar_bpp(uint32_t drm_format) > } > } > > -static struct intel_buf *create_buf(struct fb_blit_upload *blit, > - const struct igt_fb *fb, > - const char *name) > +struct intel_buf * > +igt_fb_create_intel_buf(int fd, struct buf_ops *bops, > + const struct igt_fb *fb, > + const char *name) > { > struct intel_buf *buf; > uint32_t bo_name, handle, compression; > @@ -2169,10 +2170,10 @@ static struct intel_buf *create_buf(struct fb_blit_upload *blit, > compression = I915_COMPRESSION_NONE; > } > > - bo_name = gem_flink(blit->fd, fb->gem_handle); > - handle = gem_open(blit->fd, bo_name); > + bo_name = gem_flink(fd, fb->gem_handle); > + handle = gem_open(fd, bo_name); > > - buf = intel_buf_create_using_handle(blit->bops, handle, > + buf = intel_buf_create_using_handle(bops, handle, > fb->width, fb->height, > fb->plane_bpp[0], 0, > igt_fb_mod_to_tiling(fb->modifier), > @@ -2213,6 +2214,13 @@ static struct intel_buf *create_buf(struct fb_blit_upload *blit, > return buf; > } > > +static struct intel_buf *create_buf(struct fb_blit_upload *blit, > + const struct igt_fb *fb, > + const char *name) > +{ > + return igt_fb_create_intel_buf(blit->fd, blit->bops, fb, name); > +} > + > static void fini_buf(struct intel_buf *buf) > { > intel_buf_destroy(buf); > diff --git a/lib/igt_fb.h b/lib/igt_fb.h > index b36db965..bc5b8fa0 100644 > --- a/lib/igt_fb.h > +++ b/lib/igt_fb.h > @@ -39,6 +39,7 @@ > > #include "igt_color_encoding.h" > #include "igt_debugfs.h" > +#include "intel_bufops.h" struct intel_buf; is enough here to avoid adding a header dependency > > /* > * Internal format to denote a buffer compatible with pixman's > @@ -129,6 +130,8 @@ igt_create_fb_with_bo_size(int fd, int width, int height, > enum igt_color_range color_range, > struct igt_fb *fb, uint64_t bo_size, > unsigned bo_stride); > +struct intel_buf *igt_fb_create_intel_buf(int fd, struct buf_ops *bops, > + const struct igt_fb *fb, const char *name); > unsigned int igt_create_fb(int fd, int width, int height, uint32_t format, > uint64_t modifier, struct igt_fb *fb); > unsigned int igt_create_color_fb(int fd, int width, int height, > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c > index 7b4cfb0d..faec8531 100644 > --- a/lib/intel_batchbuffer.c > +++ b/lib/intel_batchbuffer.c > @@ -1096,6 +1096,11 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid) > return copy; > } > > +igt_render_clearfunc_t igt_get_render_clearfunc(int devid) > +{ > + return IS_GEN12(devid) ? gen12_render_clearfunc : NULL; > +} > + > /** > * igt_get_media_fillfunc: > * @devid: pci device id > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > index ab1b0c28..250566da 100644 > --- a/lib/intel_batchbuffer.h > +++ b/lib/intel_batchbuffer.h > @@ -374,6 +374,12 @@ typedef void (*igt_vebox_copyfunc_t)(struct intel_bb *ibb, > > igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid); > > +typedef void (*igt_render_clearfunc_t)(struct intel_bb *ibb, > + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, > + unsigned int width, unsigned int height, > + const float cc_color[4]); > +igt_render_clearfunc_t igt_get_render_clearfunc(int devid); > + > /** > * igt_fillfunc_t: > * @i915: drm fd > diff --git a/lib/rendercopy.h b/lib/rendercopy.h > index 7d5f0802..d2d9c586 100644 > --- a/lib/rendercopy.h > +++ b/lib/rendercopy.h > @@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct intel_bb *ibb, > intel_bb_out(ibb, u.ui); > } > > +void gen12_render_clearfunc(struct intel_bb *ibb, > + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, > + unsigned int width, unsigned int height, > + const float clear_color[4]); > void gen12_render_copyfunc(struct intel_bb *ibb, > struct intel_buf *src, uint32_t src_x, uint32_t src_y, > uint32_t width, uint32_t height, > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > index ef6855c9..95563066 100644 > --- a/lib/rendercopy_gen9.c > +++ b/lib/rendercopy_gen9.c > @@ -185,23 +185,25 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { > > address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, > read_domain, write_domain, > - buf->ccs[0].offset, > + (buf->cc.offset ? (1 << 10) : 0) | buf->ccs[0].offset, > intel_bb_offset(ibb) + 4 * 10, > buf->addr.offset); > - ss->ss10.aux_base_addr = (address + buf->ccs[0].offset); > + ss->ss10.aux_base_addr = (address + buf->ccs[0].offset) >> 12; > ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >> 32; > - } > > - if (buf->cc.offset) { > - igt_assert(buf->compression == I915_COMPRESSION_RENDER); > + if (buf->cc.offset) { > + igt_assert(buf->compression == I915_COMPRESSION_RENDER); > > - address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, > - read_domain, write_domain, > - buf->cc.offset, > - intel_bb_offset(ibb) + 4 * 12, > - buf->addr.offset); > - ss->ss12.clear_address = address + buf->cc.offset; > - ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32; > + ss->ss10.clearvalue_addr_enable = 1; > + > + address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, > + read_domain, write_domain, > + buf->cc.offset, > + intel_bb_offset(ibb) + 4 * 12, > + buf->addr.offset); > + ss->ss12.clear_address = address + buf->cc.offset; > + ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32; > + } > } > > return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*ss)); > @@ -218,7 +220,9 @@ gen8_bind_surfaces(struct intel_bb *ibb, > binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, 32); > > binding_table[0] = gen8_bind_buf(ibb, dst, 1); > - binding_table[1] = gen8_bind_buf(ibb, src, 0); > + > + if (src != NULL) > + binding_table[1] = gen8_bind_buf(ibb, src, 0); > > return binding_table_offset; > } > @@ -273,17 +277,37 @@ gen7_fill_vertex_buffer_data(struct intel_bb *ibb, > intel_bb_ptr_align(ibb, 8); > offset = intel_bb_offset(ibb); > > - emit_vertex_2s(ibb, dst_x + width, dst_y + height); > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > + if (src != NULL) { > + emit_vertex_2s(ibb, dst_x + width, dst_y + height); > + > + emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > - emit_vertex_2s(ibb, dst_x, dst_y + height); > - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > + emit_vertex_2s(ibb, dst_x, dst_y + height); > > - emit_vertex_2s(ibb, dst_x, dst_y); > - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > - emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); > + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > + > + emit_vertex_2s(ibb, dst_x, dst_y); > + > + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > + emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); > + } else { > + emit_vertex_2s(ibb, (dst_x + width)/64, DIV_ROUND_UP(dst_y + height, 16)); DIV_ROUND_UP(dst_x + width, 64), DIV_ROUND_UP(dst_y + height, 16) as start coords need to be rounded down and end coords up > + > + emit_vertex_normalized(ibb, 0, 0); > + emit_vertex_normalized(ibb, 0, 0); > + > + emit_vertex_2s(ibb, dst_x/64, DIV_ROUND_UP(dst_y + height, 16)); > + > + emit_vertex_normalized(ibb, 0, 0); > + emit_vertex_normalized(ibb, 0, 0); > + > + emit_vertex_2s(ibb, dst_x/64, dst_y/16); > + > + emit_vertex_normalized(ibb, 0, 0); > + emit_vertex_normalized(ibb, 0, 0); > + } > > return offset; > } > @@ -729,7 +753,7 @@ gen8_emit_sf(struct intel_bb *ibb) > } > > static void > -gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { > +gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) { > const int max_threads = 63; > > intel_bb_out(ibb, GEN6_3DSTATE_WM | (2 - 2)); > @@ -753,12 +777,19 @@ gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { > intel_bb_out(ibb, GEN7_3DSTATE_PS | (12-2)); > intel_bb_out(ibb, kernel); > intel_bb_out(ibb, 0); /* kernel hi */ > - intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT | > - 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); > + > + if (fast_clear) > + intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); > + else > + intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT | > + 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); > + > intel_bb_out(ibb, 0); /* scratch space stuff */ > intel_bb_out(ibb, 0); /* scratch hi */ > + > intel_bb_out(ibb, (max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT | > - GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); > + GEN6_3DSTATE_WM_16_DISPATCH_ENABLE | > + (fast_clear ? GEN8_3DSTATE_FAST_CLEAR_ENABLE : 0)); > intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); > intel_bb_out(ibb, 0); // kernel 1 > intel_bb_out(ibb, 0); /* kernel 1 hi */ > @@ -876,27 +907,32 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset) > #define BATCH_STATE_SPLIT 2048 > > static > -void _gen9_render_copyfunc(struct intel_bb *ibb, > - struct intel_buf *src, > - unsigned int src_x, unsigned int src_y, > - unsigned int width, unsigned int height, > - struct intel_buf *dst, > - unsigned int dst_x, unsigned int dst_y, > - struct intel_buf *aux_pgtable_buf, > - const uint32_t ps_kernel[][4], > - uint32_t ps_kernel_size) > +void _gen9_render_op(struct intel_bb *ibb, > + struct intel_buf *src, > + unsigned int src_x, unsigned int src_y, > + unsigned int width, unsigned int height, > + struct intel_buf *dst, > + unsigned int dst_x, unsigned int dst_y, > + struct intel_buf *aux_pgtable_buf, > + const float clear_color[4], > + const uint32_t ps_kernel[][4], > + uint32_t ps_kernel_size) > { > uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table; > uint32_t scissor_state; > uint32_t vertex_buffer; > uint32_t aux_pgtable_state; > + bool fast_clear = !src; > > - igt_assert(src->bpp == dst->bpp); > + if (!fast_clear) > + igt_assert(src->bpp == dst->bpp); > > intel_bb_flush_render(ibb); > > intel_bb_add_intel_buf(ibb, dst, true); > - intel_bb_add_intel_buf(ibb, src, false); > + > + if (!fast_clear) > + intel_bb_add_intel_buf(ibb, src, false); > > intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); > > @@ -924,6 +960,18 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, > > gen12_emit_aux_pgtable_state(ibb, aux_pgtable_state, true); > > + if (fast_clear) { > + for (int i = 0; i < 4; i++) { > + intel_bb_out(ibb, MI_STORE_DWORD_IMM); > + intel_bb_emit_reloc(ibb, dst->handle, > + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, > + dst->cc.offset + i*sizeof(float), > + dst->addr.offset); > + intel_bb_out(ibb, *(uint32_t*)&clear_color[i]); > + } > + } some w/s and indentation to be fixed above Looks ok with the above things fixed: Reviewed-by: Imre Deak <imre.deak@intel.com> > + > + > gen8_emit_sip(ibb); > > gen7_emit_push_constants(ibb); > @@ -953,7 +1001,7 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, > > gen8_emit_sf(ibb); > > - gen8_emit_ps(ibb, ps_kernel_off); > + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); > > intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS); > intel_bb_out(ibb, ps_binding_table); > @@ -991,9 +1039,9 @@ void gen9_render_copyfunc(struct intel_bb *ibb, > unsigned int dst_x, unsigned int dst_y) > > { > - _gen9_render_copyfunc(ibb, src, src_x, src_y, > - width, height, dst, dst_x, dst_y, NULL, > - ps_kernel_gen9, sizeof(ps_kernel_gen9)); > + _gen9_render_op(ibb, src, src_x, src_y, > + width, height, dst, dst_x, dst_y, NULL, NULL, > + ps_kernel_gen9, sizeof(ps_kernel_gen9)); > } > > void gen11_render_copyfunc(struct intel_bb *ibb, > @@ -1003,9 +1051,9 @@ void gen11_render_copyfunc(struct intel_bb *ibb, > struct intel_buf *dst, > unsigned int dst_x, unsigned int dst_y) > { > - _gen9_render_copyfunc(ibb, src, src_x, src_y, > - width, height, dst, dst_x, dst_y, NULL, > - ps_kernel_gen11, sizeof(ps_kernel_gen11)); > + _gen9_render_op(ibb, src, src_x, src_y, > + width, height, dst, dst_x, dst_y, NULL, NULL, > + ps_kernel_gen11, sizeof(ps_kernel_gen11)); > } > > void gen12_render_copyfunc(struct intel_bb *ibb, > @@ -1019,11 +1067,32 @@ void gen12_render_copyfunc(struct intel_bb *ibb, > > gen12_aux_pgtable_init(&pgtable_info, ibb, src, dst); > > - _gen9_render_copyfunc(ibb, src, src_x, src_y, > - width, height, dst, dst_x, dst_y, > - pgtable_info.pgtable_buf, > - gen12_render_copy, > - sizeof(gen12_render_copy)); > + _gen9_render_op(ibb, src, src_x, src_y, > + width, height, dst, dst_x, dst_y, > + pgtable_info.pgtable_buf, > + NULL, > + gen12_render_copy, > + sizeof(gen12_render_copy)); > + > + gen12_aux_pgtable_cleanup(ibb, &pgtable_info); > +} > + > +void gen12_render_clearfunc(struct intel_bb *ibb, > + struct intel_buf *dst, > + unsigned int dst_x, unsigned int dst_y, > + unsigned int width, unsigned int height, > + const float clear_color[4]) > +{ > + struct aux_pgtable_info pgtable_info = { }; > + > + gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst); > + > + _gen9_render_op(ibb, NULL, 0, 0, > + width, height, dst, dst_x, dst_y, > + pgtable_info.pgtable_buf, > + clear_color, > + gen12_render_copy, > + sizeof(gen12_render_copy)); > > gen12_aux_pgtable_cleanup(ibb, &pgtable_info); > } > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v10 3/4] lib/intel_aux_pgtable: Initialize aux pagetable for fast clear 2020-11-20 9:36 [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 1/4] tests/kms_ccs: Add debug information on format modifier Mika Kahola 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 2/4] lib/rendercopy: Enable fast clear Mika Kahola @ 2020-11-20 9:36 ` Mika Kahola 2020-11-20 11:44 ` Imre Deak 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test Mika Kahola ` (2 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Mika Kahola @ 2020-11-20 9:36 UTC (permalink / raw) To: igt-dev For fast clear we haven't defined source buffer. Therefore, we only need to initialize only destination aux pagetable. v2: Cleaner solution proposed by Imre (Imre) Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- lib/intel_aux_pgtable.c | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index ef6a9fef..c05d4511 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -514,18 +514,35 @@ gen12_aux_pgtable_init(struct aux_pgtable_info *info, struct intel_buf *dst_buf) { struct intel_buf *bufs[2]; + int buf_count = 0; struct intel_buf *reserved_bufs[2]; int reserved_buf_count; + bool has_compressed_buf = false; + bool write_buf[2]; int i; igt_assert_f(ibb->enforce_relocs == false, "We support aux pgtables for non-forced relocs yet!"); - if (!intel_buf_compressed(src_buf) && !intel_buf_compressed(dst_buf)) - return; + if (src_buf) { + bufs[buf_count] = src_buf; + write_buf[buf_count] = false; + buf_count++; + + if (intel_buf_compressed(src_buf)) + has_compressed_buf = true; + } + if (dst_buf) { + bufs[buf_count] = dst_buf; + write_buf[buf_count] = true; + buf_count++; + + if (intel_buf_compressed(dst_buf)) + has_compressed_buf = true; + } - bufs[0] = src_buf; - bufs[1] = dst_buf; + if (!has_compressed_buf) + return; /* * Surface index in pgt table depend on its address so: @@ -541,17 +558,15 @@ gen12_aux_pgtable_init(struct aux_pgtable_info *info, * surfaces. */ - intel_bb_add_intel_buf(ibb, src_buf, false); - if (intel_buf_compressed(src_buf)) - intel_bb_object_set_flag(ibb, src_buf->handle, EXEC_OBJECT_PINNED); - - intel_bb_add_intel_buf(ibb, dst_buf, true); - if (intel_buf_compressed(dst_buf)) - intel_bb_object_set_flag(ibb, dst_buf->handle, EXEC_OBJECT_PINNED); + for (i = 0; i < buf_count; i++) { + intel_bb_add_intel_buf(ibb, bufs[i], write_buf[i]); + if (intel_buf_compressed(bufs[i])) + intel_bb_object_set_flag(ibb, bufs[i]->handle, EXEC_OBJECT_PINNED); + } reserved_buf_count = 0; /* First reserve space for any bufs that are bound already. */ - for (i = 0; i < ARRAY_SIZE(bufs); i++) { + for (i = 0; i < buf_count; i++) { igt_assert(bufs[i]->addr.offset != INTEL_BUF_INVALID_ADDRESS); aux_pgtable_reserve_buf_slot(reserved_bufs, reserved_buf_count++, -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v10 3/4] lib/intel_aux_pgtable: Initialize aux pagetable for fast clear 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 3/4] lib/intel_aux_pgtable: Initialize aux pagetable for " Mika Kahola @ 2020-11-20 11:44 ` Imre Deak 0 siblings, 0 replies; 11+ messages in thread From: Imre Deak @ 2020-11-20 11:44 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev On Fri, Nov 20, 2020 at 11:36:45AM +0200, Mika Kahola wrote: > For fast clear we haven't defined source buffer. Therefore, we only > need to initialize only destination aux pagetable. > > v2: Cleaner solution proposed by Imre (Imre) > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > lib/intel_aux_pgtable.c | 39 +++++++++++++++++++++++++++------------ > 1 file changed, 27 insertions(+), 12 deletions(-) > > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c > index ef6a9fef..c05d4511 100644 > --- a/lib/intel_aux_pgtable.c > +++ b/lib/intel_aux_pgtable.c > @@ -514,18 +514,35 @@ gen12_aux_pgtable_init(struct aux_pgtable_info *info, > struct intel_buf *dst_buf) > { > struct intel_buf *bufs[2]; > + int buf_count = 0; > struct intel_buf *reserved_bufs[2]; > int reserved_buf_count; > + bool has_compressed_buf = false; > + bool write_buf[2]; > int i; > > igt_assert_f(ibb->enforce_relocs == false, > "We support aux pgtables for non-forced relocs yet!"); > > - if (!intel_buf_compressed(src_buf) && !intel_buf_compressed(dst_buf)) > - return; > + if (src_buf) { > + bufs[buf_count] = src_buf; > + write_buf[buf_count] = false; > + buf_count++; > + > + if (intel_buf_compressed(src_buf)) > + has_compressed_buf = true; > + } > + if (dst_buf) { > + bufs[buf_count] = dst_buf; > + write_buf[buf_count] = true; > + buf_count++; > + > + if (intel_buf_compressed(dst_buf)) > + has_compressed_buf = true; > + } > > - bufs[0] = src_buf; > - bufs[1] = dst_buf; > + if (!has_compressed_buf) > + return; > > /* > * Surface index in pgt table depend on its address so: > @@ -541,17 +558,15 @@ gen12_aux_pgtable_init(struct aux_pgtable_info *info, > * surfaces. > */ > > - intel_bb_add_intel_buf(ibb, src_buf, false); > - if (intel_buf_compressed(src_buf)) > - intel_bb_object_set_flag(ibb, src_buf->handle, EXEC_OBJECT_PINNED); > - > - intel_bb_add_intel_buf(ibb, dst_buf, true); > - if (intel_buf_compressed(dst_buf)) > - intel_bb_object_set_flag(ibb, dst_buf->handle, EXEC_OBJECT_PINNED); > + for (i = 0; i < buf_count; i++) { > + intel_bb_add_intel_buf(ibb, bufs[i], write_buf[i]); > + if (intel_buf_compressed(bufs[i])) > + intel_bb_object_set_flag(ibb, bufs[i]->handle, EXEC_OBJECT_PINNED); > + } > > reserved_buf_count = 0; > /* First reserve space for any bufs that are bound already. */ > - for (i = 0; i < ARRAY_SIZE(bufs); i++) { > + for (i = 0; i < buf_count; i++) { > igt_assert(bufs[i]->addr.offset != INTEL_BUF_INVALID_ADDRESS); > aux_pgtable_reserve_buf_slot(reserved_bufs, > reserved_buf_count++, > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test 2020-11-20 9:36 [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test Mika Kahola ` (2 preceding siblings ...) 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 3/4] lib/intel_aux_pgtable: Initialize aux pagetable for " Mika Kahola @ 2020-11-20 9:36 ` Mika Kahola 2020-11-20 11:52 ` Imre Deak 2020-11-20 10:09 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2020-11-20 12:09 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 1 reply; 11+ messages in thread From: Mika Kahola @ 2020-11-20 9:36 UTC (permalink / raw) To: igt-dev The patch proposes a method to test CCS with clear color capability. The test paints a solid color on primary fb and a small sprite fb. These are cleared with fast clear feature. A crc is captured and compared against the reference. v2: Modify _gen9_render_copyfunc to support fast clear (Matt) Enable fast clear bit on 3D sequence (Matt) Add helper function to figure out clear color modifier (Matt) v3: Remove unrelated line additions/removes v4: Fast clear with color (Imre) v5: Write raw 32-bit color values to register (Imre) Require 32-bit color format v6: Rebase to use batchbuffer without libdrm dependency v7: Enable clear color (Nanley) v8: Various cleanups (Imre) v9: Splitting patch for smaller hunks (Imre) v10: Remove switch from CCS CC modifier check (Imre) Color map conversion (Imre) Separate function to check CCS CC plane (Imre) Removed left-over comment (Imre) Replace inte_bb_reset() with intel_bb_sync() and intel_bb_destroy() when cleaning up (Imre) Fix logic to test CCS clear color only with XRGB8888 format (Imre) Move fast clear to it's own function (Imre) Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- tests/kms_ccs.c | 75 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 6 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 53abecce..8c2d7b3d 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -120,6 +120,11 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) } } +static bool is_ccs_cc_modifier(uint64_t modifier) +{ + return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; +} + /* * The CCS planes of compressed framebuffers contain non-zero bytes if the * engine compressed effectively the framebuffer. The actual encoding of these @@ -155,7 +160,36 @@ static void check_ccs_plane(int drm_fd, igt_fb_t *fb, int plane) plane, igt_fb_ccs_to_main_plane(fb, plane)); } -static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) +static void check_ccs_cc_plane(int drm_fd, igt_fb_t *fb, int plane, const float *cc_color) +{ + union cc { + float f; + uint32_t d; + } *cc_p; + void *map; + uint32_t native_color; + + gem_set_domain(drm_fd, fb->gem_handle, I915_GEM_DOMAIN_CPU, 0); + + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, PROT_READ); + cc_p = map + fb->offsets[plane]; + + igt_assert(cc_color[0] == cc_p[0].f && + cc_color[1] == cc_p[1].f && + cc_color[2] == cc_p[2].f && + cc_color[3] == cc_p[3].f); + + native_color = (uint8_t)(cc_color[3] * 0xff) << 24 | + (uint8_t)(cc_color[0] * 0xff) << 16 | + (uint8_t)(cc_color[1] * 0xff) << 8 | + (uint8_t)(cc_color[2] * 0xff); + + igt_assert(native_color == cc_p[4].d); + + munmap(map, fb->size); +}; + +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb, const float *cc_color) { int i; @@ -163,6 +197,8 @@ static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) if (igt_fb_is_ccs_plane(fb, i) && !igt_fb_is_gen12_ccs_cc_plane(fb, i)) check_ccs_plane(drm_fd, fb, i); + else if (igt_fb_is_gen12_ccs_cc_plane(fb, i)) + check_ccs_cc_plane(drm_fd, fb, i, cc_color); } } @@ -176,6 +212,24 @@ static int get_ccs_plane_index(uint32_t format) return index; } +static void fast_clear_fb(int drm_fd, struct igt_fb *fb, const float *cc_color) +{ + igt_render_clearfunc_t fast_clear = igt_get_render_clearfunc(intel_get_drm_devid(drm_fd)); + struct intel_bb *ibb = intel_bb_create(drm_fd, 4096); + struct buf_ops *bops = buf_ops_create(drm_fd); + struct intel_buf *dst = igt_fb_create_intel_buf(drm_fd, bops, fb, "fast clear dst"); + + gem_set_domain(drm_fd, fb->gem_handle, + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); + + fast_clear(ibb, dst, 0, 0, fb->width, fb->height, cc_color); + + intel_bb_sync(ibb); + intel_bb_destroy(ibb); + intel_buf_destroy(dst); + buf_ops_destroy(bops); +} + static void generate_fb(data_t *data, struct igt_fb *fb, int width, int height, enum test_fb_flags fb_flags) @@ -186,6 +240,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb, cairo_t *cr; int index; int ret; + const float cc_color[4] = {colors[0].r, colors[0].g, colors[0].b, 1.0}; /* Use either compressed or Y-tiled to test. However, given the lack of * available bandwidth, we use linear for the primary plane when @@ -246,10 +301,14 @@ static void generate_fb(data_t *data, struct igt_fb *fb, if (!(data->flags & TEST_BAD_PIXEL_FORMAT)) { int c = !!data->plane; - cr = igt_get_cairo_ctx(data->drm_fd, fb); - igt_paint_color(cr, 0, 0, width, height, - colors[c].r, colors[c].g, colors[c].b); - igt_put_cairo_ctx(cr); + if (is_ccs_cc_modifier(modifier)) { + fast_clear_fb(data->drm_fd, fb, cc_color); + } else { + cr = igt_get_cairo_ctx(data->drm_fd, fb); + igt_paint_color(cr, 0, 0, width, height, + colors[c].r, colors[c].g, colors[c].b); + igt_put_cairo_ctx(cr); + } } ret = drmIoctl(data->drm_fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f); @@ -261,7 +320,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb, igt_assert_eq(ret, 0); if (check_ccs_planes) - check_all_ccs_planes(data->drm_fd, fb); + check_all_ccs_planes(data->drm_fd, fb, cc_color); fb->fb_id = f.fb_id; } @@ -349,6 +408,10 @@ static bool try_config(data_t *data, enum test_fb_flags fb_flags, if (data->flags & TEST_BAD_ROTATION_90) igt_plane_set_rotation(primary, IGT_ROTATION_90); + if (is_ccs_cc_modifier(data->ccs_modifier) + && data->format != DRM_FORMAT_XRGB8888) + return false; + ret = igt_display_try_commit2(display, commit); if (data->flags & TEST_BAD_ROTATION_90) { igt_assert_eq(ret, -EINVAL); -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test Mika Kahola @ 2020-11-20 11:52 ` Imre Deak 2020-11-20 11:56 ` Kahola, Mika 0 siblings, 1 reply; 11+ messages in thread From: Imre Deak @ 2020-11-20 11:52 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev On Fri, Nov 20, 2020 at 11:36:46AM +0200, Mika Kahola wrote: > The patch proposes a method to test CCS with clear color > capability. > > The test paints a solid color on primary fb and a small sprite fb. > These are cleared with fast clear feature. A crc is captured and > compared against the reference. > > v2: Modify _gen9_render_copyfunc to support fast clear (Matt) > Enable fast clear bit on 3D sequence (Matt) > Add helper function to figure out clear color modifier (Matt) > v3: Remove unrelated line additions/removes > v4: Fast clear with color (Imre) > v5: Write raw 32-bit color values to register (Imre) > Require 32-bit color format > v6: Rebase to use batchbuffer without libdrm dependency > v7: Enable clear color (Nanley) > v8: Various cleanups (Imre) > v9: Splitting patch for smaller hunks (Imre) > v10: Remove switch from CCS CC modifier check (Imre) > Color map conversion (Imre) > Separate function to check CCS CC plane (Imre) > Removed left-over comment (Imre) > Replace inte_bb_reset() with intel_bb_sync() and > intel_bb_destroy() when cleaning up (Imre) > Fix logic to test CCS clear color only with > XRGB8888 format (Imre) > Move fast clear to it's own function (Imre) > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > tests/kms_ccs.c | 75 +++++++++++++++++++++++++++++++++++++++++++++---- > 1 file changed, 69 insertions(+), 6 deletions(-) > > diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c > index 53abecce..8c2d7b3d 100644 > --- a/tests/kms_ccs.c > +++ b/tests/kms_ccs.c > @@ -120,6 +120,11 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) > } > } > > +static bool is_ccs_cc_modifier(uint64_t modifier) > +{ > + return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; > +} > + > /* > * The CCS planes of compressed framebuffers contain non-zero bytes if the > * engine compressed effectively the framebuffer. The actual encoding of these > @@ -155,7 +160,36 @@ static void check_ccs_plane(int drm_fd, igt_fb_t *fb, int plane) > plane, igt_fb_ccs_to_main_plane(fb, plane)); > } > > -static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) > +static void check_ccs_cc_plane(int drm_fd, igt_fb_t *fb, int plane, const float *cc_color) > +{ > + union cc { > + float f; > + uint32_t d; > + } *cc_p; > + void *map; > + uint32_t native_color; > + > + gem_set_domain(drm_fd, fb->gem_handle, I915_GEM_DOMAIN_CPU, 0); > + > + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, PROT_READ); > + cc_p = map + fb->offsets[plane]; > + > + igt_assert(cc_color[0] == cc_p[0].f && > + cc_color[1] == cc_p[1].f && > + cc_color[2] == cc_p[2].f && > + cc_color[3] == cc_p[3].f); > + > + native_color = (uint8_t)(cc_color[3] * 0xff) << 24 | > + (uint8_t)(cc_color[0] * 0xff) << 16 | > + (uint8_t)(cc_color[1] * 0xff) << 8 | > + (uint8_t)(cc_color[2] * 0xff); > + > + igt_assert(native_color == cc_p[4].d); > + > + munmap(map, fb->size); > +}; > + > +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb, const float *cc_color) > { > int i; > > @@ -163,6 +197,8 @@ static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) > if (igt_fb_is_ccs_plane(fb, i) && > !igt_fb_is_gen12_ccs_cc_plane(fb, i)) > check_ccs_plane(drm_fd, fb, i); > + else if (igt_fb_is_gen12_ccs_cc_plane(fb, i)) > + check_ccs_cc_plane(drm_fd, fb, i, cc_color); > } > } > > @@ -176,6 +212,24 @@ static int get_ccs_plane_index(uint32_t format) > return index; > } > > +static void fast_clear_fb(int drm_fd, struct igt_fb *fb, const float *cc_color) > +{ > + igt_render_clearfunc_t fast_clear = igt_get_render_clearfunc(intel_get_drm_devid(drm_fd)); > + struct intel_bb *ibb = intel_bb_create(drm_fd, 4096); > + struct buf_ops *bops = buf_ops_create(drm_fd); > + struct intel_buf *dst = igt_fb_create_intel_buf(drm_fd, bops, fb, "fast clear dst"); > + > + gem_set_domain(drm_fd, fb->gem_handle, > + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); > + > + fast_clear(ibb, dst, 0, 0, fb->width, fb->height, cc_color); > + > + intel_bb_sync(ibb); > + intel_bb_destroy(ibb); > + intel_buf_destroy(dst); > + buf_ops_destroy(bops); > +} > + > static void generate_fb(data_t *data, struct igt_fb *fb, > int width, int height, > enum test_fb_flags fb_flags) > @@ -186,6 +240,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb, > cairo_t *cr; > int index; > int ret; > + const float cc_color[4] = {colors[0].r, colors[0].g, colors[0].b, 1.0}; this needs to match the reference FB color, which is different in the sprite subtests: colors[!!data->plane] > > /* Use either compressed or Y-tiled to test. However, given the lack of > * available bandwidth, we use linear for the primary plane when > @@ -246,10 +301,14 @@ static void generate_fb(data_t *data, struct igt_fb *fb, > if (!(data->flags & TEST_BAD_PIXEL_FORMAT)) { > int c = !!data->plane; > > - cr = igt_get_cairo_ctx(data->drm_fd, fb); > - igt_paint_color(cr, 0, 0, width, height, > - colors[c].r, colors[c].g, colors[c].b); > - igt_put_cairo_ctx(cr); > + if (is_ccs_cc_modifier(modifier)) { > + fast_clear_fb(data->drm_fd, fb, cc_color); > + } else { > + cr = igt_get_cairo_ctx(data->drm_fd, fb); > + igt_paint_color(cr, 0, 0, width, height, > + colors[c].r, colors[c].g, colors[c].b); > + igt_put_cairo_ctx(cr); > + } > } > > ret = drmIoctl(data->drm_fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f); > @@ -261,7 +320,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb, > igt_assert_eq(ret, 0); > > if (check_ccs_planes) > - check_all_ccs_planes(data->drm_fd, fb); > + check_all_ccs_planes(data->drm_fd, fb, cc_color); > > fb->fb_id = f.fb_id; > } > @@ -349,6 +408,10 @@ static bool try_config(data_t *data, enum test_fb_flags fb_flags, > if (data->flags & TEST_BAD_ROTATION_90) > igt_plane_set_rotation(primary, IGT_ROTATION_90); > > + if (is_ccs_cc_modifier(data->ccs_modifier) > + && data->format != DRM_FORMAT_XRGB8888) > + return false; this should be checked early after igt_plane_has_format_mod() to avoid the overhead up to this point. Also codying style is && at the end of line. With the above fixed, looks ok: Reviewed-by: Imre Deak <imre.deak@intel.com> > + > ret = igt_display_try_commit2(display, commit); > if (data->flags & TEST_BAD_ROTATION_90) { > igt_assert_eq(ret, -EINVAL); > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test 2020-11-20 11:52 ` Imre Deak @ 2020-11-20 11:56 ` Kahola, Mika 0 siblings, 0 replies; 11+ messages in thread From: Kahola, Mika @ 2020-11-20 11:56 UTC (permalink / raw) To: Deak, Imre; +Cc: igt-dev@lists.freedesktop.org > -----Original Message----- > From: Imre Deak <imre.deak@intel.com> > Sent: Friday, November 20, 2020 1:53 PM > To: Kahola, Mika <mika.kahola@intel.com> > Cc: igt-dev@lists.freedesktop.org > Subject: Re: [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test > > On Fri, Nov 20, 2020 at 11:36:46AM +0200, Mika Kahola wrote: > > The patch proposes a method to test CCS with clear color capability. > > > > The test paints a solid color on primary fb and a small sprite fb. > > These are cleared with fast clear feature. A crc is captured and > > compared against the reference. > > > > v2: Modify _gen9_render_copyfunc to support fast clear (Matt) > > Enable fast clear bit on 3D sequence (Matt) > > Add helper function to figure out clear color modifier (Matt) > > v3: Remove unrelated line additions/removes > > v4: Fast clear with color (Imre) > > v5: Write raw 32-bit color values to register (Imre) > > Require 32-bit color format > > v6: Rebase to use batchbuffer without libdrm dependency > > v7: Enable clear color (Nanley) > > v8: Various cleanups (Imre) > > v9: Splitting patch for smaller hunks (Imre) > > v10: Remove switch from CCS CC modifier check (Imre) > > Color map conversion (Imre) > > Separate function to check CCS CC plane (Imre) > > Removed left-over comment (Imre) > > Replace inte_bb_reset() with intel_bb_sync() and > > intel_bb_destroy() when cleaning up (Imre) > > Fix logic to test CCS clear color only with > > XRGB8888 format (Imre) > > Move fast clear to it's own function (Imre) > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > --- > > tests/kms_ccs.c | 75 > > +++++++++++++++++++++++++++++++++++++++++++++---- > > 1 file changed, 69 insertions(+), 6 deletions(-) > > > > diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index > > 53abecce..8c2d7b3d 100644 > > --- a/tests/kms_ccs.c > > +++ b/tests/kms_ccs.c > > @@ -120,6 +120,11 @@ static void addfb_init(struct igt_fb *fb, struct > drm_mode_fb_cmd2 *f) > > } > > } > > > > +static bool is_ccs_cc_modifier(uint64_t modifier) { > > + return modifier == > LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; > > +} > > + > > /* > > * The CCS planes of compressed framebuffers contain non-zero bytes if > the > > * engine compressed effectively the framebuffer. The actual encoding > > of these @@ -155,7 +160,36 @@ static void check_ccs_plane(int drm_fd, > igt_fb_t *fb, int plane) > > plane, igt_fb_ccs_to_main_plane(fb, plane)); } > > > > -static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) > > +static void check_ccs_cc_plane(int drm_fd, igt_fb_t *fb, int plane, > > +const float *cc_color) { > > + union cc { > > + float f; > > + uint32_t d; > > + } *cc_p; > > + void *map; > > + uint32_t native_color; > > + > > + gem_set_domain(drm_fd, fb->gem_handle, > I915_GEM_DOMAIN_CPU, 0); > > + > > + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, > PROT_READ); > > + cc_p = map + fb->offsets[plane]; > > + > > + igt_assert(cc_color[0] == cc_p[0].f && > > + cc_color[1] == cc_p[1].f && > > + cc_color[2] == cc_p[2].f && > > + cc_color[3] == cc_p[3].f); > > + > > + native_color = (uint8_t)(cc_color[3] * 0xff) << 24 | > > + (uint8_t)(cc_color[0] * 0xff) << 16 | > > + (uint8_t)(cc_color[1] * 0xff) << 8 | > > + (uint8_t)(cc_color[2] * 0xff); > > + > > + igt_assert(native_color == cc_p[4].d); > > + > > + munmap(map, fb->size); > > +}; > > + > > +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb, const > > +float *cc_color) > > { > > int i; > > > > @@ -163,6 +197,8 @@ static void check_all_ccs_planes(int drm_fd, > igt_fb_t *fb) > > if (igt_fb_is_ccs_plane(fb, i) && > > !igt_fb_is_gen12_ccs_cc_plane(fb, i)) > > check_ccs_plane(drm_fd, fb, i); > > + else if (igt_fb_is_gen12_ccs_cc_plane(fb, i)) > > + check_ccs_cc_plane(drm_fd, fb, i, cc_color); > > } > > } > > > > @@ -176,6 +212,24 @@ static int get_ccs_plane_index(uint32_t format) > > return index; > > } > > > > +static void fast_clear_fb(int drm_fd, struct igt_fb *fb, const float > > +*cc_color) { > > + igt_render_clearfunc_t fast_clear = > igt_get_render_clearfunc(intel_get_drm_devid(drm_fd)); > > + struct intel_bb *ibb = intel_bb_create(drm_fd, 4096); > > + struct buf_ops *bops = buf_ops_create(drm_fd); > > + struct intel_buf *dst = igt_fb_create_intel_buf(drm_fd, bops, fb, > > +"fast clear dst"); > > + > > + gem_set_domain(drm_fd, fb->gem_handle, > > + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); > > + > > + fast_clear(ibb, dst, 0, 0, fb->width, fb->height, cc_color); > > + > > + intel_bb_sync(ibb); > > + intel_bb_destroy(ibb); > > + intel_buf_destroy(dst); > > + buf_ops_destroy(bops); > > +} > > + > > static void generate_fb(data_t *data, struct igt_fb *fb, > > int width, int height, > > enum test_fb_flags fb_flags) > > @@ -186,6 +240,7 @@ static void generate_fb(data_t *data, struct igt_fb > *fb, > > cairo_t *cr; > > int index; > > int ret; > > + const float cc_color[4] = {colors[0].r, colors[0].g, colors[0].b, > > +1.0}; > > this needs to match the reference FB color, which is different in the sprite > subtests: colors[!!data->plane] > > > > > /* Use either compressed or Y-tiled to test. However, given the lack > of > > * available bandwidth, we use linear for the primary plane when > @@ > > -246,10 +301,14 @@ static void generate_fb(data_t *data, struct igt_fb *fb, > > if (!(data->flags & TEST_BAD_PIXEL_FORMAT)) { > > int c = !!data->plane; > > > > - cr = igt_get_cairo_ctx(data->drm_fd, fb); > > - igt_paint_color(cr, 0, 0, width, height, > > - colors[c].r, colors[c].g, colors[c].b); > > - igt_put_cairo_ctx(cr); > > + if (is_ccs_cc_modifier(modifier)) { > > + fast_clear_fb(data->drm_fd, fb, cc_color); > > + } else { > > + cr = igt_get_cairo_ctx(data->drm_fd, fb); > > + igt_paint_color(cr, 0, 0, width, height, > > + colors[c].r, colors[c].g, colors[c].b); > > + igt_put_cairo_ctx(cr); > > + } > > } > > > > ret = drmIoctl(data->drm_fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, > &f); @@ > > -261,7 +320,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb, > > igt_assert_eq(ret, 0); > > > > if (check_ccs_planes) > > - check_all_ccs_planes(data->drm_fd, fb); > > + check_all_ccs_planes(data->drm_fd, fb, cc_color); > > > > fb->fb_id = f.fb_id; > > } > > @@ -349,6 +408,10 @@ static bool try_config(data_t *data, enum > test_fb_flags fb_flags, > > if (data->flags & TEST_BAD_ROTATION_90) > > igt_plane_set_rotation(primary, IGT_ROTATION_90); > > > > + if (is_ccs_cc_modifier(data->ccs_modifier) > > + && data->format != DRM_FORMAT_XRGB8888) > > + return false; > > this should be checked early after igt_plane_has_format_mod() to avoid the > overhead up to this point. Also codying style is && at the end of line. > > With the above fixed, looks ok: > Reviewed-by: Imre Deak <imre.deak@intel.com> Thanks for the review! I will fix those two points. Cheers, Mika > > > + > > ret = igt_display_try_commit2(display, commit); > > if (data->flags & TEST_BAD_ROTATION_90) { > > igt_assert_eq(ret, -EINVAL); > > -- > > 2.25.1 > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/kms_ccs: CCS Clear Color test 2020-11-20 9:36 [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test Mika Kahola ` (3 preceding siblings ...) 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test Mika Kahola @ 2020-11-20 10:09 ` Patchwork 2020-11-20 12:09 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-11-20 10:09 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 5233 bytes --] == Series Details == Series: tests/kms_ccs: CCS Clear Color test URL : https://patchwork.freedesktop.org/series/84095/ State : success == Summary == CI Bug Log - changes from CI_DRM_9367 -> IGTPW_5200 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/index.html Known issues ------------ Here are the changes found in IGTPW_5200 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_tiled_blits@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-y/igt@gem_tiled_blits@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-tgl-y/igt@gem_tiled_blits@basic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html - fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html * igt@i915_module_load@reload: - fi-icl-y: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-icl-y/igt@i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-icl-y/igt@i915_module_load@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_psr@primary_page_flip: - fi-tgl-y: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-y/igt@kms_psr@primary_page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-tgl-y/igt@kms_psr@primary_page_flip.html * igt@vgem_basic@dmabuf-fence-before: - fi-tgl-y: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-y/igt@vgem_basic@dmabuf-fence-before.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-tgl-y/igt@vgem_basic@dmabuf-fence-before.html #### Warnings #### * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][21] ([i915#2411] / [i915#402]) -> [DMESG-WARN][22] ([i915#2411]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (45 -> 41) ------------------------------ Additional (1): fi-ehl-1 Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5863 -> IGTPW_5200 CI-20190529: 20190529 CI_DRM_9367: ab86e9c56070fc3d27eabb564159a7a0a4b3265f @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/index.html IGT_5863: 849de1780d33c6749e0a26dc3c642eb9b3d6cd42 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/index.html [-- Attachment #1.2: Type: text/html, Size: 6766 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for tests/kms_ccs: CCS Clear Color test 2020-11-20 9:36 [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test Mika Kahola ` (4 preceding siblings ...) 2020-11-20 10:09 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork @ 2020-11-20 12:09 ` Patchwork 5 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-11-20 12:09 UTC (permalink / raw) To: Kahola, Mika; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 22351 bytes --] == Series Details == Series: tests/kms_ccs: CCS Clear Color test URL : https://patchwork.freedesktop.org/series/84095/ State : success == Summary == CI Bug Log - changes from CI_DRM_9367_full -> IGTPW_5200_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/index.html Known issues ------------ Here are the changes found in IGTPW_5200_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_whisper@basic-forked: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk5/igt@gem_exec_whisper@basic-forked.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk8/igt@gem_exec_whisper@basic-forked.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([i915#1635] / [i915#2635]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl1/igt@gem_workarounds@suspend-resume-context.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl2/igt@gem_workarounds@suspend-resume-context.html - shard-kbl: [PASS][5] -> [INCOMPLETE][6] ([CI#80]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl4/igt@gem_workarounds@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html * igt@i915_pm_rpm@gem-execbuf: - shard-hsw: [PASS][7] -> [SKIP][8] ([fdo#109271]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-hsw6/igt@i915_pm_rpm@gem-execbuf.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-hsw4/igt@i915_pm_rpm@gem-execbuf.html * igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#1982]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl1/igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl4/igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][11] -> [FAIL][12] ([i915#96]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk7/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk5/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([i915#1185]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb5/igt@kms_fbcon_fbt@fbc-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb8/igt@kms_fbcon_fbt@fbc-suspend.html - shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([i915#155]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][19] -> [INCOMPLETE][20] ([i915#2635]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk7/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk6/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1: - shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([i915#2637]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-hsw7/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-hsw4/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_prime@basic-crc@second-to-first: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl4/igt@kms_prime@basic-crc@second-to-first.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl3/igt@kms_prime@basic-crc@second-to-first.html * igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109278]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb4/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb8/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html - shard-glk: [PASS][29] -> [SKIP][30] ([fdo#109271]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk3/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk6/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html - shard-apl: [PASS][31] -> [SKIP][32] ([fdo#109271] / [i915#1635]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html * igt@perf@polling-parameterized: - shard-iclb: [PASS][33] -> [FAIL][34] ([i915#1542]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb5/igt@perf@polling-parameterized.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb4/igt@perf@polling-parameterized.html * igt@perf_pmu@module-unload: - shard-iclb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982] / [i915#262]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb2/igt@perf_pmu@module-unload.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb6/igt@perf_pmu@module-unload.html #### Possible fixes #### * igt@gem_huc_copy@huc-copy: - shard-tglb: [SKIP][37] ([i915#2190]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb6/igt@gem_huc_copy@huc-copy.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb7/igt@gem_huc_copy@huc-copy.html * igt@i915_module_load@reload: - shard-tglb: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb7/igt@i915_module_load@reload.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb3/igt@i915_module_load@reload.html * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-hsw: [SKIP][41] ([fdo#109271]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-hsw2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-hsw8/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html - shard-kbl: [SKIP][43] ([fdo#109271]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl1/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html - shard-apl: [SKIP][45] ([fdo#109271] / [i915#1635]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl3/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html - shard-glk: [SKIP][47] ([fdo#109271]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk9/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge: - shard-apl: [DMESG-WARN][49] ([i915#1635] / [i915#1982]) -> [PASS][50] +5 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl7/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl8/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [FAIL][51] ([i915#96]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [FAIL][53] ([i915#2370]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-iclb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-glk: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +7 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-hsw: [INCOMPLETE][59] ([i915#2637]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-hsw2/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-hsw7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html - shard-kbl: [INCOMPLETE][61] ([i915#155]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html - shard-iclb: [INCOMPLETE][63] ([i915#1185]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb3/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html - shard-apl: [INCOMPLETE][65] ([i915#1635] / [i915#2635]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html - shard-glk: [INCOMPLETE][67] ([i915#2635]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk9/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk8/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-b-wait-forked-busy: - shard-kbl: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +6 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl7/igt@kms_vblank@pipe-b-wait-forked-busy.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html * igt@perf@polling-parameterized: - shard-tglb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb2/igt@perf@polling-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb2/igt@perf@polling-parameterized.html #### Warnings #### * igt@gem_workarounds@suspend-resume-context: - shard-tglb: [DMESG-WARN][73] ([i915#2411]) -> [INCOMPLETE][74] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411] / [i915#456]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb6/igt@gem_workarounds@suspend-resume-context.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb7/igt@gem_workarounds@suspend-resume-context.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][75] ([i915#588]) -> [SKIP][76] ([i915#658]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-tglb: [SKIP][77] ([i915#579]) -> [SKIP][78] ([fdo#111644] / [i915#1397] / [i915#2411]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb8/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html - shard-iclb: [SKIP][79] ([i915#579]) -> [SKIP][80] ([fdo#110892]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-tglb: [SKIP][81] ([fdo#109506] / [i915#2411]) -> [SKIP][82] ([i915#579]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb7/igt@i915_pm_rpm@modeset-pc8-residency-stress.html - shard-iclb: [SKIP][83] ([fdo#109293] / [fdo#109506]) -> [SKIP][84] ([i915#579]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb8/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm: - shard-tglb: [DMESG-WARN][85] ([i915#2411]) -> [SKIP][86] ([i915#2648]) +1 similar issue [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb6/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb7/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-tglb: [INCOMPLETE][87] ([i915#1436] / [i915#1602] / [i915#1798] / [i915#1887] / [i915#1982] / [i915#2411] / [i915#456]) -> [DMESG-WARN][88] ([i915#2411]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-tglb8/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-tglb1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html * igt@runner@aborted: - shard-kbl: ([FAIL][89], [FAIL][90]) ([i915#1814] / [i915#2295] / [i915#483] / [i915#602]) -> ([FAIL][91], [FAIL][92]) ([i915#2295] / [i915#92]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl1/igt@runner@aborted.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-kbl2/igt@runner@aborted.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl7/igt@runner@aborted.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-kbl7/igt@runner@aborted.html - shard-iclb: ([FAIL][93], [FAIL][94]) ([i915#1814] / [i915#2295] / [i915#483]) -> ([FAIL][95], [FAIL][96], [FAIL][97]) ([i915#2295] / [i915#483]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb2/igt@runner@aborted.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-iclb7/igt@runner@aborted.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb5/igt@runner@aborted.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb8/igt@runner@aborted.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-iclb8/igt@runner@aborted.html - shard-apl: ([FAIL][98], [FAIL][99]) ([i915#1635] / [i915#1814] / [i915#2295]) -> ([FAIL][100], [FAIL][101], [FAIL][102]) ([fdo#109271] / [i915#1635] / [i915#2295]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl4/igt@runner@aborted.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-apl3/igt@runner@aborted.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl6/igt@runner@aborted.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl7/igt@runner@aborted.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-apl2/igt@runner@aborted.html - shard-glk: ([FAIL][103], [FAIL][104]) ([i915#1814] / [i915#2295] / [k.org#202321]) -> ([FAIL][105], [FAIL][106], [FAIL][107]) ([i915#2295] / [k.org#202321]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk9/igt@runner@aborted.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/shard-glk6/igt@runner@aborted.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk1/igt@runner@aborted.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk6/igt@runner@aborted.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/shard-glk2/igt@runner@aborted.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1798]: https://gitlab.freedesktop.org/drm/intel/issues/1798 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635 [i915#2637]: https://gitlab.freedesktop.org/drm/intel/issues/2637 [i915#2648]: https://gitlab.freedesktop.org/drm/intel/issues/2648 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (10 -> 8) ------------------------------ Missing (2): pig-skl-6260u pig-glk-j5005 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5863 -> IGTPW_5200 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_9367: ab86e9c56070fc3d27eabb564159a7a0a4b3265f @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/index.html IGT_5863: 849de1780d33c6749e0a26dc3c642eb9b3d6cd42 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5200/index.html [-- Attachment #1.2: Type: text/html, Size: 28136 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-11-20 12:09 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-11-20 9:36 [igt-dev] [PATCH i-g-t v10 0/4] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 1/4] tests/kms_ccs: Add debug information on format modifier Mika Kahola 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 2/4] lib/rendercopy: Enable fast clear Mika Kahola 2020-11-20 11:43 ` Imre Deak 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 3/4] lib/intel_aux_pgtable: Initialize aux pagetable for " Mika Kahola 2020-11-20 11:44 ` Imre Deak 2020-11-20 9:36 ` [igt-dev] [PATCH i-g-t v10 4/4] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-11-20 11:52 ` Imre Deak 2020-11-20 11:56 ` Kahola, Mika 2020-11-20 10:09 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2020-11-20 12:09 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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