[igt-dev] [PATCH i-g-t v3 00/15] DG2 platform definition and Tile 4 plane format support

[igt-dev] [PATCH i-g-t v3 00/15] DG2 platform definition and Tile 4 plane format support

[Jeevan B]

Added DG2 platform definition with PCI IDS.
Also introduce support for the new Tile4 format, which is
4K column-major tiles consisting of 64B row-major subtiles,
with same base structure as Y Tile(16B OWords * 4)

v3: Remove DG2 platform definition patch and
    Add check for tile4 support in kms_draw_crc patch.


Jeevan B (6):
  igt/tests: Add support for Tile4(TileF) format to kms_rotation_crc
  igt/tests: Add support for Tile4(TileF) format to
    tests/kms_plane_multiple
  igt/tests: Add support for Tile4(TileF) format to
    tests/kms_plane_lowres
  igt/tests: Add support for Tile4(TileF) format to tests/kms_big_fb
  igt/tests: Add support for Tile4(TileF) format to
    tests/kms_addfb_basic
  tests/kms_plane_scaling: Adding Tile-4 support

Matt Roper (3):
  lib/igt_draw: Add pixel math for tile-4
  igt/tests: Add support for Tile4(TileF) format to testdisplay
  lib/igt_draw: Use XY_FAST_COLOR_BLT on DG2

Mika Kahola (4):
  lib/intel_device_info: Add a flag to indicate tiling 4 support
  tests/kms_frontbuffer_tracking: Add support for 4 tiling
  tests/kms_draw_crc: Use 4 tiling when filling framebuffer
  tests/kms_plane_scaling: Use tiling 4 if platform has support for it

Stanislav Lisovskiy (2):
  igt/lib: Add tile 4(F-tile) format support
  igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

 include/drm-uapi/drm_fourcc.h         |  39 +++++
 include/drm-uapi/i915_drm.h           |   3 +-
 lib/gpu_cmds.c                        |   4 +-
 lib/igt_draw.c                        | 223 ++++++++++++++++++++++----
 lib/igt_fb.c                          |  40 ++++-
 lib/intel_batchbuffer.c               |   8 +-
 lib/intel_batchbuffer.h               |   4 +-
 lib/intel_chipset.h                   |   3 +
 lib/intel_device_info.c               |   1 +
 lib/intel_reg.h                       |   2 +
 tests/i915/kms_big_fb.c               |   1 +
 tests/i915/kms_draw_crc.c             |  23 ++-
 tests/i915/kms_frontbuffer_tracking.c |  22 ++-
 tests/kms_addfb_basic.c               |  44 ++++-
 tests/kms_plane_lowres.c              |   3 +
 tests/kms_plane_multiple.c            |   3 +
 tests/kms_plane_scaling.c             |  22 ++-
 tests/kms_rotation_crc.c              |   4 +
 tests/testdisplay.c                   |   6 +-
 19 files changed, 400 insertions(+), 55 deletions(-)

-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 01/15] lib/intel_device_info: Add a flag to indicate tiling 4 support

[Jeevan B]

From: Mika Kahola <mika.kahola@intel.com>

Add tiling 4 support flag for DG2 platform. This is similar that
we have defined in kernel i915_pci.c intel_device_info() for DG2.

v2: rebase

Signed-off-by: Jeevan B <jeevan.b@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
 lib/intel_chipset.h     | 3 +++
 lib/intel_device_info.c | 1 +
 2 files changed, 4 insertions(+)

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index e27b9aab..db75a829 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -40,6 +40,7 @@ struct intel_device_info {
 	unsigned graphics_ver;
 	unsigned display_ver;
 	unsigned gt; /* 0 if unknown */
+	bool has_4tile : 1;
 	bool has_flatccs;
 	bool is_mobile : 1;
 	bool is_whitney : 1;
@@ -216,6 +217,8 @@ void intel_check_pch(void);
 				   IS_CHERRYVIEW(devid) || \
 				   IS_BROXTON(devid)))
 
+#define HAS_4TILE(devid)	(intel_get_device_info(devid)->has_4tile)
+
 #define HAS_FLATCCS(devid)	(intel_get_device_info(devid)->has_flatccs)
 
 #endif /* _INTEL_CHIPSET_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 9f191367..e55841df 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -393,6 +393,7 @@ static const struct intel_device_info intel_dg1_info = {
 static const struct intel_device_info intel_dg2_info = {
 	.graphics_ver = 12,
 	.display_ver = 13,
+	.has_4tile = true,
 	.is_dg2 = true,
 	.codename = "dg2",
 	.has_flatccs = true,
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 02/15] igt/lib: Add tile 4(F-tile) format support

[Jeevan B]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Introduce support for the new Tile4 format, which is
4K column-major tiles consisting of 64B row-major subtiles,
with same base structure as Y Tile(16B OWords * 4)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 include/drm-uapi/drm_fourcc.h | 39 ++++++++++++++++++++++++++++++++++
 include/drm-uapi/i915_drm.h   |  3 ++-
 lib/gpu_cmds.c                |  4 ++--
 lib/igt_draw.c                |  7 +++++-
 lib/igt_fb.c                  | 40 ++++++++++++++++++++++++++++++-----
 lib/intel_batchbuffer.c       |  8 +++++--
 lib/intel_batchbuffer.h       |  4 ++--
 7 files changed, 92 insertions(+), 13 deletions(-)

diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 91b6a0fd..4dc4e5a4 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -559,6 +559,45 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
 
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED                 fourcc_mod_code(INTEL, 12)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 render compression.
+ *
+ * DG2 uses a new compression format for render compression. The general
+ * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ * but a new hashing/compression algorithm is used, so a fresh modifier must
+ * be associated with buffers of this type. Render compression uses 128 byte
+ * compression blocks.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS              fourcc_mod_code(INTEL, 9)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 media compression.
+ *
+ * DG2 uses a new compression format for media compression. The general
+ * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ * but a new hashing/compression algorithm is used, so a fresh modifier must
+ * be associated with buffers of this type. Media compression uses 256 byte
+ * compression blocks.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS              fourcc_mod_code(INTEL, 10)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 clear color render compression.
+ *
+ * DG2 uses a unified compression format for clear color render compression.
+ * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC           fourcc_mod_code(INTEL, 11)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 9c9e1afa..75206fc3 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1522,13 +1522,14 @@ struct drm_i915_gem_caching {
 #define I915_TILING_NONE	0
 #define I915_TILING_X		1
 #define I915_TILING_Y		2
+#define I915_TILING_4		3
 /*
  * Do not add new tiling types here.  The I915_TILING_* values are for
  * de-tiling fence registers that no longer exist on modern platforms.  Although
  * the hardware may support new types of tiling in general (e.g., Tile4), we
  * do not need to add them to the uapi that is specific to now-defunct ioctls.
  */
-#define I915_TILING_LAST	I915_TILING_Y
+#define I915_TILING_LAST	I915_TILING_4
 
 #define I915_BIT_6_SWIZZLE_NONE		0
 #define I915_BIT_6_SWIZZLE_9		1
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index a45a9048..c31b51f7 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -156,7 +156,7 @@ gen8_fill_surface_state(struct intel_bb *ibb,
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
-	else if (buf->tiling == I915_TILING_Y)
+	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
 		ss->ss0.tiled_mode = 3;
 
 	address = intel_bb_offset_reloc(ibb, buf->handle,
@@ -211,7 +211,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
-	else if (buf->tiling == I915_TILING_Y)
+	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
 		ss->ss0.tiled_mode = 3;
 	else
 		ss->ss0.tiled_mode = 0;
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 2af27b11..0ca43deb 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -271,7 +271,7 @@ static void switch_blt_tiling(struct intel_bb *ibb, uint32_t tiling, bool on)
 	uint32_t bcs_swctrl;
 
 	/* Default is X-tile */
-	if (tiling != I915_TILING_Y)
+	if (tiling != I915_TILING_Y && tiling != I915_TILING_4)
 		return;
 
 	igt_require(ibb->gen >= 6);
@@ -318,6 +318,7 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t stride, uint32_t tiling,
 							       swizzle, bpp);
 				break;
 			case I915_TILING_Y:
+			case I915_TILING_4:
 				pos = linear_x_y_to_ytiled_pos(x, y, stride,
 							       swizzle, bpp);
 				break;
@@ -350,6 +351,7 @@ static void draw_rect_mmap_cpu(int fd, struct buf_data *buf, struct rect *rect,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_4:
 		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
 				    color, buf->bpp);
 		break;
@@ -409,6 +411,7 @@ static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect *rect,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_4:
 		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
 				    color, buf->bpp);
 		break;
@@ -467,6 +470,7 @@ static void draw_rect_pwrite_tiled(int fd, struct buf_data *buf,
 						 swizzle, buf->bpp, &x, &y);
 			break;
 		case I915_TILING_Y:
+		case I915_TILING_4:
 			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
 						 swizzle, buf->bpp, &x, &y);
 			break;
@@ -507,6 +511,7 @@ static void draw_rect_pwrite(int fd, struct buf_data *buf,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_4:
 		draw_rect_pwrite_tiled(fd, buf, tiling, rect, color, swizzle);
 		break;
 	default:
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 1530b960..4fa357f8 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -456,6 +456,10 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 		igt_require_intel(fd);
 		if (intel_display_ver(intel_get_drm_devid(fd)) == 2) {
 			*width_ret = 128;
@@ -564,14 +568,17 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 
 static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
 }
 
 static bool is_gen12_ccs_modifier(uint64_t modifier)
 {
 	return is_gen12_mc_ccs_modifier(modifier) ||
 		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
+		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
 }
 
 static bool is_ccs_modifier(uint64_t modifier)
@@ -601,8 +608,15 @@ static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane)
 
 static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
 {
-	return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
-	       plane == 2;
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
+	       plane == 2)
+		return true;
+
+	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC &&
+		plane == 1)
+		return true;
+
+	return false;
 }
 
 bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
@@ -688,7 +702,8 @@ static int fb_num_planes(const struct igt_fb *fb)
 	if (is_ccs_modifier(fb->modifier))
 		num_planes *= 2;
 
-	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+	    fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
 		num_planes++;
 
 	return num_planes;
@@ -964,6 +979,11 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
+	case I915_FORMAT_MOD_4_TILED:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+		return I915_TILING_4;
 	case I915_FORMAT_MOD_Yf_TILED:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 		return I915_TILING_Yf;
@@ -991,6 +1011,8 @@ uint64_t igt_fb_tiling_to_mod(uint64_t tiling)
 		return I915_FORMAT_MOD_X_TILED;
 	case I915_TILING_Y:
 		return I915_FORMAT_MOD_Y_TILED;
+	case I915_TILING_4:
+		return I915_FORMAT_MOD_4_TILED;
 	case I915_TILING_Yf:
 		return I915_FORMAT_MOD_Yf_TILED;
 	default:
@@ -4398,6 +4420,14 @@ const char *igt_fb_modifier_name(uint64_t modifier)
 		return "Y-RC_CCS-CC";
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return "Y-MC_CCS";
+	case I915_FORMAT_MOD_4_TILED:
+		return "4";
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+		return "4-RC_CCS";
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+		return "4-MC_CCS";
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+		return "4-RC_CCS-CC";
 	default:
 		return "?";
 	}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index e5666cd4..f02d0f3c 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -617,6 +617,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
 		dword0 |= XY_FAST_COPY_SRC_TILING_X;
 		break;
 	case I915_TILING_Y:
+	case I915_TILING_4:
 	case I915_TILING_Yf:
 		dword0 |= XY_FAST_COPY_SRC_TILING_Yb_Yf;
 		break;
@@ -633,6 +634,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
 		dword0 |= XY_FAST_COPY_DST_TILING_X;
 		break;
 	case I915_TILING_Y:
+	case I915_TILING_4:
 	case I915_TILING_Yf:
 		dword0 |= XY_FAST_COPY_DST_TILING_Yb_Yf;
 		break;
@@ -653,9 +655,11 @@ static uint32_t fast_copy_dword1(unsigned int src_tiling,
 {
 	uint32_t dword1 = 0;
 
-	if (src_tiling == I915_TILING_Yf)
+	if (src_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
+		/* Repurposed as Tile-4 on DG2 */
 		dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
-	if (dst_tiling == I915_TILING_Yf)
+	if (dst_tiling == I915_TILING_Yf || dst_tiling == I915_TILING_4)
+		/* Repurposed as Tile-4 on DG2 */
 		dword1 |= XY_FAST_COPY_DST_TILING_Yf;
 
 	switch (bpp) {
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index a488f9cf..4cf67296 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -210,8 +210,8 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
  *
  * They are to be used the the blitting routines below.
  */
-#define I915_TILING_Yf	3
-#define I915_TILING_Ys	4
+#define I915_TILING_Yf	(I915_TILING_LAST + 1)
+#define I915_TILING_Ys	(I915_TILING_LAST + 2)
 
 enum i915_compression {
 	I915_COMPRESSION_NONE,
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t v3 02/15] igt/lib: Add tile 4(F-tile) format support

[Petri Latvala]

On Wed, Feb 16, 2022 at 03:56:20PM +0530, Jeevan B wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Introduce support for the new Tile4 format, which is
> 4K column-major tiles consisting of 64B row-major subtiles,
> with same base structure as Y Tile(16B OWords * 4)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>  include/drm-uapi/drm_fourcc.h | 39 ++++++++++++++++++++++++++++++++++
>  include/drm-uapi/i915_drm.h   |  3 ++-

Please separate the change to these two files into a separate commit
that copies the files from the kernel, with the commit message stating
which kernel commit they're from.


-- 
Petri Latvala




>  lib/gpu_cmds.c                |  4 ++--
>  lib/igt_draw.c                |  7 +++++-
>  lib/igt_fb.c                  | 40 ++++++++++++++++++++++++++++++-----
>  lib/intel_batchbuffer.c       |  8 +++++--
>  lib/intel_batchbuffer.h       |  4 ++--
>  7 files changed, 92 insertions(+), 13 deletions(-)
> 
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
> index 91b6a0fd..4dc4e5a4 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -559,6 +559,45 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
>  
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_4_TILED                 fourcc_mod_code(INTEL, 12)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 render compression.
> + *
> + * DG2 uses a new compression format for render compression. The general
> + * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + * but a new hashing/compression algorithm is used, so a fresh modifier must
> + * be associated with buffers of this type. Render compression uses 128 byte
> + * compression blocks.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS              fourcc_mod_code(INTEL, 9)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 media compression.
> + *
> + * DG2 uses a new compression format for media compression. The general
> + * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + * but a new hashing/compression algorithm is used, so a fresh modifier must
> + * be associated with buffers of this type. Media compression uses 256 byte
> + * compression blocks.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS              fourcc_mod_code(INTEL, 10)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 clear color render compression.
> + *
> + * DG2 uses a unified compression format for clear color render compression.
> + * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC           fourcc_mod_code(INTEL, 11)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 9c9e1afa..75206fc3 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -1522,13 +1522,14 @@ struct drm_i915_gem_caching {
>  #define I915_TILING_NONE	0
>  #define I915_TILING_X		1
>  #define I915_TILING_Y		2
> +#define I915_TILING_4		3
>  /*
>   * Do not add new tiling types here.  The I915_TILING_* values are for
>   * de-tiling fence registers that no longer exist on modern platforms.  Although
>   * the hardware may support new types of tiling in general (e.g., Tile4), we
>   * do not need to add them to the uapi that is specific to now-defunct ioctls.
>   */
> -#define I915_TILING_LAST	I915_TILING_Y
> +#define I915_TILING_LAST	I915_TILING_4
>  
>  #define I915_BIT_6_SWIZZLE_NONE		0
>  #define I915_BIT_6_SWIZZLE_9		1
> diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
> index a45a9048..c31b51f7 100644
> --- a/lib/gpu_cmds.c
> +++ b/lib/gpu_cmds.c
> @@ -156,7 +156,7 @@ gen8_fill_surface_state(struct intel_bb *ibb,
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> -	else if (buf->tiling == I915_TILING_Y)
> +	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
>  		ss->ss0.tiled_mode = 3;
>  
>  	address = intel_bb_offset_reloc(ibb, buf->handle,
> @@ -211,7 +211,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> -	else if (buf->tiling == I915_TILING_Y)
> +	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
>  		ss->ss0.tiled_mode = 3;
>  	else
>  		ss->ss0.tiled_mode = 0;
> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
> index 2af27b11..0ca43deb 100644
> --- a/lib/igt_draw.c
> +++ b/lib/igt_draw.c
> @@ -271,7 +271,7 @@ static void switch_blt_tiling(struct intel_bb *ibb, uint32_t tiling, bool on)
>  	uint32_t bcs_swctrl;
>  
>  	/* Default is X-tile */
> -	if (tiling != I915_TILING_Y)
> +	if (tiling != I915_TILING_Y && tiling != I915_TILING_4)
>  		return;
>  
>  	igt_require(ibb->gen >= 6);
> @@ -318,6 +318,7 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t stride, uint32_t tiling,
>  							       swizzle, bpp);
>  				break;
>  			case I915_TILING_Y:
> +			case I915_TILING_4:
>  				pos = linear_x_y_to_ytiled_pos(x, y, stride,
>  							       swizzle, bpp);
>  				break;
> @@ -350,6 +351,7 @@ static void draw_rect_mmap_cpu(int fd, struct buf_data *buf, struct rect *rect,
>  		break;
>  	case I915_TILING_X:
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
>  				    color, buf->bpp);
>  		break;
> @@ -409,6 +411,7 @@ static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect *rect,
>  		break;
>  	case I915_TILING_X:
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
>  				    color, buf->bpp);
>  		break;
> @@ -467,6 +470,7 @@ static void draw_rect_pwrite_tiled(int fd, struct buf_data *buf,
>  						 swizzle, buf->bpp, &x, &y);
>  			break;
>  		case I915_TILING_Y:
> +		case I915_TILING_4:
>  			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
>  						 swizzle, buf->bpp, &x, &y);
>  			break;
> @@ -507,6 +511,7 @@ static void draw_rect_pwrite(int fd, struct buf_data *buf,
>  		break;
>  	case I915_TILING_X:
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  		draw_rect_pwrite_tiled(fd, buf, tiling, rect, color, swizzle);
>  		break;
>  	default:
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 1530b960..4fa357f8 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -456,6 +456,10 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +	case I915_FORMAT_MOD_4_TILED:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>  		igt_require_intel(fd);
>  		if (intel_display_ver(intel_get_drm_devid(fd)) == 2) {
>  			*width_ret = 128;
> @@ -564,14 +568,17 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
>  
>  static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
>  }
>  
>  static bool is_gen12_ccs_modifier(uint64_t modifier)
>  {
>  	return is_gen12_mc_ccs_modifier(modifier) ||
>  		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> -		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> +		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
>  }
>  
>  static bool is_ccs_modifier(uint64_t modifier)
> @@ -601,8 +608,15 @@ static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane)
>  
>  static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
>  {
> -	return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> -	       plane == 2;
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> +	       plane == 2)
> +		return true;
> +
> +	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC &&
> +		plane == 1)
> +		return true;
> +
> +	return false;
>  }
>  
>  bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
> @@ -688,7 +702,8 @@ static int fb_num_planes(const struct igt_fb *fb)
>  	if (is_ccs_modifier(fb->modifier))
>  		num_planes *= 2;
>  
> -	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> +	    fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
>  		num_planes++;
>  
>  	return num_planes;
> @@ -964,6 +979,11 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return I915_TILING_Y;
> +	case I915_FORMAT_MOD_4_TILED:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> +		return I915_TILING_4;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  		return I915_TILING_Yf;
> @@ -991,6 +1011,8 @@ uint64_t igt_fb_tiling_to_mod(uint64_t tiling)
>  		return I915_FORMAT_MOD_X_TILED;
>  	case I915_TILING_Y:
>  		return I915_FORMAT_MOD_Y_TILED;
> +	case I915_TILING_4:
> +		return I915_FORMAT_MOD_4_TILED;
>  	case I915_TILING_Yf:
>  		return I915_FORMAT_MOD_Yf_TILED;
>  	default:
> @@ -4398,6 +4420,14 @@ const char *igt_fb_modifier_name(uint64_t modifier)
>  		return "Y-RC_CCS-CC";
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return "Y-MC_CCS";
> +	case I915_FORMAT_MOD_4_TILED:
> +		return "4";
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +		return "4-RC_CCS";
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +		return "4-MC_CCS";
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> +		return "4-RC_CCS-CC";
>  	default:
>  		return "?";
>  	}
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index e5666cd4..f02d0f3c 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -617,6 +617,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
>  		dword0 |= XY_FAST_COPY_SRC_TILING_X;
>  		break;
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  	case I915_TILING_Yf:
>  		dword0 |= XY_FAST_COPY_SRC_TILING_Yb_Yf;
>  		break;
> @@ -633,6 +634,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
>  		dword0 |= XY_FAST_COPY_DST_TILING_X;
>  		break;
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  	case I915_TILING_Yf:
>  		dword0 |= XY_FAST_COPY_DST_TILING_Yb_Yf;
>  		break;
> @@ -653,9 +655,11 @@ static uint32_t fast_copy_dword1(unsigned int src_tiling,
>  {
>  	uint32_t dword1 = 0;
>  
> -	if (src_tiling == I915_TILING_Yf)
> +	if (src_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
> +		/* Repurposed as Tile-4 on DG2 */
>  		dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
> -	if (dst_tiling == I915_TILING_Yf)
> +	if (dst_tiling == I915_TILING_Yf || dst_tiling == I915_TILING_4)
> +		/* Repurposed as Tile-4 on DG2 */
>  		dword1 |= XY_FAST_COPY_DST_TILING_Yf;
>  
>  	switch (bpp) {
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index a488f9cf..4cf67296 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -210,8 +210,8 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
>   *
>   * They are to be used the the blitting routines below.
>   */
> -#define I915_TILING_Yf	3
> -#define I915_TILING_Ys	4
> +#define I915_TILING_Yf	(I915_TILING_LAST + 1)
> +#define I915_TILING_Ys	(I915_TILING_LAST + 2)
>  
>  enum i915_compression {
>  	I915_COMPRESSION_NONE,
> -- 
> 2.17.1
> 

Re: [igt-dev] [PATCH i-g-t v3 02/15] igt/lib: Add tile 4(F-tile) format support

[B, Jeevan]

>-----Original Message-----
>From: Latvala, Petri <petri.latvala@intel.com>
>Sent: Wednesday, February 16, 2022 4:17 PM
>To: B, Jeevan <jeevan.b@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Heikkila, Juha-pekka <juha-
>pekka.heikkila@intel.com>
>Subject: Re: [igt-dev] [PATCH i-g-t v3 02/15] igt/lib: Add tile 4(F-tile) format
>support
>
>On Wed, Feb 16, 2022 at 03:56:20PM +0530, Jeevan B wrote:
>> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>
>> Introduce support for the new Tile4 format, which is 4K column-major
>> tiles consisting of 64B row-major subtiles, with same base structure
>> as Y Tile(16B OWords * 4)
>>
>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> Signed-off-by: Jeevan B <jeevan.b@intel.com>
>> ---
>>  include/drm-uapi/drm_fourcc.h | 39 ++++++++++++++++++++++++++++++++++
>>  include/drm-uapi/i915_drm.h   |  3 ++-
>
>Please separate the change to these two files into a separate commit that copies
>the files from the kernel, with the commit message stating which kernel commit
>they're from.

Sure, Will do this. 
Thanks 
>
>
>--
>Petri Latvala
>
>
>
>
>>  lib/gpu_cmds.c                |  4 ++--
>>  lib/igt_draw.c                |  7 +++++-
>>  lib/igt_fb.c                  | 40 ++++++++++++++++++++++++++++++-----
>>  lib/intel_batchbuffer.c       |  8 +++++--
>>  lib/intel_batchbuffer.h       |  4 ++--
>>  7 files changed, 92 insertions(+), 13 deletions(-)
>>
>> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
>> index 91b6a0fd..4dc4e5a4 100644
>> --- a/include/drm-uapi/drm_fourcc.h
>> +++ b/include/drm-uapi/drm_fourcc.h
>> @@ -559,6 +559,45 @@ extern "C" {
>>   */
>>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
>fourcc_mod_code(INTEL, 8)
>>
>> +/*
>> + * Intel F-tiling(aka Tile4) layout
>> + *
>> + * This is a tiled layout using 4Kb tiles in row-major layout.
>> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
>> + * (16 bytes) chunks column-major..
>> + */
>> +#define I915_FORMAT_MOD_4_TILED                 fourcc_mod_code(INTEL, 12)
>> +
>> +/*
>> + * Intel color control surfaces (CCS) for DG2 render compression.
>> + *
>> + * DG2 uses a new compression format for render compression. The general
>> + * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>> + * but a new hashing/compression algorithm is used, so a fresh modifier must
>> + * be associated with buffers of this type. Render compression uses 128 byte
>> + * compression blocks.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS
>fourcc_mod_code(INTEL, 9)
>> +
>> +/*
>> + * Intel color control surfaces (CCS) for DG2 media compression.
>> + *
>> + * DG2 uses a new compression format for media compression. The general
>> + * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>> + * but a new hashing/compression algorithm is used, so a fresh modifier must
>> + * be associated with buffers of this type. Media compression uses 256 byte
>> + * compression blocks.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS
>fourcc_mod_code(INTEL, 10)
>> +
>> +/*
>> + * Intel color control surfaces (CCS) for DG2 clear color render compression.
>> + *
>> + * DG2 uses a unified compression format for clear color render compression.
>> + * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC
>fourcc_mod_code(INTEL, 11)
>> +
>>  /*
>>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>>   *
>> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
>> index 9c9e1afa..75206fc3 100644
>> --- a/include/drm-uapi/i915_drm.h
>> +++ b/include/drm-uapi/i915_drm.h
>> @@ -1522,13 +1522,14 @@ struct drm_i915_gem_caching {
>>  #define I915_TILING_NONE	0
>>  #define I915_TILING_X		1
>>  #define I915_TILING_Y		2
>> +#define I915_TILING_4		3
>>  /*
>>   * Do not add new tiling types here.  The I915_TILING_* values are for
>>   * de-tiling fence registers that no longer exist on modern platforms.  Although
>>   * the hardware may support new types of tiling in general (e.g., Tile4), we
>>   * do not need to add them to the uapi that is specific to now-defunct ioctls.
>>   */
>> -#define I915_TILING_LAST	I915_TILING_Y
>> +#define I915_TILING_LAST	I915_TILING_4
>>
>>  #define I915_BIT_6_SWIZZLE_NONE		0
>>  #define I915_BIT_6_SWIZZLE_9		1
>> diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
>> index a45a9048..c31b51f7 100644
>> --- a/lib/gpu_cmds.c
>> +++ b/lib/gpu_cmds.c
>> @@ -156,7 +156,7 @@ gen8_fill_surface_state(struct intel_bb *ibb,
>>
>>  	if (buf->tiling == I915_TILING_X)
>>  		ss->ss0.tiled_mode = 2;
>> -	else if (buf->tiling == I915_TILING_Y)
>> +	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
>>  		ss->ss0.tiled_mode = 3;
>>
>>  	address = intel_bb_offset_reloc(ibb, buf->handle,
>> @@ -211,7 +211,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
>>
>>  	if (buf->tiling == I915_TILING_X)
>>  		ss->ss0.tiled_mode = 2;
>> -	else if (buf->tiling == I915_TILING_Y)
>> +	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
>>  		ss->ss0.tiled_mode = 3;
>>  	else
>>  		ss->ss0.tiled_mode = 0;
>> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
>> index 2af27b11..0ca43deb 100644
>> --- a/lib/igt_draw.c
>> +++ b/lib/igt_draw.c
>> @@ -271,7 +271,7 @@ static void switch_blt_tiling(struct intel_bb *ibb,
>uint32_t tiling, bool on)
>>  	uint32_t bcs_swctrl;
>>
>>  	/* Default is X-tile */
>> -	if (tiling != I915_TILING_Y)
>> +	if (tiling != I915_TILING_Y && tiling != I915_TILING_4)
>>  		return;
>>
>>  	igt_require(ibb->gen >= 6);
>> @@ -318,6 +318,7 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t
>stride, uint32_t tiling,
>>  							       swizzle, bpp);
>>  				break;
>>  			case I915_TILING_Y:
>> +			case I915_TILING_4:
>>  				pos = linear_x_y_to_ytiled_pos(x, y, stride,
>>  							       swizzle, bpp);
>>  				break;
>> @@ -350,6 +351,7 @@ static void draw_rect_mmap_cpu(int fd, struct
>buf_data *buf, struct rect *rect,
>>  		break;
>>  	case I915_TILING_X:
>>  	case I915_TILING_Y:
>> +	case I915_TILING_4:
>>  		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
>>  				    color, buf->bpp);
>>  		break;
>> @@ -409,6 +411,7 @@ static void draw_rect_mmap_wc(int fd, struct buf_data
>*buf, struct rect *rect,
>>  		break;
>>  	case I915_TILING_X:
>>  	case I915_TILING_Y:
>> +	case I915_TILING_4:
>>  		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
>>  				    color, buf->bpp);
>>  		break;
>> @@ -467,6 +470,7 @@ static void draw_rect_pwrite_tiled(int fd, struct
>buf_data *buf,
>>  						 swizzle, buf->bpp, &x, &y);
>>  			break;
>>  		case I915_TILING_Y:
>> +		case I915_TILING_4:
>>  			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
>>  						 swizzle, buf->bpp, &x, &y);
>>  			break;
>> @@ -507,6 +511,7 @@ static void draw_rect_pwrite(int fd, struct buf_data
>*buf,
>>  		break;
>>  	case I915_TILING_X:
>>  	case I915_TILING_Y:
>> +	case I915_TILING_4:
>>  		draw_rect_pwrite_tiled(fd, buf, tiling, rect, color, swizzle);
>>  		break;
>>  	default:
>> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
>> index 1530b960..4fa357f8 100644
>> --- a/lib/igt_fb.c
>> +++ b/lib/igt_fb.c
>> @@ -456,6 +456,10 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int
>fb_bpp,
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>> +	case I915_FORMAT_MOD_4_TILED:
>> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
>> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>>  		igt_require_intel(fd);
>>  		if (intel_display_ver(intel_get_drm_devid(fd)) == 2) {
>>  			*width_ret = 128;
>> @@ -564,14 +568,17 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int
>fb_bpp,
>>
>>  static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
>>  {
>> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
>> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
>> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
>>  }
>>
>>  static bool is_gen12_ccs_modifier(uint64_t modifier)
>>  {
>>  	return is_gen12_mc_ccs_modifier(modifier) ||
>>  		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
>> -		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
>> +		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
>||
>> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
>> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
>>  }
>>
>>  static bool is_ccs_modifier(uint64_t modifier)
>> @@ -601,8 +608,15 @@ static bool is_gen12_ccs_plane(const struct igt_fb
>*fb, int plane)
>>
>>  static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
>>  {
>> -	return fb->modifier ==
>I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
>> -	       plane == 2;
>> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
>&&
>> +	       plane == 2)
>> +		return true;
>> +
>> +	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC &&
>> +		plane == 1)
>> +		return true;
>> +
>> +	return false;
>>  }
>>
>>  bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
>> @@ -688,7 +702,8 @@ static int fb_num_planes(const struct igt_fb *fb)
>>  	if (is_ccs_modifier(fb->modifier))
>>  		num_planes *= 2;
>>
>> -	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
>> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
>> +	    fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
>>  		num_planes++;
>>
>>  	return num_planes;
>> @@ -964,6 +979,11 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>>  		return I915_TILING_Y;
>> +	case I915_FORMAT_MOD_4_TILED:
>> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
>> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>> +		return I915_TILING_4;
>>  	case I915_FORMAT_MOD_Yf_TILED:
>>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>>  		return I915_TILING_Yf;
>> @@ -991,6 +1011,8 @@ uint64_t igt_fb_tiling_to_mod(uint64_t tiling)
>>  		return I915_FORMAT_MOD_X_TILED;
>>  	case I915_TILING_Y:
>>  		return I915_FORMAT_MOD_Y_TILED;
>> +	case I915_TILING_4:
>> +		return I915_FORMAT_MOD_4_TILED;
>>  	case I915_TILING_Yf:
>>  		return I915_FORMAT_MOD_Yf_TILED;
>>  	default:
>> @@ -4398,6 +4420,14 @@ const char *igt_fb_modifier_name(uint64_t
>modifier)
>>  		return "Y-RC_CCS-CC";
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>>  		return "Y-MC_CCS";
>> +	case I915_FORMAT_MOD_4_TILED:
>> +		return "4";
>> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
>> +		return "4-RC_CCS";
>> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>> +		return "4-MC_CCS";
>> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>> +		return "4-RC_CCS-CC";
>>  	default:
>>  		return "?";
>>  	}
>> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
>> index e5666cd4..f02d0f3c 100644
>> --- a/lib/intel_batchbuffer.c
>> +++ b/lib/intel_batchbuffer.c
>> @@ -617,6 +617,7 @@ static uint32_t fast_copy_dword0(unsigned int
>src_tiling,
>>  		dword0 |= XY_FAST_COPY_SRC_TILING_X;
>>  		break;
>>  	case I915_TILING_Y:
>> +	case I915_TILING_4:
>>  	case I915_TILING_Yf:
>>  		dword0 |= XY_FAST_COPY_SRC_TILING_Yb_Yf;
>>  		break;
>> @@ -633,6 +634,7 @@ static uint32_t fast_copy_dword0(unsigned int
>src_tiling,
>>  		dword0 |= XY_FAST_COPY_DST_TILING_X;
>>  		break;
>>  	case I915_TILING_Y:
>> +	case I915_TILING_4:
>>  	case I915_TILING_Yf:
>>  		dword0 |= XY_FAST_COPY_DST_TILING_Yb_Yf;
>>  		break;
>> @@ -653,9 +655,11 @@ static uint32_t fast_copy_dword1(unsigned int
>src_tiling,
>>  {
>>  	uint32_t dword1 = 0;
>>
>> -	if (src_tiling == I915_TILING_Yf)
>> +	if (src_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
>> +		/* Repurposed as Tile-4 on DG2 */
>>  		dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
>> -	if (dst_tiling == I915_TILING_Yf)
>> +	if (dst_tiling == I915_TILING_Yf || dst_tiling == I915_TILING_4)
>> +		/* Repurposed as Tile-4 on DG2 */
>>  		dword1 |= XY_FAST_COPY_DST_TILING_Yf;
>>
>>  	switch (bpp) {
>> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
>> index a488f9cf..4cf67296 100644
>> --- a/lib/intel_batchbuffer.h
>> +++ b/lib/intel_batchbuffer.h
>> @@ -210,8 +210,8 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
>>   *
>>   * They are to be used the the blitting routines below.
>>   */
>> -#define I915_TILING_Yf	3
>> -#define I915_TILING_Ys	4
>> +#define I915_TILING_Yf	(I915_TILING_LAST + 1)
>> +#define I915_TILING_Ys	(I915_TILING_LAST + 2)
>>
>>  enum i915_compression {
>>  	I915_COMPRESSION_NONE,
>> --
>> 2.17.1
>>

[igt-dev] [PATCH i-g-t v3 03/15] lib/igt_draw: Add pixel math for tile-4

[Jeevan B]

From: Matt Roper <matthew.d.roper@intel.com>

We need to implement the tile-4 math to convert x,y coordinates to
buffer offsets and vice versa for cases where we're using the CPU to
tile/detile rather than a GPU engine (e.g., the mmap_cpu and pwrite
subtests for kms_draw_crc).

The bspec description of tiling-4 is very confusing/misleading, but the
implementation here does match the tile-4 content generated by GPU
engines and recognized properly by the display controller.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/igt_draw.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 111 insertions(+), 2 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 0ca43deb..d78ecdf0 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -226,6 +226,71 @@ static int linear_x_y_to_ytiled_pos(int x, int y, uint32_t stride, int swizzle,
 	return pos / pixel_size;
 }
 
+#define OW_SIZE 16			/* in bytes */
+#define TILE_4_SUBTILE_SIZE 64		/* in bytes */
+#define TILE_4_WIDTH 128		/* in bytes */
+#define TILE_4_HEIGHT 32		/* in pixels */
+#define TILE_4_SUBTILE_WIDTH  OW_SIZE	/* in bytes */
+#define TILE_4_SUBTILE_HEIGHT 4		/* in pixels */
+
+/*
+ * Subtile remapping for tile 4.  Note that map[a]==b implies map[b]==a
+ * so we can use the same table to tile and until.
+ */
+static const int tile4_subtile_map[] = {
+	0,  1,  2,  3,  8,  9, 10, 11,
+	4,  5,  6,  7, 12, 13, 14, 15,
+	16, 17, 18, 19, 24, 25, 26, 27,
+	20, 21, 22, 23, 28, 29, 30, 31,
+	32, 33, 34, 35, 40, 41, 42, 43,
+	36, 37, 38, 39, 44, 45, 46, 47,
+	48, 49, 50, 51, 56, 57, 58, 59,
+	52, 53, 54, 55, 60, 61, 62, 63
+};
+
+static int linear_x_y_to_4tiled_pos(int x, int y, uint32_t stride, int swizzle,
+				    int bpp)
+{
+	int tile_base_pos;
+	int tile_x, tile_y;
+	int subtile_col, subtile_row, subtile_num, new_subtile_num;
+	int pixel_size = bpp / 8;
+	int byte_x = x * pixel_size;
+	int pos;
+
+	/* Modern platforms that have 4-tiling don't use old bit 6 swizzling */
+	igt_assert_eq(swizzle, I915_BIT_6_SWIZZLE_NONE);
+
+	/*
+	* Where does the 4k tile start (in bytes)?  This is the same for Y and
+	* F so we can use the Y-tile algorithm to get to that point.
+	*/
+	tile_base_pos = (y / TILE_4_HEIGHT) * stride * TILE_4_HEIGHT +
+		4096 * (byte_x / TILE_4_WIDTH);
+
+	/* Find pixel within tile */
+	tile_x = (byte_x % TILE_4_WIDTH);
+	tile_y = y % TILE_4_HEIGHT;
+
+	/* And figure out the subtile within the 4k tile */
+	subtile_col = tile_x / TILE_4_SUBTILE_WIDTH;
+	subtile_row = tile_y / TILE_4_SUBTILE_HEIGHT;
+	subtile_num = subtile_row * 8 + subtile_col;
+
+	/* Swizzle the subtile number according to the bspec diagram */
+	new_subtile_num = tile4_subtile_map[subtile_num];
+
+	/* Calculate new position */
+	pos = tile_base_pos +
+		new_subtile_num * TILE_4_SUBTILE_SIZE +
+		(tile_y % TILE_4_SUBTILE_HEIGHT) * OW_SIZE +
+		tile_x % TILE_4_SUBTILE_WIDTH;
+	igt_assert(pos % pixel_size == 0);
+	pos /= pixel_size;
+
+	return pos;
+}
+
 static void xtiled_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
 				     int swizzle, int bpp, int *x, int *y)
 {
@@ -253,6 +318,44 @@ static void ytiled_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
 	*x /= pixel_size;
 }
 
+static void tile4_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
+				    int swizzle, int bpp, int *x, int *y)
+{
+	int pixel_size = bpp / 8;
+	int tiles_per_line = stride / TILE_4_WIDTH;
+	int tile_num, tile_offset, tile_row, tile_col;
+	int tile_origin_x, tile_origin_y;
+	int subtile_num, subtile_offset, subtile_row, subtile_col;
+	int subtile_origin_x, subtile_origin_y;
+	int oword_num, byte_num;
+
+	/* Modern platforms that have 4-tiling don't use old bit 6 swizzling */
+	igt_assert_eq(swizzle, I915_BIT_6_SWIZZLE_NONE);
+
+	/* Calculate the x,y of the start of the 4k tile */
+	tile_num = tiled_pos / 4096;
+	tile_row = tile_num / tiles_per_line;
+	tile_col = tile_num % tiles_per_line;
+	tile_origin_x = tile_col * TILE_4_WIDTH;
+	tile_origin_y = tile_row * TILE_4_HEIGHT;
+
+	/* Now calculate the x,y offset of the start of the subtile */
+	tile_offset = tiled_pos % 4096;
+	subtile_num = tile4_subtile_map[tile_offset / TILE_4_SUBTILE_SIZE];
+	subtile_row = subtile_num / 8;
+	subtile_col = subtile_num % 8;
+	subtile_origin_x = subtile_col * TILE_4_SUBTILE_WIDTH;
+	subtile_origin_y = subtile_row * TILE_4_SUBTILE_HEIGHT;
+
+	/* Next the oword and byte within the subtile */
+	subtile_offset = tiled_pos % TILE_4_SUBTILE_SIZE;
+	oword_num = subtile_offset / OW_SIZE;
+	byte_num = subtile_offset % OW_SIZE;
+
+	*x = (tile_origin_x + subtile_origin_x + byte_num) / pixel_size;
+	*y = tile_origin_y + subtile_origin_y + oword_num;
+}
+
 static void set_pixel(void *_ptr, int index, uint32_t color, int bpp)
 {
 	if (bpp == 16) {
@@ -318,10 +421,13 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t stride, uint32_t tiling,
 							       swizzle, bpp);
 				break;
 			case I915_TILING_Y:
-			case I915_TILING_4:
 				pos = linear_x_y_to_ytiled_pos(x, y, stride,
 							       swizzle, bpp);
 				break;
+			case I915_TILING_4:
+				pos = linear_x_y_to_4tiled_pos(x, y, stride,
+							       swizzle, bpp);
+				break;
 			default:
 				igt_assert(false);
 			}
@@ -470,10 +576,13 @@ static void draw_rect_pwrite_tiled(int fd, struct buf_data *buf,
 						 swizzle, buf->bpp, &x, &y);
 			break;
 		case I915_TILING_Y:
-		case I915_TILING_4:
 			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
 						 swizzle, buf->bpp, &x, &y);
 			break;
+		case I915_TILING_4:
+			tile4_pos_to_x_y_linear(tiled_pos, buf->stride,
+						swizzle, buf->bpp, &x, &y);
+			break;
 		default:
 			igt_assert(false);
 		}
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

[Jeevan B]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

kms_draw_crc would be the first sample test to support new
format.

v2: add check for tile-4 support

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_draw_crc.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
index 82c368e1..33b7bdf4 100644
--- a/tests/i915/kms_draw_crc.c
+++ b/tests/i915/kms_draw_crc.c
@@ -41,25 +41,24 @@ drmModeConnectorPtr drm_connectors[MAX_CONNECTORS];
 struct buf_ops *bops;
 igt_pipe_crc_t *pipe_crc;
 
-#define N_FORMATS 3
-static const uint32_t formats[N_FORMATS] = {
+static const uint32_t formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB2101010,
 };
 
-#define N_MODIFIER_METHODS 3
-static const uint64_t modifiers[N_MODIFIER_METHODS] = {
+static const uint64_t modifiers[] = {
 	DRM_FORMAT_MOD_LINEAR,
 	I915_FORMAT_MOD_X_TILED,
 	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_4_TILED,
 };
 
 struct base_crc {
 	bool set;
 	igt_crc_t crc;
 };
-struct base_crc base_crcs[N_FORMATS];
+struct base_crc base_crcs[ARRAY_SIZE(formats)];
 
 struct modeset_params ms;
 
@@ -178,6 +177,9 @@ static void draw_method_subtest(enum igt_draw_method method,
 {
 	igt_crc_t crc;
 
+	igt_skip_on(modifier == I915_FORMAT_MOD_4_TILED &&
+		    !HAS_4TILE(intel_get_drm_devid(drm_fd)));
+
 	igt_skip_on(method == IGT_DRAW_MMAP_WC && !gem_mmap__has_wc(drm_fd));
 	igt_skip_on(method == IGT_DRAW_MMAP_GTT &&
 		    !gem_has_mappable_ggtt(drm_fd));
@@ -315,6 +317,8 @@ static const char *modifier_str(int modifier_index)
 		return "xtiled";
 	case I915_FORMAT_MOD_Y_TILED:
 		return "ytiled";
+	case I915_FORMAT_MOD_4_TILED:
+		return "4tiled";
 	default:
 		igt_assert(false);
 	}
@@ -328,9 +332,9 @@ igt_main
 	igt_fixture
 		setup_environment();
 
-	for (format_idx = 0; format_idx < N_FORMATS; format_idx++) {
+	for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++) {
 	for (method = 0; method < IGT_DRAW_METHOD_COUNT; method++) {
-	for (modifier_idx = 0; modifier_idx < N_MODIFIER_METHODS; modifier_idx++) {
+	for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers); modifier_idx++) {
 		igt_describe("This subtest verfies igt_draw library works "
 			     "with different modifiers, DRM_FORMATS, DRAW_METHODS.");
 		igt_subtest_f("draw-method-%s-%s-%s",
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

[Lisovskiy, Stanislav]

On Wed, Feb 16, 2022 at 03:56:22PM +0530, Jeevan B wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> kms_draw_crc would be the first sample test to support new
> format.
> 
> v2: add check for tile-4 support
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>  tests/i915/kms_draw_crc.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
> index 82c368e1..33b7bdf4 100644
> --- a/tests/i915/kms_draw_crc.c
> +++ b/tests/i915/kms_draw_crc.c
> @@ -41,25 +41,24 @@ drmModeConnectorPtr drm_connectors[MAX_CONNECTORS];
>  struct buf_ops *bops;
>  igt_pipe_crc_t *pipe_crc;
>  
> -#define N_FORMATS 3
> -static const uint32_t formats[N_FORMATS] = {
> +static const uint32_t formats[] = {
>  	DRM_FORMAT_XRGB8888,
>  	DRM_FORMAT_RGB565,
>  	DRM_FORMAT_XRGB2101010,
>  };
>  
> -#define N_MODIFIER_METHODS 3
> -static const uint64_t modifiers[N_MODIFIER_METHODS] = {
> +static const uint64_t modifiers[] = {
>  	DRM_FORMAT_MOD_LINEAR,
>  	I915_FORMAT_MOD_X_TILED,
>  	I915_FORMAT_MOD_Y_TILED,
> +	I915_FORMAT_MOD_4_TILED,
>  };
>  
>  struct base_crc {
>  	bool set;
>  	igt_crc_t crc;
>  };
> -struct base_crc base_crcs[N_FORMATS];
> +struct base_crc base_crcs[ARRAY_SIZE(formats)];
>  
>  struct modeset_params ms;
>  
> @@ -178,6 +177,9 @@ static void draw_method_subtest(enum igt_draw_method method,
>  {
>  	igt_crc_t crc;
>  
> +	igt_skip_on(modifier == I915_FORMAT_MOD_4_TILED &&
> +		    !HAS_4TILE(intel_get_drm_devid(drm_fd)));

I wonder, why we don't use format_is_supported call here. 
We anyway call it, however its done with igt_require..

Didn't we have somekind of more unified way of testing formats, only
supported by current kernel/platform?

I thought Ville did something about this..

Stan

> +
>  	igt_skip_on(method == IGT_DRAW_MMAP_WC && !gem_mmap__has_wc(drm_fd));
>  	igt_skip_on(method == IGT_DRAW_MMAP_GTT &&
>  		    !gem_has_mappable_ggtt(drm_fd));
> @@ -315,6 +317,8 @@ static const char *modifier_str(int modifier_index)
>  		return "xtiled";
>  	case I915_FORMAT_MOD_Y_TILED:
>  		return "ytiled";
> +	case I915_FORMAT_MOD_4_TILED:
> +		return "4tiled";
>  	default:
>  		igt_assert(false);
>  	}
> @@ -328,9 +332,9 @@ igt_main
>  	igt_fixture
>  		setup_environment();
>  
> -	for (format_idx = 0; format_idx < N_FORMATS; format_idx++) {
> +	for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++) {
>  	for (method = 0; method < IGT_DRAW_METHOD_COUNT; method++) {
> -	for (modifier_idx = 0; modifier_idx < N_MODIFIER_METHODS; modifier_idx++) {
> +	for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers); modifier_idx++) {
>  		igt_describe("This subtest verfies igt_draw library works "
>  			     "with different modifiers, DRM_FORMATS, DRAW_METHODS.");
>  		igt_subtest_f("draw-method-%s-%s-%s",
> -- 
> 2.17.1
> 

Re: [igt-dev] [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

[B, Jeevan]

>-----Original Message-----
>From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
>Sent: Thursday, February 17, 2022 6:21 PM
>To: B, Jeevan <jeevan.b@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Heikkila, Juha-pekka <juha-
>pekka.heikkila@intel.com>; Kahola, Mika <mika.kahola@intel.com>
>Subject: Re: [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format
>to kms_draw_crc
>
>On Wed, Feb 16, 2022 at 03:56:22PM +0530, Jeevan B wrote:
>> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>
>> kms_draw_crc would be the first sample test to support new format.
>>
>> v2: add check for tile-4 support
>>
>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> Signed-off-by: Jeevan B <jeevan.b@intel.com>
>> ---
>>  tests/i915/kms_draw_crc.c | 18 +++++++++++-------
>>  1 file changed, 11 insertions(+), 7 deletions(-)
>>
>> diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
>> index 82c368e1..33b7bdf4 100644
>> --- a/tests/i915/kms_draw_crc.c
>> +++ b/tests/i915/kms_draw_crc.c
>> @@ -41,25 +41,24 @@ drmModeConnectorPtr
>> drm_connectors[MAX_CONNECTORS];  struct buf_ops *bops;  igt_pipe_crc_t
>> *pipe_crc;
>>
>> -#define N_FORMATS 3
>> -static const uint32_t formats[N_FORMATS] = {
>> +static const uint32_t formats[] = {
>>  	DRM_FORMAT_XRGB8888,
>>  	DRM_FORMAT_RGB565,
>>  	DRM_FORMAT_XRGB2101010,
>>  };
>>
>> -#define N_MODIFIER_METHODS 3
>> -static const uint64_t modifiers[N_MODIFIER_METHODS] = {
>> +static const uint64_t modifiers[] = {
>>  	DRM_FORMAT_MOD_LINEAR,
>>  	I915_FORMAT_MOD_X_TILED,
>>  	I915_FORMAT_MOD_Y_TILED,
>> +	I915_FORMAT_MOD_4_TILED,
>>  };
>>
>>  struct base_crc {
>>  	bool set;
>>  	igt_crc_t crc;
>>  };
>> -struct base_crc base_crcs[N_FORMATS];
>> +struct base_crc base_crcs[ARRAY_SIZE(formats)];
>>
>>  struct modeset_params ms;
>>
>> @@ -178,6 +177,9 @@ static void draw_method_subtest(enum
>> igt_draw_method method,  {
>>  	igt_crc_t crc;
>>
>> +	igt_skip_on(modifier == I915_FORMAT_MOD_4_TILED &&
>> +		    !HAS_4TILE(intel_get_drm_devid(drm_fd)));
>
>I wonder, why we don't use format_is_supported call here.
>We anyway call it, however its done with igt_require..
>
>Didn't we have somekind of more unified way of testing formats, only supported
>by current kernel/platform?
>
>I thought Ville did something about this..

No, we have has_4tile other than that I don't think there is other way. 

Thanks 
Jeevan B
>
>Stan
>
>> +
>>  	igt_skip_on(method == IGT_DRAW_MMAP_WC &&
>!gem_mmap__has_wc(drm_fd));
>>  	igt_skip_on(method == IGT_DRAW_MMAP_GTT &&
>>  		    !gem_has_mappable_ggtt(drm_fd)); @@ -315,6 +317,8 @@
>static
>> const char *modifier_str(int modifier_index)
>>  		return "xtiled";
>>  	case I915_FORMAT_MOD_Y_TILED:
>>  		return "ytiled";
>> +	case I915_FORMAT_MOD_4_TILED:
>> +		return "4tiled";
>>  	default:
>>  		igt_assert(false);
>>  	}
>> @@ -328,9 +332,9 @@ igt_main
>>  	igt_fixture
>>  		setup_environment();
>>
>> -	for (format_idx = 0; format_idx < N_FORMATS; format_idx++) {
>> +	for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++)
>> +{
>>  	for (method = 0; method < IGT_DRAW_METHOD_COUNT; method++) {
>> -	for (modifier_idx = 0; modifier_idx < N_MODIFIER_METHODS;
>modifier_idx++) {
>> +	for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers);
>> +modifier_idx++) {
>>  		igt_describe("This subtest verfies igt_draw library works "
>>  			     "with different modifiers, DRM_FORMATS,
>DRAW_METHODS.");
>>  		igt_subtest_f("draw-method-%s-%s-%s",
>> --
>> 2.17.1
>>

Re: [igt-dev] [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

[Lisovskiy, Stanislav]

On Fri, Feb 18, 2022 at 10:15:31AM +0200, B, Jeevan wrote:
> >-----Original Message-----
> >From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> >Sent: Thursday, February 17, 2022 6:21 PM
> >To: B, Jeevan <jeevan.b@intel.com>
> >Cc: igt-dev@lists.freedesktop.org; Heikkila, Juha-pekka <juha-
> >pekka.heikkila@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> >Subject: Re: [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format
> >to kms_draw_crc
> >
> >On Wed, Feb 16, 2022 at 03:56:22PM +0530, Jeevan B wrote:
> >> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >>
> >> kms_draw_crc would be the first sample test to support new format.
> >>
> >> v2: add check for tile-4 support
> >>
> >> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> >> ---
> >>  tests/i915/kms_draw_crc.c | 18 +++++++++++-------
> >>  1 file changed, 11 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
> >> index 82c368e1..33b7bdf4 100644
> >> --- a/tests/i915/kms_draw_crc.c
> >> +++ b/tests/i915/kms_draw_crc.c
> >> @@ -41,25 +41,24 @@ drmModeConnectorPtr
> >> drm_connectors[MAX_CONNECTORS];  struct buf_ops *bops;  igt_pipe_crc_t
> >> *pipe_crc;
> >>
> >> -#define N_FORMATS 3
> >> -static const uint32_t formats[N_FORMATS] = {
> >> +static const uint32_t formats[] = {
> >>  	DRM_FORMAT_XRGB8888,
> >>  	DRM_FORMAT_RGB565,
> >>  	DRM_FORMAT_XRGB2101010,
> >>  };
> >>
> >> -#define N_MODIFIER_METHODS 3
> >> -static const uint64_t modifiers[N_MODIFIER_METHODS] = {
> >> +static const uint64_t modifiers[] = {
> >>  	DRM_FORMAT_MOD_LINEAR,
> >>  	I915_FORMAT_MOD_X_TILED,
> >>  	I915_FORMAT_MOD_Y_TILED,
> >> +	I915_FORMAT_MOD_4_TILED,
> >>  };
> >>
> >>  struct base_crc {
> >>  	bool set;
> >>  	igt_crc_t crc;
> >>  };
> >> -struct base_crc base_crcs[N_FORMATS];
> >> +struct base_crc base_crcs[ARRAY_SIZE(formats)];
> >>
> >>  struct modeset_params ms;
> >>
> >> @@ -178,6 +177,9 @@ static void draw_method_subtest(enum
> >> igt_draw_method method,  {
> >>  	igt_crc_t crc;
> >>
> >> +	igt_skip_on(modifier == I915_FORMAT_MOD_4_TILED &&
> >> +		    !HAS_4TILE(intel_get_drm_devid(drm_fd)));
> >
> >I wonder, why we don't use format_is_supported call here.
> >We anyway call it, however its done with igt_require..
> >
> >Didn't we have somekind of more unified way of testing formats, only supported
> >by current kernel/platform?
> >
> >I thought Ville did something about this..
> 
> No, we have has_4tile other than that I don't think there is other way. 

Can you check 87302b06b99faf42c5543908174c2606ce22443e("Generalize away copy-pasta")
commit from Ville. I think it is possible just to iterate all the formats/mods reported
by plane, thus all supported formats would be tested.
Just want to make sure we are doing the things in a most optimal way.

Stan

> 
> Thanks 
> Jeevan B
> >
> >Stan
> >
> >> +
> >>  	igt_skip_on(method == IGT_DRAW_MMAP_WC &&
> >!gem_mmap__has_wc(drm_fd));
> >>  	igt_skip_on(method == IGT_DRAW_MMAP_GTT &&
> >>  		    !gem_has_mappable_ggtt(drm_fd)); @@ -315,6 +317,8 @@
> >static
> >> const char *modifier_str(int modifier_index)
> >>  		return "xtiled";
> >>  	case I915_FORMAT_MOD_Y_TILED:
> >>  		return "ytiled";
> >> +	case I915_FORMAT_MOD_4_TILED:
> >> +		return "4tiled";
> >>  	default:
> >>  		igt_assert(false);
> >>  	}
> >> @@ -328,9 +332,9 @@ igt_main
> >>  	igt_fixture
> >>  		setup_environment();
> >>
> >> -	for (format_idx = 0; format_idx < N_FORMATS; format_idx++) {
> >> +	for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++)
> >> +{
> >>  	for (method = 0; method < IGT_DRAW_METHOD_COUNT; method++) {
> >> -	for (modifier_idx = 0; modifier_idx < N_MODIFIER_METHODS;
> >modifier_idx++) {
> >> +	for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers);
> >> +modifier_idx++) {
> >>  		igt_describe("This subtest verfies igt_draw library works "
> >>  			     "with different modifiers, DRM_FORMATS,
> >DRAW_METHODS.");
> >>  		igt_subtest_f("draw-method-%s-%s-%s",
> >> --
> >> 2.17.1
> >>

Re: [igt-dev] [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

[B, Jeevan]

>-----Original Message-----
>From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
>Sent: Friday, February 18, 2022 3:46 PM
>To: B, Jeevan <jeevan.b@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Heikkila, Juha-pekka <juha-
>pekka.heikkila@intel.com>; Kahola, Mika <mika.kahola@intel.com>
>Subject: Re: [PATCH i-g-t v3 04/15] igt/tests: Add support for Tile4(TileF) format
>to kms_draw_crc
>
>On Fri, Feb 18, 2022 at 10:15:31AM +0200, B, Jeevan wrote:
>> >-----Original Message-----
>> >From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
>> >Sent: Thursday, February 17, 2022 6:21 PM
>> >To: B, Jeevan <jeevan.b@intel.com>
>> >Cc: igt-dev@lists.freedesktop.org; Heikkila, Juha-pekka <juha-
>> >pekka.heikkila@intel.com>; Kahola, Mika <mika.kahola@intel.com>
>> >Subject: Re: [PATCH i-g-t v3 04/15] igt/tests: Add support for
>> >Tile4(TileF) format to kms_draw_crc
>> >
>> >On Wed, Feb 16, 2022 at 03:56:22PM +0530, Jeevan B wrote:
>> >> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> >>
>> >> kms_draw_crc would be the first sample test to support new format.
>> >>
>> >> v2: add check for tile-4 support
>> >>
>> >> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> >> Signed-off-by: Jeevan B <jeevan.b@intel.com>
>> >> ---
>> >>  tests/i915/kms_draw_crc.c | 18 +++++++++++-------
>> >>  1 file changed, 11 insertions(+), 7 deletions(-)
>> >>
>> >> diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
>> >> index 82c368e1..33b7bdf4 100644
>> >> --- a/tests/i915/kms_draw_crc.c
>> >> +++ b/tests/i915/kms_draw_crc.c
>> >> @@ -41,25 +41,24 @@ drmModeConnectorPtr
>> >> drm_connectors[MAX_CONNECTORS];  struct buf_ops *bops;
>> >> igt_pipe_crc_t *pipe_crc;
>> >>
>> >> -#define N_FORMATS 3
>> >> -static const uint32_t formats[N_FORMATS] = {
>> >> +static const uint32_t formats[] = {
>> >>  	DRM_FORMAT_XRGB8888,
>> >>  	DRM_FORMAT_RGB565,
>> >>  	DRM_FORMAT_XRGB2101010,
>> >>  };
>> >>
>> >> -#define N_MODIFIER_METHODS 3
>> >> -static const uint64_t modifiers[N_MODIFIER_METHODS] = {
>> >> +static const uint64_t modifiers[] = {
>> >>  	DRM_FORMAT_MOD_LINEAR,
>> >>  	I915_FORMAT_MOD_X_TILED,
>> >>  	I915_FORMAT_MOD_Y_TILED,
>> >> +	I915_FORMAT_MOD_4_TILED,
>> >>  };
>> >>
>> >>  struct base_crc {
>> >>  	bool set;
>> >>  	igt_crc_t crc;
>> >>  };
>> >> -struct base_crc base_crcs[N_FORMATS];
>> >> +struct base_crc base_crcs[ARRAY_SIZE(formats)];
>> >>
>> >>  struct modeset_params ms;
>> >>
>> >> @@ -178,6 +177,9 @@ static void draw_method_subtest(enum
>> >> igt_draw_method method,  {
>> >>  	igt_crc_t crc;
>> >>
>> >> +	igt_skip_on(modifier == I915_FORMAT_MOD_4_TILED &&
>> >> +		    !HAS_4TILE(intel_get_drm_devid(drm_fd)));
>> >
>> >I wonder, why we don't use format_is_supported call here.
>> >We anyway call it, however its done with igt_require..
>> >
>> >Didn't we have somekind of more unified way of testing formats, only
>> >supported by current kernel/platform?
>> >
>> >I thought Ville did something about this..
>>
>> No, we have has_4tile other than that I don't think there is other way.
>
>Can you check 87302b06b99faf42c5543908174c2606ce22443e("Generalize away
>copy-pasta") commit from Ville. I think it is possible just to iterate all the
>formats/mods reported by plane, thus all supported formats would be tested.
>Just want to make sure we are doing the things in a most optimal way.
>
Ok, Got it now. Will the do the change.  

Thanks 
Jeevan B 

>Stan
>
>>
>> Thanks
>> Jeevan B
>> >
>> >Stan
>> >
>> >> +
>> >>  	igt_skip_on(method == IGT_DRAW_MMAP_WC &&
>> >!gem_mmap__has_wc(drm_fd));
>> >>  	igt_skip_on(method == IGT_DRAW_MMAP_GTT &&
>> >>  		    !gem_has_mappable_ggtt(drm_fd)); @@ -315,6 +317,8 @@
>> >static
>> >> const char *modifier_str(int modifier_index)
>> >>  		return "xtiled";
>> >>  	case I915_FORMAT_MOD_Y_TILED:
>> >>  		return "ytiled";
>> >> +	case I915_FORMAT_MOD_4_TILED:
>> >> +		return "4tiled";
>> >>  	default:
>> >>  		igt_assert(false);
>> >>  	}
>> >> @@ -328,9 +332,9 @@ igt_main
>> >>  	igt_fixture
>> >>  		setup_environment();
>> >>
>> >> -	for (format_idx = 0; format_idx < N_FORMATS; format_idx++) {
>> >> +	for (format_idx = 0; format_idx < ARRAY_SIZE(formats);
>> >> +format_idx++) {
>> >>  	for (method = 0; method < IGT_DRAW_METHOD_COUNT; method++) {
>> >> -	for (modifier_idx = 0; modifier_idx < N_MODIFIER_METHODS;
>> >modifier_idx++) {
>> >> +	for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers);
>> >> +modifier_idx++) {
>> >>  		igt_describe("This subtest verfies igt_draw library works "
>> >>  			     "with different modifiers, DRM_FORMATS,
>> >DRAW_METHODS.");
>> >>  		igt_subtest_f("draw-method-%s-%s-%s",
>> >> --
>> >> 2.17.1
>> >>

[igt-dev] [PATCH i-g-t v3 05/15] igt/tests: Add support for Tile4(TileF) format to kms_rotation_crc

[Jeevan B]

Adding subtest to test new tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_rotation_crc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 3f716002..50869a08 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -983,6 +983,8 @@ static const char *modifier_test_str(uint64_t modifier)
 		return "y-tiled";
 	case I915_FORMAT_MOD_Yf_TILED:
 		return "yf-tiled";
+	case I915_FORMAT_MOD_4_TILED:
+		return "4-tiled";
 	default:
 		igt_assert(0);
 	}
@@ -1041,6 +1043,8 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_90 },
 		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_180 },
 		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_270 },
+		{ I915_FORMAT_MOD_4_TILED, IGT_ROTATION_0 },
+		{ I915_FORMAT_MOD_4_TILED, IGT_ROTATION_180 },
 		{ 0, 0 }
 	};
 
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 06/15] igt/tests: Add support for Tile4(TileF) format to tests/kms_plane_multiple

[Jeevan B]

Adding subtest to test new tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_plane_multiple.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index ebadc14b..1679f7ce 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -398,6 +398,9 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
 	igt_subtest_f("atomic-pipe-%s-tiling-yf", kmstest_pipe_name(pipe))
 		test_plane_position(data, pipe, I915_FORMAT_MOD_Yf_TILED);
 
+	igt_subtest_f("atomic-pipe-%s-tiling-4", kmstest_pipe_name(pipe))
+		test_plane_position(data, pipe, I915_FORMAT_MOD_4_TILED);
+
 	igt_subtest_f("atomic-pipe-%s-tiling-none", kmstest_pipe_name(pipe))
 		test_plane_position(data, pipe, DRM_FORMAT_MOD_LINEAR);
 }
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 07/15] igt/tests: Add support for Tile4(TileF) format to tests/kms_plane_lowres

[Jeevan B]

Adding subtest to test new tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_plane_lowres.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
index 6c0fce86..3f3f77c8 100644
--- a/tests/kms_plane_lowres.c
+++ b/tests/kms_plane_lowres.c
@@ -314,6 +314,9 @@ igt_main
 			     "high and low resolution with yf-tiling.");
 		igt_subtest_f("pipe-%s-tiling-yf", kmstest_pipe_name(pipe))
 			test_planes_on_pipe(&data, I915_FORMAT_MOD_Yf_TILED);
+
+		igt_subtest_f("pipe-%s-tiling-4", kmstest_pipe_name(pipe))
+			test_planes_on_pipe(&data, I915_FORMAT_MOD_4_TILED);
 	}
 
 	igt_fixture {
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 08/15] igt/tests: Add support for Tile4(TileF) format to tests/kms_big_fb

[Jeevan B]

Extending the test to support new Tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_big_fb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/kms_big_fb.c b/tests/i915/kms_big_fb.c
index 9ebf6155..8724d606 100644
--- a/tests/i915/kms_big_fb.c
+++ b/tests/i915/kms_big_fb.c
@@ -784,6 +784,7 @@ static const struct {
 	{ I915_FORMAT_MOD_X_TILED, "x-tiled", },
 	{ I915_FORMAT_MOD_Y_TILED, "y-tiled", },
 	{ I915_FORMAT_MOD_Yf_TILED, "yf-tiled", },
+	{ I915_FORMAT_MOD_4_TILED, "4-tiled", },
 };
 
 static const struct {
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 09/15] igt/tests: Add support for Tile4(TileF) format to testdisplay

[Jeevan B]

From: Matt Roper <matthew.d.roper@intel.com>

testdisplay is a great test for manual testing/debug of Tile-4; we just
need an extra parameter to enable that tiling format.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/testdisplay.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/tests/testdisplay.c b/tests/testdisplay.c
index 54327761..e9fbd260 100644
--- a/tests/testdisplay.c
+++ b/tests/testdisplay.c
@@ -593,7 +593,7 @@ static void set_termio_mode(void)
 	tcsetattr(tio_fd, TCSANOW, &tio);
 }
 
-static char optstr[] = "3Aiaf:s:d:p:mrto:j:y";
+static char optstr[] = "3Aiaf:s:d:p:mrt4o:j:y";
 static struct option long_opts[] = {
 	{"yb", 0, 0, OPT_YB},
 	{"yf", 0, 0, OPT_YF},
@@ -612,6 +612,7 @@ static const char *help_str =
 	"  -t\tuse an X-tiled framebuffer\n"
 	"  -y, --yb\n"
 	"  \tuse a Y-tiled framebuffer\n"
+	"  -4\tuse an Tile-4 framebuffer\n"
 	"  --yf\tuse a Yf-tiled framebuffer\n"
 	"  -j\tdo dpms off, optional arg to select dpms level (1-3)\n"
 	"  -r\tprint a QR code on the screen whose content is \"pass\" for the automatic test\n"
@@ -680,6 +681,9 @@ static int opt_handler(int opt, int opt_index, void *data)
 	case OPT_YF:
 		modifier = I915_FORMAT_MOD_Yf_TILED;
 		break;
+	case '4':
+		modifier = I915_FORMAT_MOD_4_TILED;
+		break;
 	case 'r':
 		qr_code = 1;
 		break;
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 10/15] lib/igt_draw: Use XY_FAST_COLOR_BLT on DG2

[Jeevan B]

From: Matt Roper <matthew.d.roper@intel.com>

The XY_COLOR_BLT instruction used by igt_draw's blitter implementation
doesn't support F-tile (plus we've heard informally from the hardware
team that the instruction is deprecated in general).  Switch to
XY_FAST_COLOR_BLT to perform our solid fills on DG2.  This instruction
will also allow us to extend the igt_draw support to 64bit+ color depths
in the future too if we have tests that start wanting to test that.

Note that we don't currently pass enough information down to this
routine to pick an appropriate value for the smem vs lmem performance
hint bit, but that doesn't impact the output generated.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/igt_draw.c  | 107 ++++++++++++++++++++++++++++++++++++------------
 lib/intel_reg.h |   2 +
 2 files changed, 83 insertions(+), 26 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index d78ecdf0..056101b9 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -666,36 +666,91 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 	ibb = intel_bb_create(fd, PAGE_SIZE);
 	intel_bb_add_intel_buf(ibb, dst, true);
 
-	switch (buf->bpp) {
-	case 8:
-		blt_cmd_depth = 0;
-		break;
-	case 16: /* we're assuming 565 */
-		blt_cmd_depth = 1 << 24;
-		break;
-	case 32:
-		blt_cmd_depth = 3 << 24;
-		break;
-	default:
-		igt_assert(false);
-	}
+	if (IS_DG2(intel_get_drm_devid(fd))) {
+		int buf_height = buf->size / buf->stride;
+
+		switch (buf->bpp) {
+		case 8:
+			blt_cmd_depth = 0;
+			break;
+		case 16: /* we're assuming 565 */
+			blt_cmd_depth = 1 << 19;
+			break;
+		case 32:
+			blt_cmd_depth = 2 << 19;
+			break;
+		case 64:
+			/* Not used or supported yet */
+		default:
+			igt_assert(false);
+		}
+
+		switch (tiling) {
+		case I915_TILING_NONE:
+			blt_cmd_tiling = 0;
+			break;
+		case I915_TILING_X:
+			blt_cmd_tiling = 1 << 30;
+			break;
+		case I915_TILING_4:
+			blt_cmd_tiling = 2 << 30;
+			break;
+		default:
+			igt_assert(false);
+		}
+
+		pitch = tiling ? buf->stride / 4 : buf->stride;
+
+		intel_bb_out(ibb, XY_FAST_COLOR_BLT | blt_cmd_depth);
+		/* DG2 MOCS entry 2 is "UC - Non-Coherent; GO:Memory" */
+		intel_bb_out(ibb, blt_cmd_tiling | 2 << 21 | (pitch-1));
+		intel_bb_out(ibb, (rect->y << 16) | rect->x);
+		intel_bb_out(ibb, ((rect->y + rect->h) << 16) | (rect->x + rect->w));
+		intel_bb_emit_reloc_fenced(ibb, dst->handle, 0,
+					   I915_GEM_DOMAIN_RENDER, 0,
+					   dst->addr.offset);
+		intel_bb_out(ibb, 0);	/* TODO: Pass down enough info for target memory hint */
+		intel_bb_out(ibb, color);
+		intel_bb_out(ibb, 0);	/* 64 bit color */
+		intel_bb_out(ibb, 0);	/* 96 bit color */
+		intel_bb_out(ibb, 0);	/* 128 bit color */
+		intel_bb_out(ibb, 0);	/* clear address */
+		intel_bb_out(ibb, 0);	/* clear address */
+		intel_bb_out(ibb, (1 << 29) | ((pitch-1) << 14) | (buf_height-1));
+		intel_bb_out(ibb, 0);	/* mipmap levels / qpitch */
+		intel_bb_out(ibb, 0);	/* mipmap index / alignment */
+	} else {
+		switch (buf->bpp) {
+		case 8:
+			blt_cmd_depth = 0;
+			break;
+		case 16: /* we're assuming 565 */
+			blt_cmd_depth = 1 << 24;
+			break;
+		case 32:
+			blt_cmd_depth = 3 << 24;
+			break;
+		default:
+			igt_assert(false);
+		}
 
-	blt_cmd_len = (gen >= 8) ?  0x5 : 0x4;
-	blt_cmd_tiling = (tiling) ? XY_COLOR_BLT_TILED : 0;
-	pitch = (gen >= 4 && tiling) ? buf->stride / 4 : buf->stride;
+		blt_cmd_len = (gen >= 8) ?  0x5 : 0x4;
+		blt_cmd_tiling = (tiling) ? XY_COLOR_BLT_TILED : 0;
+		pitch = (gen >= 4 && tiling) ? buf->stride / 4 : buf->stride;
 
-	switch_blt_tiling(ibb, tiling, true);
+		switch_blt_tiling(ibb, tiling, true);
 
-	intel_bb_out(ibb, XY_COLOR_BLT_CMD_NOLEN | XY_COLOR_BLT_WRITE_ALPHA |
-		     XY_COLOR_BLT_WRITE_RGB | blt_cmd_tiling | blt_cmd_len);
-	intel_bb_out(ibb, blt_cmd_depth | (0xF0 << 16) | pitch);
-	intel_bb_out(ibb, (rect->y << 16) | rect->x);
-	intel_bb_out(ibb, ((rect->y + rect->h) << 16) | (rect->x + rect->w));
-	intel_bb_emit_reloc_fenced(ibb, dst->handle, 0, I915_GEM_DOMAIN_RENDER,
-				   0, dst->addr.offset);
-	intel_bb_out(ibb, color);
+		intel_bb_out(ibb, XY_COLOR_BLT_CMD_NOLEN | XY_COLOR_BLT_WRITE_ALPHA |
+			     XY_COLOR_BLT_WRITE_RGB | blt_cmd_tiling | blt_cmd_len);
+		intel_bb_out(ibb, blt_cmd_depth | (0xF0 << 16) | pitch);
+		intel_bb_out(ibb, (rect->y << 16) | rect->x);
+		intel_bb_out(ibb, ((rect->y + rect->h) << 16) | (rect->x + rect->w));
+		intel_bb_emit_reloc_fenced(ibb, dst->handle, 0, I915_GEM_DOMAIN_RENDER,
+					   0, dst->addr.offset);
+		intel_bb_out(ibb, color);
 
-	switch_blt_tiling(ibb, tiling, false);
+		switch_blt_tiling(ibb, tiling, false);
+	}
 
 	intel_bb_flush_blit(ibb);
 	intel_bb_destroy(ibb);
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 44b0d480..cb627288 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2557,6 +2557,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define XY_MONO_SRC_BLT_WRITE_ALPHA	(1<<21)
 #define XY_MONO_SRC_BLT_WRITE_RGB	(1<<20)
 
+#define XY_FAST_COLOR_BLT		((0x2<<29)|(0x44<<22)|0xe)
+
 #define XY_FAST_COPY_BLT				((2<<29)|(0x42<<22)|0x8)
 /* dword 0 */
 #define   XY_FAST_COPY_SRC_TILING_LINEAR		(0 << 20)
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 11/15] igt/tests: Add support for Tile4(TileF) format to tests/kms_addfb_basic

[Jeevan B]

Adding subtest to test new tiling format

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_addfb_basic.c | 44 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index b7b3b0f2..2fc99eb4 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -155,7 +155,6 @@ static void invalid_tests(int fd)
 		uint64_t size;
 
 		igt_require_intel(fd);
-		igt_require(gem_has_lmem(fd));
 		igt_calc_fb_size(fd, f.width, f.height,
 				DRM_FORMAT_XRGB8888, 0, &size, &stride);
 		handle = gem_create_in_memory_regions(fd, size, REGION_SMEM);
@@ -676,6 +675,47 @@ static void addfb25_ytile(int fd)
 	}
 }
 
+static void addfb25_4tile(int fd)
+{
+	struct drm_mode_fb_cmd2 f = {};
+	igt_display_t display;
+
+	igt_fixture {
+		igt_display_require(&display, fd);
+
+		gem_bo = igt_create_bo_with_dimensions(fd, 1024, 1024,
+				DRM_FORMAT_XRGB8888, 0, 0, NULL, NULL, NULL);
+		igt_assert(gem_bo);
+
+		memset(&f, 0, sizeof(f));
+
+		f.width = 1024;
+		f.height = 1024;
+		f.pixel_format = DRM_FORMAT_XRGB8888;
+		f.pitches[0] = 1024*4;
+		f.flags = DRM_MODE_FB_MODIFIERS;
+		f.modifier[0] = DRM_FORMAT_MOD_LINEAR;
+
+		f.handles[0] = gem_bo;
+	}
+
+	igt_subtest("addfb25-4-tiled") {
+		igt_require_fb_modifiers(fd);
+
+		f.modifier[0] = I915_FORMAT_MOD_4_TILED;
+		igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, &f) ==
+			   addfb_expected_ret(&display, &f));
+		if (!addfb_expected_ret(&display, &f))
+			igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id) == 0);
+		f.fb_id = 0;
+	}
+
+	igt_fixture {
+		gem_close(fd, gem_bo);
+		igt_display_fini(&display);
+	}
+}
+
 static void prop_tests(int fd)
 {
 	struct drm_mode_fb_cmd2 f = {};
@@ -826,6 +866,8 @@ igt_main
 
 	addfb25_ytile(fd);
 
+	addfb25_4tile(fd);
+
 	tiling_tests(fd);
 
 	prop_tests(fd);
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 12/15] tests/kms_frontbuffer_tracking: Add support for 4 tiling

[Jeevan B]

From: Mika Kahola <mika.kahola@intel.com>

GEN12 uses 4 tiling instead of Y tiling. Let's add support for
tiling 4.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_frontbuffer_tracking.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/tests/i915/kms_frontbuffer_tracking.c b/tests/i915/kms_frontbuffer_tracking.c
index 532bfbb9..3f4c7e1b 100644
--- a/tests/i915/kms_frontbuffer_tracking.c
+++ b/tests/i915/kms_frontbuffer_tracking.c
@@ -136,6 +136,7 @@ struct test_mode {
 		TILING_LINEAR = 0,
 		TILING_X,
 		TILING_Y,
+		TILING_4,
 		TILING_COUNT,
 		TILING_DEFAULT = TILING_X,
 	} tiling;
@@ -462,6 +463,8 @@ static uint64_t tiling_to_modifier(enum tiling_type tiling)
 		return I915_FORMAT_MOD_X_TILED;
 	case TILING_Y:
 		return I915_FORMAT_MOD_Y_TILED;
+	case TILING_4:
+		return I915_FORMAT_MOD_4_TILED;
 	default:
 		igt_assert(false);
 	}
@@ -2232,6 +2235,8 @@ static bool tiling_is_valid(int feature_flags, enum tiling_type tiling)
 	case TILING_X:
 	case TILING_Y:
 		return true;
+	case TILING_4:
+		return AT_LEAST_GEN(devid, 12);
 	default:
 		igt_assert(false);
 		return false;
@@ -3208,6 +3213,8 @@ static int opt_handler(int option, int option_index, void *data)
 			opt.tiling = TILING_X;
 		else if (!strcmp(optarg, "y"))
 			opt.tiling = TILING_Y;
+		else if (!strcmp(optarg, "4"))
+			opt.tiling = TILING_4;
 		else if (!strcmp(optarg, "l")) {
 			opt.tiling = TILING_LINEAR;
 		} else {
@@ -3351,6 +3358,8 @@ static const char *tiling_str(enum tiling_type tiling)
 		return "x";
 	case TILING_Y:
 		return "y";
+	case TILING_4:
+		return "4";
 	default:
 		igt_assert(false);
 	}
@@ -3402,9 +3411,12 @@ struct option long_options[] = {
 igt_main_args("", long_options, help_str, opt_handler, NULL)
 {
 	struct test_mode t;
+	int devid;
 
-	igt_fixture
+	igt_fixture {
 		setup_environment();
+		devid = intel_get_drm_devid(drm.fd);
+	}
 
 	for (t.feature = 0; t.feature < FEATURE_COUNT; t.feature++) {
 		if (!opt.show_hidden && t.feature == FEATURE_NONE)
@@ -3602,8 +3614,14 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
 
 					/* Tiling Y is only supported on GEN9+ */
 					if (t.tiling == TILING_Y) {
-						int devid = intel_get_drm_devid(drm.fd);
 						igt_require(AT_LEAST_GEN(devid, 9));
+						igt_require(!intel_get_device_info(devid)->has_4tile);
+					}
+
+					/* Tiling 4 is only supported on GEN12+ */
+					if (t.tiling == TILING_4) {
+						igt_require(AT_LEAST_GEN(devid, 12));
+						igt_require(intel_get_device_info(devid)->has_4tile);
 					}
 
 					if (tiling_is_valid(t.feature, t.tiling))
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 13/15] tests/kms_draw_crc: Use 4 tiling when filling framebuffer

[Jeevan B]

From: Mika Kahola <mika.kahola@intel.com>

For platforms with 4 tiling, let's use 4 tiling instead of Y tiling.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_draw_crc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
index 33b7bdf4..33fefed4 100644
--- a/tests/i915/kms_draw_crc.c
+++ b/tests/i915/kms_draw_crc.c
@@ -226,6 +226,7 @@ static void fill_fb_subtest(void)
 	int rc;
 	struct igt_fb fb;
 	igt_crc_t base_crc, crc;
+	bool has_4tile = intel_get_device_info(intel_get_drm_devid(drm_fd))->has_4tile;
 
 	igt_create_fb(drm_fd, ms.mode->hdisplay, ms.mode->vdisplay,
 		      DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_LINEAR, &fb);
@@ -248,7 +249,9 @@ static void fill_fb_subtest(void)
 	igt_assert_crc_equal(&crc, &base_crc);
 
 	if (intel_display_ver(intel_get_drm_devid(drm_fd)) >= 9) {
-		get_fill_crc(I915_FORMAT_MOD_Y_TILED, &crc);
+		get_fill_crc(has_4tile ?
+			     I915_FORMAT_MOD_4_TILED : I915_FORMAT_MOD_Y_TILED,
+			     &crc);
 		igt_assert_crc_equal(&crc, &base_crc);
 	}
 
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 14/15] tests/kms_plane_scaling: Adding Tile-4 support

[Jeevan B]

adding tile-4 changes for 2x-scaler-multi-pipe subtest to support on dg2

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_plane_scaling.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 85db11ee..1ab7e5ce 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -613,8 +613,15 @@ static void test_scaler_with_multi_pipe_plane(data_t *d)
 	igt_output_t *output1, *output2;
 	drmModeModeInfo *mode1, *mode2;
 	enum pipe pipe1, pipe2;
-	uint64_t modifier = is_i915_device(display->drm_fd) ?
-		I915_FORMAT_MOD_Y_TILED : DRM_FORMAT_MOD_LINEAR;
+	bool has_4tile = intel_get_device_info(intel_get_drm_devid(d->drm_fd))->has_4tile;
+	uint64_t modifier;
+
+	if (is_i915_device(display->drm_fd) && has_4tile)
+		modifier = I915_FORMAT_MOD_4_TILED;
+	else if (is_i915_device(display->drm_fd))
+		modifier = I915_FORMAT_MOD_Y_TILED;
+	else
+		modifier = DRM_FORMAT_MOD_LINEAR;
 
 	cleanup_crtc(d);
 
-- 
2.17.1

[igt-dev] [PATCH i-g-t v3 15/15] tests/kms_plane_scaling: Use tiling 4 if platform has support for it

[Jeevan B]

From: Mika Kahola <mika.kahola@intel.com>

Switch using tiling 4 if a platform has support for it. For DG2 tiling 4
is superseeds Y tiling.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_plane_scaling.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 1ab7e5ce..4baa8855 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -45,6 +45,7 @@ typedef struct {
 	igt_plane_t *plane3;
 	igt_plane_t *plane4;
 	bool extended;
+	bool has_4tile;
 } data_t;
 
 static int get_num_scalers(data_t* d, enum pipe pipe)
@@ -250,6 +251,9 @@ static void test_scaler_with_rotation_pipe(data_t *d, enum pipe pipe,
 	uint64_t modifier = is_i915_device(d->drm_fd) ?
 		I915_FORMAT_MOD_Y_TILED : DRM_FORMAT_MOD_LINEAR;
 
+	if (d->has_4tile)
+		modifier = I915_FORMAT_MOD_4_TILED;
+
 	igt_require(get_num_scalers(d, pipe) > 0);
 
 	igt_output_set_pipe(output, pipe);
@@ -285,7 +289,8 @@ static const uint64_t modifiers[] = {
 	DRM_FORMAT_MOD_LINEAR,
 	I915_FORMAT_MOD_X_TILED,
 	I915_FORMAT_MOD_Y_TILED,
-	I915_FORMAT_MOD_Yf_TILED
+	I915_FORMAT_MOD_Yf_TILED,
+	I915_FORMAT_MOD_4_TILED
 };
 
 static void test_scaler_with_pixel_format_pipe(data_t *d, enum pipe pipe, igt_output_t *output)
@@ -531,6 +536,7 @@ test_scaler_with_clipping_clamping_scenario(data_t *d, enum pipe pipe, igt_outpu
 	igt_pipe_t *pipe_obj = &d->display.pipes[pipe];
 	drmModeModeInfo *mode;
 	struct igt_vec tested_formats1;
+	uint64_t modifier = d->has_4tile ? I915_FORMAT_MOD_4_TILED : I915_FORMAT_MOD_Y_TILED;
 
 	igt_require(get_num_scalers(d, pipe) >= 2);
 
@@ -567,7 +573,7 @@ test_scaler_with_clipping_clamping_scenario(data_t *d, enum pipe pipe, igt_outpu
 
 			igt_create_pattern_fb(d->drm_fd,
 					      mode->hdisplay, mode->vdisplay, f2,
-					      I915_FORMAT_MOD_Y_TILED,
+					      modifier,
 					      &d->fb[2]);
 
 			__test_scaler_with_clipping_clamping_scenario(d, mode);
@@ -613,10 +619,9 @@ static void test_scaler_with_multi_pipe_plane(data_t *d)
 	igt_output_t *output1, *output2;
 	drmModeModeInfo *mode1, *mode2;
 	enum pipe pipe1, pipe2;
-	bool has_4tile = intel_get_device_info(intel_get_drm_devid(d->drm_fd))->has_4tile;
 	uint64_t modifier;
 
-	if (is_i915_device(display->drm_fd) && has_4tile)
+	if (is_i915_device(display->drm_fd) && d->has_4tile)
 		modifier = I915_FORMAT_MOD_4_TILED;
 	else if (is_i915_device(display->drm_fd))
 		modifier = I915_FORMAT_MOD_Y_TILED;
@@ -721,6 +726,8 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 		data.devid = is_i915_device(data.drm_fd) ?
 			intel_get_drm_devid(data.drm_fd) : 0;
 		igt_require(data.display.is_atomic);
+		data.has_4tile = is_i915_device(data.drm_fd) &&
+				 intel_get_device_info(intel_get_drm_devid(data.drm_fd))->has_4tile;
 	}
 
 	igt_subtest_group {
-- 
2.17.1

[igt-dev] ✗ Fi.CI.BAT: failure for DG2 platform definition and Tile 4 plane format support (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 14277 bytes --]

== Series Details ==

Series: DG2 platform definition and Tile 4 plane format support (rev3)
URL   : https://patchwork.freedesktop.org/series/99784/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11233 -> IGTPW_6635
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6635 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6635, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/index.html

Participating hosts (47 -> 46)
------------------------------

  Additional (1): fi-icl-u2 
  Missing    (2): fi-bsw-cyan shard-tglu 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6635:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@workarounds:
    - fi-rkl-guc:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-rkl-guc/igt@i915_selftest@live@workarounds.html

  
Known issues
------------

  Here are the changes found in IGTPW_6635 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-hsw-4770:        NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-blb-e6850:       [PASS][5] -> [FAIL][6] ([i915#3194])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
    - fi-icl-u2:          NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-skl-6600u:       NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live:
    - fi-skl-6600u:       NOTRUN -> [FAIL][11] ([i915#4547])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gem:
    - fi-pnv-d510:        [PASS][12] -> [DMESG-FAIL][13] ([i915#2927])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-pnv-d510/igt@i915_selftest@live@gem.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-pnv-d510/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-5:          [PASS][14] -> [DMESG-FAIL][15] ([i915#4494] / [i915#4957])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
    - fi-snb-2600:        [PASS][16] -> [INCOMPLETE][17] ([i915#3921])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_chamelium@vga-edid-read:
    - fi-skl-6600u:       NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-u2:          NOTRUN -> [SKIP][20] ([fdo#109278]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][21] ([fdo#109271]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-u2:          NOTRUN -> [SKIP][22] ([fdo#109285])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-6600u:       NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#533])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][24] ([i915#3301])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-pnv-d510:        NOTRUN -> [FAIL][25] ([fdo#109271] / [i915#2403] / [i915#4312])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-pnv-d510/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-cfl-8109u:       [DMESG-WARN][26] ([i915#203] / [i915#262] / [i915#295]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - fi-cfl-8109u:       [DMESG-WARN][28] ([i915#203] / [i915#295]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0@smem.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       [INCOMPLETE][30] ([i915#4547]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@i915_selftest@live@gt_heartbeat:
    - {fi-ehl-2}:         [DMESG-FAIL][32] -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-ehl-2/igt@i915_selftest@live@gt_heartbeat.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-ehl-2/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [INCOMPLETE][34] ([i915#3303]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-skl-6600u:       [FAIL][36] ([i915#2722] / [i915#4312]) -> [FAIL][37] ([i915#1436] / [i915#4312])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11233/fi-skl-6600u/igt@runner@aborted.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/fi-skl-6600u/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6347 -> IGTPW_6635

  CI-20190529: 20190529
  CI_DRM_11233: 7bb15e416a5fa97dcbfe36f1461939a42266831e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6635: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/index.html
  IGT_6347: 37ea4c86f97c0e05fcb6b04cff72ec927930536e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@kms_addfb_basic@addfb25-4-tiled
+igt@kms_big_fb@4-tiled-8bpp-rotate-0
+igt@kms_big_fb@4-tiled-8bpp-rotate-90
+igt@kms_big_fb@4-tiled-8bpp-rotate-180
+igt@kms_big_fb@4-tiled-8bpp-rotate-270
+igt@kms_big_fb@4-tiled-16bpp-rotate-0
+igt@kms_big_fb@4-tiled-16bpp-rotate-90
+igt@kms_big_fb@4-tiled-16bpp-rotate-180
+igt@kms_big_fb@4-tiled-16bpp-rotate-270
+igt@kms_big_fb@4-tiled-32bpp-rotate-0
+igt@kms_big_fb@4-tiled-32bpp-rotate-90
+igt@kms_big_fb@4-tiled-32bpp-rotate-180
+igt@kms_big_fb@4-tiled-32bpp-rotate-270
+igt@kms_big_fb@4-tiled-64bpp-rotate-0
+igt@kms_big_fb@4-tiled-64bpp-rotate-90
+igt@kms_big_fb@4-tiled-64bpp-rotate-180
+igt@kms_big_fb@4-tiled-64bpp-rotate-270
+igt@kms_big_fb@4-tiled-addfb
+igt@kms_big_fb@4-tiled-addfb-size-offset-overflow
+igt@kms_big_fb@4-tiled-addfb-size-overflow
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip
+igt@kms_draw_crc@draw-method-rgb565-blt-4tiled
+igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled
+igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled
+igt@kms_draw_crc@draw-method-rgb565-mmap-wc-4tiled
+igt@kms_draw_crc@draw-method-rgb565-pwrite-4tiled
+igt@kms_draw_crc@draw-method-rgb565-render-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-blt-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-render-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-blt-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled
+igt@kms_frontbuffer_tracking@fbcdrrs-tiling-4
+igt@kms_frontbuffer_tracking@fbcpsrdrrs-tiling-4
+igt@kms_frontbuffer_tracking@fbcpsr-tiling-4
+igt@kms_frontbuffer_tracking@fbc-tiling-4
+igt@kms_plane_lowres@pipe-a-tiling-4
+igt@kms_plane_lowres@pipe-b-tiling-4
+igt@kms_plane_lowres@pipe-c-tiling-4
+igt@kms_plane_lowres@pipe-d-tiling-4
+igt@kms_plane_lowres@pipe-e-tiling-4
+igt@kms_plane_lowres@pipe-f-tiling-4
+igt@kms_plane_multiple@atomic-pipe-a-tiling-4
+igt@kms_plane_multiple@atomic-pipe-b-tiling-4
+igt@kms_plane_multiple@atomic-pipe-c-tiling-4
+igt@kms_plane_multiple@atomic-pipe-d-tiling-4
+igt@kms_plane_multiple@atomic-pipe-e-tiling-4
+igt@kms_plane_multiple@atomic-pipe-f-tiling-4
+igt@kms_rotation_crc@primary-4-tiled-reflect-x-0
+igt@kms_rotation_crc@primary-4-tiled-reflect-x-180

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6635/index.html

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